Proceedings of 20 IS IEEE

International Conference on Mechatronics and Automation

August 2 - 5, Beijing, China

Based on UCC3895 phase-shift full bridge ZVZCS with

average current control closed loop simulation and design
Jie zou Chengning zhang
College of mechanical and vehicle College of mechanical and vehicle
Beijing institute of technology Beijing institute of technology
Beijing,china Beijing, China
zcyxljzj@163.com mrzhchn@bit.edu.cn
Abstract - Based on UCC3895 chips for the lagging arm series Fig.l is ZVZCS circuit structure, of which, Q1and Q3

diode ZVZCS converter's phase shifting control, combined with a constitute the leading bridge arm, Q2 and Q4 constitute the
average current control part of the compensation network for lagging bridge arm, Cr is block capacitor, which can make
feedback, it is good for soft switch, reduces the circuit switch loss, the original current ip reduce to zero, the diode 01, O2 can
improves the overall efficiency of the converter, and can achieve prevent the original current reversely increases so that the
stable performance and a fast dynamic response. Design a lagging arm can achieve zero current switching. So the leading
switching power supply for electric cars, that is, a 1.2 kW output arm is zero voltage switching, the lagging arm is zero current
of on-board DC/DC converter as an example, through the PSIM switching. Assume that all components are ideal, blocking
2
closed-loop simulation to the whole circuit, verifies the capacitor Cr is large enough, C1= C3, K Lf » Lr (K is tum
correctness of the resu It. ratio of transformer).
Key words: ZVZCS, Phase shift control,UCC3895,PSIM

simulate.

I. INTRODUCTION

The full bridge converter topology is one of the most

commonly used forms of high power, with the DC/DC
converter higher requirement for volume and power density, Vi" :

so to reduce the loss of the switch of opened and shut off,

there appears a ZVS circuit, realizing the zero voltage
switching, however, because the ZVS circuit duty ratio loss is D2

serious, may make it harder for the lagging arm to realize zero
voltage switching, so the ZVZCS converter appeared. Fig. 1 ZYZCS converter topology structure

There are many kinds of topology to realize ZVZCS. But Within a switching cycle, the working principle of the
all have shortcomings, this paper select a topology structure of circuit is as follows:
the lagging arm series diode to achieve ZVZCS, combining When Q1' Q3 turn on, the original current ip charging
UCC3895 chip and the average current control strategy, which for Cr·

can effectively achieve soft switch, reduce the switching loss, When Q1 turn off with zero voltage, due to Lf large
improve the system dynamic response and steady state. enough, regard as a constant current source, so the original
Validated by PSIM closed-loop simulation, It has great current ip approximate constant, and continue to charging for

reference value for correctness of the whole circuit design and Cn the C1 charging and the C2 discharging.
the design of PI controller. As soon as the voltage of C2 drop to zero, Q3 achieve
zero voltage opening, secondary side diodes 03 and 04 turn
II . ZVZCS Converter with Lagging Bridge Arm Series Diode on at the same time, so the transformer primary and secondary
Working Principle voltage are zero, the original current ip decreases to zero, but

978-1-4799-7098-8115/$31.00 ©2015 IEEE 2053

voltage of blocking capacitor Cr still increases. frequency of the outer loop feu is less than the current across
When primary side current ip dropped to zero, Q4 turn frequency of the inner loop feb when feu < O.lfeb both have
off with zero current. Due to the existence of reverse diode, less affect.
to keep the primary side current ip is zero, will not reversely Fig.3 is ZVZCS phase-shift full bridge converter average
flow. current control block diagram of control.
After a small delay, Qz turn on, because of the existence
of the leakage inductance Lr, the primary side current ip

cannot mutation, which is turn on of zero current. Then, the

primary side current reverse linear increases. Due to the
R,

primary side current is not enough to provide the load current,

14------'
so, 03 and 04 still open up.
'------1 H,(s)
When the primary side can provide energy for the load,
reversely charging for blocking capacitor at the same time, the Fig.3 zyzes phase-shift full bridge converter average current control block

output rectifier diode 03 shut off. diagram of control

The above Gie(s), Gue(s) is the transfer function of

III. The Principle and Design of Average Current Control current loop and voltage loop, which is realized by PI
controller. Vs is the triangle wave modulation amplitude. Rs
A. The Average Current Control Principle
is the sampling resistance. Hu(s) as the voltage sampling
In order to design a qualified switching power supply,
ratio. Gid(S) is inductive circuit transfer function. Zo (s) is
two indicator of static and dynamic must be satisfied, the
load transfer function.
average current control is control the output voltage and
output filtering inductance's current, which has a good (1)
dynamic characteristic. Fig.2 is average current control loop
diagrams. Rd -
- - Vinc i
n

Ts = 1/2fs

B. PI Parameters Design ofAverage Current Control

In this paper, the design of switch power supply is

suitable for electric vehicle with driving charge integration.
The input voltage from a battery, the output voltage to apply to
electrical equipment within the car. So input voltage Ui=336Y,
K"U,
output voltage U0 =13.7Y, the resonant inductance
Fig.2 average current control loop diagrams Lr =lOuH, which is transformer leaking inductance, load
Voltage loop's output voltage Vev as reference voltage resistance RL=O. IS6!1, output filter capacitor Co=2200uF, the
of current loop, then its value compared with current feedback switching frequency fs=70kHZ, triangle wave amplitude �
signal iLRs' and the output access control chip UCC389S , = SY, blocking capacitor of the peak voltage Vcrp= 67.2Y, the
within chip, it will be compared with a triangle wave �, then transformer turns ratio K= IS, the output rating power Po =
the PWM control signal be output, according to different input 1200W, output filter inductance Lf =8uH, output filter
to change the duty ratio so that realize the stability of the capacitor equivalent resistance RESR =2Sm!1, current
output. Current inner loop transfer function is part of the equivalent sampling resistance Rs=O.OS!1, voltage sampling
voltage open loop transfer function, in order to avoid the ratio Hu(s)=O.36S.
mutual influence of two loop, it is best for the voltage across Known expression of Cid' prototype design parameters

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into (1) type can be: The value of fei substitute into type (9) can be:
1 Gw(2 nifei)1 =
=
4308 0.127 (10)
GideS) (2)
1+s/650
So:
current open-loop transfer function before the converter I Gie(2njfei)1 = 7.85 (11)
compensation is: Ke = 7.2

= =�
Gid(s)Rs
G.to (s)
Vs 1+s/650
Firstly, design for current inner loop, PI controller is a
single zero monopole point compensation network, schematic
diagram as shown in figA, the compensating network has
higher static gain and smaller static error, which can improve
the system dynamic performance and control precision.
According to the above results. current inner loop device
(3)
parameter of compensating network is: assuming Rz=1.3Kn,
so R1 = I S0 n, C1 = 6.SnF, Cz=lnF.
Fig.S and fig.6 is current loop bode figure before
compensation and after the compensation, it can be seen that
the current inner ring through frequency is 3SkHZ, the phase
margin is about SOdeg.The low-frequency gain is much larger
than before, which can improve the control precision, so the
current loop PI controller design meet the requirements.

Fig.4 The structure ofthe PI controller

The transfer function of compensating network are as

follows:
1+s/wcz
Gic ( s) - Ke
- s/wcz(1+s/wcp)
(4)

Of which:

Gain (S)

=
1 Fig.5 Current loop frequency characteristic before the compensation
Zero point Wez --
(6)
RzC1

=
1
Pole Wep --
(7)
RzCz

Make :
The pole frequency: fep = 2.fs =140kHZ

=-
1
Through frequency: fei 4
x 2.fs =3SkHZ

Zero frequency : fez = f

O.5 ee= 17.SkHZ
Current open-loop transfer function for the inner ring:

( )
Te s = Gie(s) Gid(s)Rs (S)
Vs

Because ( )
Te s gam IS zero when it IS m through
frequency , so:

J et.)1 =
1 Fig.6 Current loop frequency characteristic after the compensation
I G.te (2nJ'F (9)
IGiO(Znj[ei)1

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 point in the half of equivalent power level fuz fup/2
= =

When the voltage loop design, the current inner loop

231.9Hz. fev O.lfei 35 00Hz.
= =

regards as a power level, as shown in fig.7. Equivalent power

=

level is ApCs), which is equivalent to fig 7. Rz Cz RESR CO

2 CRL + RESR) Co
=

RZ C1
By the same reason, we can get:
I GvoC2rrjfe;)I
=
0.263
I GueC2rrjfe;)I
=
1/0.263
=

Fig.7 current loop power level 3.8

Ku
=

Ai! is the current inner ring of the closed-loop transfer 5.9

function: So, voltage outer loop device parameter of compensating
GMGid(S)[1+Ge(s)] - 1 network is: assuming Rz =1.3Kn, so R1 = 220n, C1 =
� �
Ai! -
- - R
-s X S +l C<p
s2 +<Pw= -
- 1 -1 .5) (12)
Te(s)+1 -
0.47uF, Cz = 0.047uF.
2 2
When f «feist, Ai! � l/Rso Fig.9 and fig.lO is voltage loop bode figure of before
Zo Cs) is load transfer function: compensation and after the compensation, it can be seen that
RL(1+S/Wzo) the voltage outer ring through frequency is 3.5kHZ, the phase
ZCs)
=

1+s/wp o (13)
margin is about 90deg.The low-frequency gain is also much
Of which: larger than before, which can improve the control precision,
1 1 sop the voltage loop PI controller design meet the
wzo
= = = =
18182; Wp o 2914
�
ESR C 0 CR L + RESR) C 0 requirements.
So:

ApCs)
=
At- ! ZCs)
=
2:.. x
RL(1+S/Wzo)
(14)
Rs 1+s/wpo

T he equivalent diagram of voltage loop control is as fig.8:

Fig.8 The equivalent diagram of voltage loop control

Voltage outer loop transfer function is:

TvCs) HuCs)
CueCs) x ApCs) x
=
(14)
Voltage open-loop transfer function before the converter
compensation is Fig 9 Voltage loop frequency characteristic before the compensation

HuCs) x ApCs)
Cvo Cs)
=
(15)
Outer ring still adopt unipolar order zero voltage
compensation network
The transfer function of compensating network are as
follows:

(16)

The pole fup offset equivalent power rating physical

ESR zero point, so fup fuz 2893.8 Hz;To make zero
= =

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Fig 10 Voltage loop frequency characteristic after the compensation
IV. Simulation
A. Circuit Simulation Is Introduced
This paper choose the PSIM simulation software, PSIM
compared with other softwares, the main advantages are that
PSIM simple operation, good man-machine interface and very
powerful simulation, which can simulate for the analog circuit,
digital circuit and power electronic circuit. It also has internal
components library, which can choose directly. For design in
this paper, the simulation was conducted for the whole circuit
closed-loop simulation, only minus the drive circuit, due to the
lack ofUCC3895 components in component library, so built a
circuit which can realize phase shifting control to simulate
UCC3895. In the actual ,UCC3895 control will only better
than the effect of the simulation model.
After open the PSIM software. Firstly , create a
schematic file, due to the PSIM can directly read circuit
diagram, so, only need to put the main circuit and control
circuit in the schematic drawing, which can add to the voltage
and current probes in where we need to know voltage or
current. After the drawing is completed, click the button of
simulate then select simulate control, set the run time about
O.Ols, step length is O.lus.You can then run the simulation.
After the completion of the operation, select the voltage or
current that you want to know so that see the corresponding
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waveform.
B. UCC3895 Simulation Model In PSIM
UCC3895 PSIM simulation model is as follows in fig. 11,
it is use the output single compared with a rectangular wave,
then get the signal into two trigger and get four PWM signals.
Fig.ll UCC3895 simulation model
Terminal output of main circuit connected to a
comparator's positive input, comparing with reverse input
rectangular wave, the rectangular wave frequency is 2 times of
the switching frequency, is 140kHZ, the voltage amplitude is
set to 5V, on the one hand, the output of the comparator direct
access T' trigger which is transformed by D trigger. T'
trigger is equivalent to the D trigger's D port connected to the
Q port, when comparator has a clock pulse every time, turn
again. On the other hand, the output of the comparator through
a NOT gate, then access to T' trigger. Every trigger each
output terminal is direct access to the AND door first, and then
after a delay time to access AND gate, the delay time is dead
zone time, set to 0.5us. Finally, through an on-off controller,
which is necessary for driving MOSFET in PSIM so that
output the four road PWM wave.
C. The Results ofSimulation
Simulation results are as follows in fig.12, from above to
below respective leading bridge arm driving waveform, the
lagging bridge arm driving waveform. The simulation results
is recorded when state of output current and voltage stability.
This is means the switch state is stable. Two driving signals is
complementary which can be seen from the diagram, and there
is a dead zone time, the leading bridge arm switch is the zero
voltage, the lagging bridge arm switch belongs to the zero
current, which achieve the four zero switching, so reduce the
switching loss and improve the efficiency.
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Fig.13 Output voltage and current
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v . Conclusion
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According to a scheme introduced in this article, Using [ 14] Unitrode application note, UCI875/2875/3875/3895 phase shift resonnat

UCC3895 chip and average current control mode to control controller.

lagging bridge arm series diode circuit, from the simulation

results , we can see it is good for soft switch, reduce the switch
switching loss and has good dynamic response performance.
the output voltage and current also satisfy the requirements of
design.

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