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Double-Loop Stabilization System of 2Xwsxw9Rowdjhri+Ljk9Rowdjh3Rzhu6Xsso/Iru Powerful Travelling Wave Tube
Double-Loop Stabilization System of 2Xwsxw9Rowdjhri+Ljk9Rowdjh3Rzhu6Xsso/Iru Powerful Travelling Wave Tube
Abstract±7KHSDSHUGHVFULEHVVFKHPHVWRVWDELOL]HRIWKHRXWSXW DQG DUH IUHTXHQWO\ XVHG IURP DOO YDULHW\ RI VFKHPHV
YROWDJH RI WKH KLJKYROWDJH SRZHU VXSSOLHV IRU WKH SRZHUIXO which kept voltage stabilization of the delay system of TWT
WUDYHOLQJZDYHWXEHV,WLVVKRZQWKDWWKHFRQVLGHUHGVFKHPHV according to the type of using structure of regulation of
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output voltage [1].
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QRQH RI WKHVH VFKHPHV SURYLGHV WKH UHOLDEOH SRZHU VXSSO\ voltage multiplier, which also performs the function of
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of the voltage multiplier from 0 to the maximum value, then The structural scheme of stabilization system is shown in
this scheme is capable to operate over the wide range of Figure 3. The main (fast-acting) control loop is shown by
disturbances. Figure 1 shows that the control element is not WKLFNHQHGOLQHLQWKH¿JXUHDQGLWFRQVLVWVRIWKHDPSOL¿HURI
affected directly on the output value, but through the voltage error signal 1, the regulator 2, the adder 10 which performs
PXOWLSOLHUDQGWKH¿OWHULQVHULHV7KHVHHOHPHQWVKDYH subtraction of the voltage drop at the control element 2
a substantial inertia as compared with other elements, and IURPWKHYROWDJHDWWKHYROWDJHPXOWLSOLHUWKH¿OWHUWKH
therefore they mainly determine the rapidity of the system. GLYLGHURIWKHIHHGEDFNYROWDJHRIWKHRXWSXWYROWDJHDQG
The stabilized power supply of the delay system of the setpoint U0. The operation of this loop is fully consistent
7:7ZLWKWKHFRQWURORQWKHVLGHRIUHFWL¿HGKLJKYROWDJH with the scheme 2.
VFKHPH RSHUDWHV GLIIHUHQWO\ 7KH UHFWL¿HG DQG ¿OWHUHG
mains voltage supplied is converted by the inverter into
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which are transformed then, and thereby galvanic isolation
of network circuits and load circuits are performed. Then,
the secondary voltage of the transformer is converted by
the voltage multiplier 3 into the constant high voltage.
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reference voltage are compared; the result of comparing
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element 2. The high voltage FET or MOSFET is used as this
control element. The circuit of the drain-source (collector-
emitter) of this transistor is switched into the circuit of the Fig. 3. The structural scheme of the double-loop stabilization system of an
load current and the voltage multiplier 3 in series. Through output voltage of high-voltage power supply of the delay system of TWT.
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difference between the voltage multiplier 3 and the control The additional control loop, which has a lower rapidity,
element 2. So the output voltage of the power supply of the consists of the voltage multiplier 3, the second control
delay system is formed. This is the scheme with regulation HOHPHQW WKH VHFRQG DPSOL¿HU RI GLIIHUHQFH VLJQDO WKH
RQWKHVLGHRIWKHUHFWL¿HGKLJKYROWDJH second divider of the feedback voltage 9 and the setpoint
The serial connection of the low-inertia control element U0’. The operation of this loop is consistent with the scheme
(transistor) and the load achieves high rapidity and low 1.
dynamic output impedance of the supply. %RWK FRQWURO ORRS KDYH DQ LQÀXHQFH RQ WKH RXWSXW
It was found that the falling of the output voltage for the voltage U +HUHZLWK WKLV IDVWDFWLQJ ORRS ZLWK D OLPLWHG
VFKHPHLVDERXWDQGIRUWKHVFKHPH±DERXW range of adjustment compensates for the part of the error
with the pulse load and the duration of the leading edge of İ1 7KH DGGLWLRQDO ORRS PRQLWRUV WKH YROWDJH DW
QVDQGWKHYDOXHRIWKH¿OWHUFDSDFLWDQFHRIQ)DVD the control element of the main loop, and comparing it to
result of the simulation, which was made by the simulation the setpoint U0’, generates the voltage at the output of the
package Micro-Cap. The amplitude of the pulsation of the voltage multiplier UVM with a delay, to compensate for the
RXWSXWYROWDJHFDXVHGE\RSHUDWLQJRIWKHUHFWL¿HUYROWDJH rest part of the error, preventing the output of the voltage of
multiplier) for the scheme 2 is about 7 times less than for the the regulator of the main loop from its control range.
scheme 1 with the maximum continuous load current of 70 The open mode is realized when the regulator voltage of
P$DQGWKHYDOXHRIWKH¿OWHUFDSDFLWDQFHQ) the main loop is out of its range because the feedback is torn
Further research showed that the scheme 1 has a RII+HUHZLWKWKLVHUURURIUHJXODWLRQİ2LVDOPRVWHTXDOWRWKH
VLJQL¿FDQWO\ODUJHUDQJHRIWKHFRQWURORIWKHRXWSXWYROWDJH setpoint U0’, which leads to a rapid increase of the output
WRWKDQWKHVFKHPH,QWXUQWKHVFKHPHKDVD voltage, and therefore, to the restoration of the main mode
YHU\QDUURZFRQWUROUDQJHZKLFKLVOLPLWHGE\FRQWURO of operation of the transistor and to the return to the main
transistor parameters and the voltage of supply. mode of stabilization.
So, none of these schemes provides the reliable power A feature of the system of stabilization according to Figure
supply in whole set of load conditions and conditions of LVWKHSUHVHQFHRIWZRYROWDJHVHWSRLQWVPDLQU0 principal
changing of parameters of the mains. for the entire system and additional U0’ for control the
,QWKLVFRQQHFWLRQLWLVLQWHUHVWLQJWR¿QGWKHVROXWLRQRI voltage at the control element of the main loop. The value
the problem of ensuring the reliable power supply in whole U0’ is determined by the value of the desired output voltage
sets which have the practical importance. to the greatest extent, i.e. the value of U0+RZHYHUWKHORDG
current IL and the voltage of supply USLVLQÀXHQFHGRQWKH
optimum value of the setpoint U0’. Both these values vary
III. T+(25< in the process of functioning of the system, that’s why the
This problem can be solved by the synthesis of the system rigid setting of U0’ leads to the deviation of its parameters
of stabilization which combines both methods of control from the optimal values. In this regard, the fuzzy regulator
used in viewed schemes [2]. [3] has been introduced into the system of stabilization. It
18th INTERNATIONAL CONFERENCE ON MICRO/NANOTECHNOLOGIES AND ELECTRON DEVICES EDM 2017
provides the automatic setting of the value U0’ depending ,Q WKLV H[DPSOH LW ZDV HQRXJK WR FRQ¿QH E\ WKH WKUHH
on the determined value U0 and the changing of the values IL WHUPVHWVIRUHDFKRI/3
and the voltage of supply US.
The fuzzy regulator is designed so that it performs the ɌLC VPDOOI1) + normal (I2) + great (I3);
IXQFWLRQ RI WKH ÀH[LEOH FRHI¿FLHQW RI WKH YLUWXDO ³YROWDJH ɌSV VPDOOU1) + normal (U2) + great (U3);
divider” k(IL, US) which depends on values of IL and US. Ɍk VPDOOk1) + normal (k2) + great (k3).
Thus, the optimal value U0’ is realized at any current values
RIWKHVHYDULDEOHV Membership functions for fuzzy values “small”, “medium”
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U 0 ' k ( I L ,U S ) U 0 . Inference rules, that are fuzzy statements, construct under
WKHVFKHPHRIORJLFDOLPSOLFDWLRQ,)±7+(17KHUXOHIRU
7KH VFKHPH RI UHDOL]DWLRQ RI WKH FRHI¿FLHQW WKH YLUWXDO the output logic variable k is of the form when we have two
³YROWDJHGLYLGHU´LVVKRZQLQ)LJXUH input logical variables IL and US
,Q)LJXUH±IX]]\UHJXODWRU±GHYLFHRIPXOWLSOLFDWLRQ TABLE I
Linguistic variables (LV) are introduced for formulating TABLE OF INFERENCE RULES OF The F8==<R(*8/$725
RI LQIHUHQFH UXOHV RI WKH IX]]\ UHJXODWRU ³ORDG FXUUHQW´ SV U1 U2 U3
(hereafter LC), “mains voltage” (SV³GLYLGHUFRHI¿FLHQW´
(k 7KH\ FRUUHVSRQG WR WKH SK\VLFDO TXDQWLWLHV LC – the LC
value of the load current, SV – the current value of the mains I1 k1 k1 k2
voltage, k±FRHI¿FLHQWRIGLYLVLRQ I2 k1 k2 k3
/9 ZHUH XVHG LQ WKH IRUP ^³1DPH´ 7 +` WR VLPSOLI\ I3 k2 k3 k3
the task, here T – term-set, N – set of fuzzy numbers,
corresponding to the elements T, and fuzzy numbers of LR- IV. EXPERIMENTAL RESULTS
type were used for setting values of LP.
The research of the proposed double loop stabilization
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have been carried out. Figure 6 shows the comparative results
of the reaction of the discussed stabilization systems on the
increment of maximum load for the double loop system. We
considered the heaviest mode of work of the systems with
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It must be concluded that the double loop stabilization
system has the lesser order of magnitude of the output voltage
at the changing of any disturbance based on the analysis
of the graphes 1 and 3, Figure 6. The results of simulation
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impossibility of its using when the output voltage is greater
than 6 kV. The simulation was made when the supply voltage
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V. DISCUSSION OF RESULTS
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of TWT is achieved by using the double loop stabilization
system of the output voltage in all sets of the load modes
)LJ0HPEHUVKLSIXQFWLRQVRIIX]]\QXPEHUVto set the values of the LV. and the mains. It is superior to existing systems to reduce of
the voltage dip due to increment of the load of 70 mA from
18th INTERNATIONAL CONFERENCE ON MICRO/NANOTECHNOLOGIES AND ELECTRON DEVICES EDM 2017
REFERENCES
[1] /DQFRY 9 9ODGLPLURY ( +LJKYROWDJH SRZHU VXSSOLHV 3DUW
3RZHUHOHFWURQLFV±±ʋ±3LQ5XVVLDQ
[2] Kalistratov N.A., Mityashin N.P. Modeling of double-loop
stabilization output voltage system of power supply of delay system
RI SRZHUIXO WUDYHOLQJ ZDYH WXEHV 3UDFWLFDO SRZHU HOHFWURQLFV ±
±ʋ±3LQ5XVVLDQ
[3] 0DPGDQL(+$VVLOLDQ6$QH[SHULPHQWLQOLQJXLVWLFV\QWKHVLVZLWK
IX]]\ORJLFFRQWUROOHU,QW-0DQ0DFKLQH6WXGLHV±±9RO
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