Biasing methods for MOSFET

Unit I
Lecture III

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 Biasing of MOSFET

• To operate the MOSFET as an amplifier, the saturation-mode

segment of the transfer curve must be used

• To operate the MOSFET as switch triode and cut-off region is used

• The device is biased at a point located somewhere close to the

middle of the curve

• DC bias point - Quiescent point

• The voltage signal to be amplified is then superimposed on the dc

voltage

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 Operation of the enhancement NMOS transistor
as vDS is increased

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• Increasing vDS, the current through the channel remains
constant at the value reached for vDS= vGS – Vt
• Drain current thus saturates at this value, MOSFET is said to
have entered the saturation region of operation
vDSsat = vGS - Vt
• Obviously, for every value of vGS > Vt, there is a
corresponding value of vDSsat
• The device operates in the saturation region if vDS> vDSsat
• The region of the iD-vDS characteristic obtained for vDS < vDSsat
is called the triode region
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 Derivation of iD – vDS characteristic

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• Expression for the iD-vDS characteristic in the saturation region

where Vt - Threshold voltage

µn - Mobility of electrons in the channel
Cox - Oxide Capacitance
W/L - Transistor aspect ratio (ratio of the channel width W
to the channel length L)
• The expression simply gives the saturation value of iD
corresponding to the given vGS
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• If the capacitance per unit gate area is denoted Cox and the thickness
of the oxide layer is tox, then

Cox = ox / tox

where ox is the permittivity of the silicon oxide,

• ox = 3.90 = 3.9 x 8.854 x 10-12 = 3.45 x 10-11 F/m

• The oxide thickness tox is determined by the process technology used

to fabricate the MOSFET

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• is constant determined by the process technology used
to fabricate the n-channel MOSFET

• It is known as the process transconductance parameter

• It determines the value of the MOSFET transconductance,

and has the dimensions of A/V2

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 Characteristic curve

• The basic control action of the

MOSFET is that changes in vGS
give rise to changes in iD
• A resistor RD to obtain an output
voltage vo,
v0 = vDS = VDD - RDiD

Fig. Basic structure of CS amplifier

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• Operation of the CS circuit is governed by

– MOSFET's iD-vDS characteristics

– Relationship between iD and vDS imposed by connecting the

drain to the power supply VDD via resistor RD

vDS = VDD – RDiD

𝑫𝑫
• Or equivalently,
𝑫 𝑫

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 Characteristic curve of CS amplifier

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• Observe from the characteristic curve that the straight line
intersects the vDS-axis at VDD

• In above equation vDS = VDD at iD = 0 or vDS = 0

• Has a slope of -1/RD

• Since RD is the load resistor of the amplifier, the straight line

in characteristic curve is known as the load line

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• Since vGS = vi, for vI < Vt, the transistor will be cut off, iD will
be zero, and v0 = vDS = VDD

• Operation will be at the point labeled A

• As VI exceeds Vt, the transistor turns on, iD increases, and v0

decreases

• Since v0 will initially be high, the transistor will be operating

in the saturation region (load line from A to B)

• This particular point in this region of operation is labeled as Q

• It is obtained for VGS = VIQ and has the coordinates V0Q =

VDSQ and IDQ
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• Saturation-region operation continues until v0 decreases to the
point that it is below vI by Vt volts

• At this point, vDS = vGS - Vt and the MOSFET enters its triode
region of operation

• This is indicated by point B, which is at the intersection of the

load line

• Point B is defined by V0B= VIB-Vt

• For vI > VIB, the transistor is driven deeper into the triode
region

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 Biasing of MOSFET

• By keeping vi sufficiently small to restrict the operation to an

almost linear segment of the transfer curve, the resulting
output signal vo will be proportional to vi

• Three regions in characteristic curve

1. Cutoff region

2. Saturation region

3. Triode region

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 Transfer characteristic showing operation as
an amplifier biased at point Q

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 Biasing of MOSFET

1. Cut off region, XA

vi  Vt, and vo = VDD

2. Saturation region, AQB

vi  Vt, and vo  vi - Vt

3. Triode region, BC

vi  Vt, and vo  vi - Vt

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 Biasing methods
• The bias point is characterized by
– Stable and predictable dc drain current ID
– DC drain-to-source voltage VDS
• To ensure the operation in the saturation region for all
expected input signal levels
1. Biasing by fixing VGS
2. Biasing by fixing VG and connecting a resistance in the
source
3. Biasing using a Drain-to-Gate feedback resistor
4. Biasing using a constant current source
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 Biasing by fixing VGS

• Approach to fix the Gate-to-

Source voltage VGS to the
value required to provide the
desired ID

• VGS value can be derived from

the power supply voltage VDD
through the use of an
appropriate voltage divider

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 Biasing by fixing VGS

• Not a good approach

• Reasons:

– Threshold voltage Vt, Oxide Capacitance Cox, and

Transistor aspect ratio W/L vary widely among devices of
same size and type

– Both Vt and n depend on temperature

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 Biasing by fixing VGS
• If the VGS value is fixed, the drain current ID becomes very
much temperature dependent

Large variability in the value of ID for fixed VGS

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 Biasing by fixing VG and connecting a
resistance in the source
• Excellent biasing technique
– Fix the dc voltage at the gate, VG
– Connect a resistance in the source lead

VG = VGS + RS ID

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 Biasing by fixing VG and connecting a
resistance in the source
• Reduced variability

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 Biasing by fixing VG and connecting a
resistance in the source

• If VG is much greater than VGS, ID will be mostly determined

by the values of VG and RS

• Even if VG is not much larger than VGS, Resistor RS provides

negative feedback, which acts to stabilize the value of bias
current ID
VG = VGS + RS ID

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 Biasing by fixing VG and connecting a
resistance in the source

• Eqn indicates that since VG is constant, VGS will have to

decrease
– Results in a decrease in ID

• Thus the action of RS works to keep ID as constant as possible

• RS - degeneration resistance - due to the negative feedback it

provides

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 Biasing by fixing VG and connecting a
resistance in the source
• Possible practical implementations

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 Biasing using a Drain-to-Gate Feedback
resistor
• Simple and effective discrete-circuit biasing arrangement
• Utilizes a feedback resistor connected between the drain and
gate

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 Biasing using a Drain-to-Gate Feedback
resistor
• Large feedback resistance RG (M range) forces the dc voltage at
the gate to be equal to that at drain ( IG = 0)
VGS = VDS = VDD - RDID
VDD = VGS + RDID
• If ID for some reason changes (increases), eqn indicates that VGS
must decrease
• The decrease in VGS in turn causes a decrease in ID , a change i.e
opposite direction to the one originally assumed
• Thus the negative feedback or degeneration provided by RG works
to keep the value ID as constant as possible
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 Biasing using a Drain-to-Gate Feedback
resistor

• Drawback
– Limited output voltage signal swing

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 Biasing using a constant current source

• Most effective scheme

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Fig. (b) Implementation of I using 30
Fig. (a) Biasing current mirror
 Biasing using a constant current source
• RG (in M range )

– Establishes a dc ground at the gate

– Presents a large resistance to an input signal source that can

be capacitively coupled to the gate

• RD

– Establishes an appropriate dc voltage at the drain to allow

for the required output signal swing

– Ensures that the transistor always remains in the saturation

region
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 Current mirror

• The drain of Q1 is shorted to its gate and thus is operating in

the saturation region such that

• Drain current of Q1 is supplied by VDD through resistor R

• Since the gate currents are zero,

• IREF - current through R - Reference current of current source

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 Current mirror
• If the parameter values of Q1 and desired value for IREF are given, Eqns
(A), (B) can be used to determine the value of R
– Q2 has same VGS as Q1
• If Q2 is operating in saturation (assume), its drain current which is the
desired current I of the current source will be

• From Eqns (B) and (C),

• I is related to IREF by the ratio of aspect ratios of Q1 and Q2

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