IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS AIND CONTROL INSTRUMENTATION, VOL. IECI-25, NO. 1, FEB.

1978 45

figuration space) and the probable holding time spent in each
region is incorporated into the controller. This information
is used in conjunction with the plant measurements to learn
which region the plant is in, so that the proper control can be
applied.
The structure of the controller is a bank of Kalman filters
each matched to a region of the configuration space. The
filter estimates are multiplied by correspoonding feedback
gains (different regions require different gains) and the overall
state variable feedback to the plant is computed as a weighted
sum of the individual feedback values.
The number of regions used in the formulation of the con-
troller depends on the design criteria and on the nature of the
nonlinear system itself. For example, a larger operational
range or better accuracy will require more regions. The type
and magnitude of the nonlinearity will also influence the num-
ber of regions. It is necessary that the domain of attraction
of adjacent regions be overlapping in order to drive from one
region to another; however, this last requirement is usually
satisfied if the number of regions is chose'n solely to give
reasonably good accuracy.
Each Kalman filter operates independently on the current
measurement, thus making this controller amendable to
parallel processing. In addition, the filter gains can be precom-
puted and stored in tabular format (unlike most nonlinear
filters, such as the "extended Kalman filter [8] "). These two
advantages yield a very low execution time for the imple-
mented controller.
The nonlinear oscillator example reported herein represents
a significant control problem due to the rapid movement of
the state between regions. The results have been very encour-
aging, even for large levels of noise. Plans are already under-
way for the application of this type of controller to nonlinear
stochastic systems of medium order (4-12).
REFERENCES
[1] O.- J. Oaks and G. Cook, 'Piecewise linea control of nonlinear
systems," IEEE Trans. IECI, vol. 23, no. 1 'pp. 56-63.
[2] H. F. VanLandingham and R. L, Moose, "'Digital control of high
performance aircraft using adaptive estimation techniques," IEEE
Trans. AES, vol. 12, no. 2, March 1977.
[3] P. E. Zwicke, R. L. Moose, and H. F. VanLandingham, "Estimation
for nonlinear systems," Proc. 9th Southeastern Symposim on Sys-
tem Theory, UNCC, Charlotte, NC., March 1977.
[4] H. F. VanLandingham, R. L. Moose, and P. E, Zwicke, "Control
of nonlinear stochastic systems using adaptive estimation," South-
eastcon Proceedings, Williamsburg, VA., April 1977.
[5l R. L. Moose and P. E. Wang, "An adaptive estimatQr with learning
for a plant con'taining semi-Markov switching parameters," IEE
Trans. SMC, vol. 3, May 1973.
[6] D. G. Lainiotis, "Partitioning: A unifying famework for adaptive
systems, II: Control," IEEE Proceedings, August, 1976.
[7] R. A. Howard, "System analysis of semi-Markov processes," IE
Trans. vol. ME-8, April 1964,
[8] A. Gielb, et al., Applied Optimal 4stimation, MIT Press, Cambridge,
MA., 1974, Chap. 6.
[9] J. S. Meditch, Stochastic Optimal Linear Estimation and ControI,
McGraw-Hill Book Co., New York, 1969 Chap. 5.

t iring Circuit or ree-rbase

yristor-Bridge Rectifier
B. ILANGO, R. KRISHNAN, R. SUBRAMANIAN, AND S. SADASIVAM

Abstract-Existing firing schemes for the firing of three-phase SCR INTRODUCTION

bridge rectifiers used for industrial applications employ equidistant
T"HE INDIVIDUAL phase control of three-phase rectifiers
firing pulses. Mostly they consist of six identical phase control circuits.
In this paper a compact scheme using minimum integrated circuit com- for industrial applications [1] uses a large number of
ponents is described. It has a fast response for triggering angle correc- components. But it has an advantage in the form of minirnum
tion andd gives a full range control of voltage. delay of one sixth of a period for the corrections of the firing
Manuscript received September 28, 1976; revised March 30, 1977. angle. An economic equidistant pulse firing scheme [21 utiliz-
B. Ilango is with the Department of Power Systems Engineering, ing minimum components using integrated circuit chips has
College of Engineering, Guindy, Madras 600025, India. given insignificant error in the equidistant spacings in the firing
R. Krishnan and R. Subramanian are with the Department of Electri-
cal Engineering, College of Engineering, Guindy, Madras 600025, India. angle and simpler generation of synchronized and phase
S. Sadasivam is with the Department of Electrical Engineering, controlled pulse train in comparison to other existing schemnes.
Central Polytechnic, Madras 600020, India. The chief disadvantage of the above scheme is its inability to
0018-9421/78/0200-0045$00.75 C 1978 IEEE
46 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS AND CONTROL INSTRUMENTATION, VOL. IECI-25, NO. 1, FEB. 1978
4 6 2]
3' CONTROLLED RE(!CTIFIER
Fig. 1. 30 full-wave controlled rectifier firing circuit-block diagram.
correct the firing angle within a time of one period of ac
supply.
The ripples from a half-wave rectified voltage are made use
of for the simultaneous pulse triggering of SCR's in bridge
ponfi uration [3]t This simple firing scheme gives only 25 to
100 control of conduction angle.
In the proposed scheme, rectified voltages are obtained
through a full-wave rectifier and the dc voltage is blocked.
Thp ripple potential is utilized for generating trigger pulses
and for synchronization. Steering of pulses to the appropriate
S R's is ac omplished through a logic circuitry. Full control
over conduction angle is achieved. A control voltage will alter
the firing angle within a maximum period of one sixth of a
cyc e. This scheme is implemented with a minimum number
of integrated circuit chips.
PROPOSED SCHEME
Fig. 1 shows the block diagram of the three-phase full-
wave controlled rectifier firing circuit. A stage by stage de-
sign is explained below. The complete firing circuit is given
in Fs. 2.
Development of Firing Circuit
A given SCR in the three-phase full-wave bridge (Fig. 1)
begins to conduct when its anode voltage becomes positive
(its voltage is crossing 600), if gate pulse is applied at this
instant. Within one cycle, six SCR's should be fired. So the
gate pulses should have a frequency six times the supply
frequency.
Three identical single-phase filament transformers, each
having a center tapped secondary, are taken. The secondaries
MODULATING
are connected in double star. The two half-wave rectifications
are done by six diodes. The rectified voltage would be dc
voltage superimposed by (third) harmonic ripples as shown in
Fig. 3d1, for half-wave rectifier 1. Fig. 3.3 gives the same for
rectifier 2.
DC Voltage Blocking
The (third) harmonic ripples can be used as the triggering
source. So the unwanted dc voltage is blocked using a resis-
tance and capacitance combination. The output is shown in
Fig. 3.2 for rectifier 1 Fig. 3.4 gives the same for rectifier 2.
The value of resistance is determined by maximum input
resistance for the monostable 1 and 3. For dc blocking, the
time constant of RC coupling should be large compared to
period of ripple.
Firing Angle Control
The (third) harmonic ripples (Fig. 3.1) from half-wave
rectifier 1 are given as triggering inputs to monostable 1. The
output of the monostable 1 would be rectangular pulses of
ripple frequency (Fig. 3.5). The input to monostable re-
quires voltage more than 0.8 V to give output. To get output
pulses at zero crossing of input ripple, as weli as variations in
firing angle, another monostable 2 is used. By varying the RC
combination of monostable 1, the negative edge of the output
pulse of it is varied. This output pulse is used as input pulse
to monostable 2. By varying the negative edge of monostable
1, the positive edge of output of monostable 2 can be varied
even from the zero crossing of the ripple (Fig. 3.6). The same
is shown for the half-wave rectifier 2 in Figs. 3.7 and 3.8. The
outputs of monostables 2 and 4 (Figs. 3.6 and 3.8) are given
 ILANGO et al: FIRING CIRCUIT FOR RECTIFIER
G,.
bo
C 0o -
230 / 9-0-9
FILAMENT
TRANSFORMERS
DIFF ERENTIATOR
Fig. 2. 3,0 full-wave controlled rectifier firing circuit.
as the inputs to the OR gate and its output is shown in Fig.
3.9. By varying the resistance in the RC combination of the
monostable 1 , full control over the conduction angle is achieved.
Mod-6 Counter Plus Decoder
The output pulses of monostable 2 are given as clock pulses
to the mod-6 counter. A decade counter (Fig, 4.1) is modified
and used as a mod-6 counter (Fig. 4.2). The output of the
mod-6 counter is given to the decoder. The decoder will
decode the input pulses so that the output would be one
pulse for six input pulses (Fig. 3.11). An inverter is used to
get positive pulses.
Steenrng Process
Firing pulses should be directed to the gate of that SCR (say
SCR1) for which the anode voltage is positive (that is, crossing
600), At the instant of switching, the counter may store any
number from 0 to 5. Hence, the firing pulse will not reach the
correct SCR. For example, the counter may store the number
3, which causes a firing pulse to be sent to SCR 4 (the anode
may not be positive), whereas the correct SCR to which the
pulse to be supplied is SCR1 (the anode will be positive). To
avoid this, a steering pulse is produced to ensure the correct
supply of gate pulse to the correct SCR.
For the production of a steering signa, a third monostable
is used. It has its input from the secondary of any one of the
filament transformers (the wave shape of this input voltage is
similar to the anode voltage of say SCR1, Fig. 3.14). The out-
put from the monostable 5 is taken from Q. The output
waveform is shown in Fig. 3.16. The position of the positive
edge of this output can be varied by varying the RC of mono-
stable 5, This positive edge is placed at 600 with respect to
the input waveform of monostable 5. This output of mono-
stable 5 is differentiated; the resultant negative pulse may be
47
sM
clipped and the remaining positive pulse occurs (Fig. 3.18) at
the 600 point of the monostable input voltage, which is also
the same point of anode voltage of SCR1. That is, the position
of the positive pulse indicates that the anode of SCR1 be-
comes positive. This positive pulse repeats for every 3600,
which can be exploited as explained below to stop the count-
ing of the decade counter and reset to 0 storage. So 0 storage
is made to appear at the gate of SCR1 (its anode is positive).
The positive pulse from the differentiator is applied to one
of the inputs of two OR gates (Fig. 4.3). The other inputs to
the OR gates are from B and C of the decade counter. The
outputs of the OR gates are applied to 2 and 3 of the decade
counter.
Table I gives its truth table. Only at the sixth pulse do the
B and C outputs become 1 and 1. Whenever the B and C try
to send 1 and 1 to 2 and 3 of the decade counter, it resets to
0. So the counter acts as mod-6 counter as shown in Fig. 4.2.
Table II gives the outputs of OR gates for all 6 possible inputs
from B and C of the decade counter, and 1 from the differen-
tiator (This 1 is the positive pulse representing the 60' crossing
of the anode voltage of SCR1). The outputs of the OR gates
are always 1 and 1 which are applied to 2 and 3 of the decade
counter (Fig. 4.3). As said earlier, the counter resets to 0,
Table III gives the outputs of the OR gates for all 6 possible
inputs from B and C of the decade counter and 0 from the
differentiator (0 represents that the angle is less than 600 of
anode voltage of SCR1, that is, the anode of SCR1 is not posi-
tive). The outputs of OR gates are not 1 and 1, so the counter
does not reset (that is, the counting proceeds), so that no
gate pulse to the nonpositive anode of SCRI. This is the
requirement.
Thus monostable 5, followed by the differentiator, the OR
gates, and the counter is made to send a signal to steer the
application of Pate oulse to that SCR for which the anode is
48 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS AND CONTROL INSTRUMENTATION, VOL. IECI-25, NO. 1, FEB. 1978

FIG.3.1 OUTPUT OF 30 HALFWAVE RECTIFIER 1 FIG. 3.12 ASTABLE OSCILLATOR OUTPUT

FIG. 3.2 THIRD HORMONIC RIPPLE AFTER DC VOLT L J L

BLOCKING OF 3.1 IL IL
IiL !LI
FIG. 3.3 OUTPUT OF 3 0 HALFWAVE RECTIFIER 2 }i ll

-- ------ . ---- ----- -~- FIG. 3.13 OUTPUT OF AND GATES

FIG. 3.4 THIRD HORMONIC RIPPLE AFTER DC VOLT Vab -Vca Vbc ab Vc Vbc Vab Vc Vbc -Vab Vca Vbc
BLOCKING OF 3.3

^~~~~~~
NEGATIVE EDGE POSITION IS VARIABLE ( SPAN 120 /

v
FIG. 3.5 OUTPUT OF MONOSTABLE 1

POSITIVE EDGE POSITION IS VARIABLE ( SPAN 1200)

FIG. 3.6 OUTPUT OF MONOSTABLE 2

FIQ3.14 APPLIED WAVEFORM TO MONOSTABLE 5/ANODE OF SCR1

H H H H
IL s
___

1 3
____

FIG.3.7 OUTPUT OF MONOSTABLE 3 1 6

2

FIG. 3.15 FIRING SEQUENCE (each SCR conducts for 1200)

FIG.3.8 OUTPUT OF MONOSTABLE 4

FIG.3.16 OYTPUT OF MONOSTABLE 4

FIG. 3.9 FIG.3.10 OUTPUT OF OR GATE/ INPUT OF

MOD.6 COUNTER
FIG. 3.17 OUTPUT OF DIFFERENTIATOR

n z LNI
L
I
Ji L- ,FIG.3.18 POSITIVE PULSE EXISTS WHENEVER ANODE
VOLTAGE OF SCR1 CROSSES 600
FIG.3.11 OUTPUT OF J L
DECODER AFTER
INVERSION
JL
Fig. 3.
 ILANGO et al.: FIRING CIRCUIT FOR RECTIFIER 4S9

INPUT V- .- TABLE I
INPUT s
NC A D I C TRUTH TABLE OF DECADE COUNTER
14 13 12 11 10 9 8 14 13 12 11 10 9 8
COUNT -D OUTPUT
1 2 3 4 5 6 7 1 2 3 4 5 6O O
C
06
B
__
-A
6 7 0 0
BD RNO RO2 NC Vcc Rg1 Rg2 I T T-,IL- ___1__ 0 0 0 1
INPUT 2 __ 0 0 1 0
3 0 0 1 1
4.__ 0 10 0
FIG. 41 7490 DECADE COUNTER FIG. 42 7490 AS MOD - 6 COUNTER _ _ ,0 1 0 1
6__ __0
7 0 1 1
8 1 0 0 0
- __ ___
_

_0

TABLE II
CONTINPUT TOO LOGIC FROM OUTPUTS OF
B C Dittrentiator WO'LOGIC NOTE:
O o N___
0. 1 1 1 COUNTER REESETS TO
FIG. 4.3 DECADE COUNTER PLUS OR LOGIC 1 O 0 -j 1 1 ZERO (-.BCOTH OUT-
Fig. 4. ,_
. 2
_
'1
_.i_ 3 1Oo. 1
1 1
1 1
1 PUTS
.OF'OI
ARE.I..AN
~~~~~~~ARE
IRLOGIC
ANDC 1)I)WHENEVER
;FROM
4
6
O
_t__
1 1.L1
11 1 __1
THEOINPUTS
NFEET IATOR ARE 1
5 O 1
positive, whatever may be the initially stored number while
starting.
Modulation TABLE III

C '-TQ
Sustained triggering is necessary to ensure reliable operation COUNT IN~' C LOGIC FROMI ORLOGIC
OUTPUTS OF
for different gate and load characteristics. Power dissipation 0
Diferenti_tor O O O
NOTE:
0 0 COUNTER PFROCEEDS
in the SCR gate is less, compared with continuous sustained 1 0 0 O 0 0 COUNTING{( . 1 BOTH
triggering. To get sustained triggering pulse, modulation of 2 1 o 0 110 OUTPUTS o)F'OR'LOGIC
control pulses (Fig. 3.11) for the SCR gate is necessary. Con-
3 O_ _ i1~ O ARE NOT 1 A iND 1)
THE INPUTS
-_
4 0- 1 [0 0 [_O
0 WHENEVER
FROM__ FFE RENT IATOR
trol pulses and high-frequency output (of the order of 5 KHz) __6 ..
_
.. .
0
. ARE O'
of astable multivibrator (Fig. 3.12) are given as inputs to an
AND gate The output of the AND gate would be the modu-
lated control pulses (Fig. 3.13).
ment of a lesser number of components, discrete components
Buffer Stage are utilized to the minimum. Pulse steering is achieved using a
In the case of the three-phase operation of an SCR bridge logic circuitry. Response of the firing angle to control voltage
circuit, the gates must be driven through pulse transformers is almost instantaneous.
because of the isolation required between different phases as
well as trigger circuits. ACKNOWLEDGMENT
Protection
The authors wish to thank Prof. T. R. Natesan and Prof.
V. N. Sujeer of the Electrical Engineering Department, College
The dc blocking resistance of RC combination connected to of Engineering, Guindy, Madras, India, for the facilities made
monostables 1 and 3 is shunted by a transistor. The transistor available for this work.
base will receive a signal in case of a fault in the power circuit,
driving the transistor to saturation. This will cut the input REFERENCES
pulses to monstables 1 and 3, and hence, the SCR's would [1I T. Krishnan and Ramaswami, "A fast response d.c. motor con-B.
not be given the gate pulses. This simple fast-acting scheme trol," IEEE Trans. Id. App., vol. IA-1O, 643-65 1, 1974. pp.

can be implemented. 2] Remy Simard and V. Rajagopalan, "Economical equidistant pulse

firing scheme for thyristorized D.C. driyes,' IEEE Trans. Ind
Electron. Contr. Instmm., vol. IECI-22, No. 3, pp. 425-429, 1975.
CONCLUSION [31 J. S. Wade Jr. and L. G. Aya, "Design for simultaneous pulse trig-
The scheme discussed above is found to work satisfactorily gering of SCRs in three phase bridge configuration," IEEE Trans.
Id. Electron. Contr. Instmm., vol. IECI-18, no. 3, pp. 104-106,
overthe entire conduction period. Apart from the require- 1971.