Counters DIGITAL ELECTRONICS n GATE Practice Questions 1. Theminimum number of fip-flops required to designa MOD-10 counter is, @3 ®) 10 O4 @s GATE (1N/1994/1M) 1 Ans.) The number of flip flops (n) required for the desired MOD number-Nis obtained by using the equation ml eNSh For N=10 2 n=4 Hence minimum number of flip flops required to design a MOD-10 counteris 4 [Refer Digital Circuits and Design by S.Salivahanan, ch -8 page-299, 8.4, page- 3.17, s.15.3] 2. -A4-bit synchronous counter witha series carry, uses flip-flopsand AND gates, havinga propagation delay of 30 ns and 10 ns respectively. The maximum time interval required between two successive clock pulses for reliable operation of the counter is (@) 10ns (b) 30ns (© 40ns @ 50ns GATE (1N/1987/1M) 2 Ans.(c) The total settling or response time ofa synchronous counter is given as follows The time taken by one flip flop to toggle plus the time for the newlogic levels to propagate througha singleAND gate to reach the J and K inputs of the following flip flop Total delay =Propagation delay of one flip flop + propagation delay ofAND gate =30ns-+ 10ns=40ns [Refer Digital Circuits and Design by S.Salivahanan, Ch-8 page- 307 (8.9)] 3. Theminimum number of flip-flops needed to make mod-? counter is, @l @)2 ©3 (@ None GATE (1N/1958/2M) 3. Ans.(a) The number of flip flops (n) required for the desired MOD number- Nis obtained by using the equation, ml SNS For N n=l (Refer Digital Circuits and Design by S.Salivahanan, 2nd edition, Ch -8 page-299, 8.4) 4. The square was C, shown in figure is givento the clock input ofa 4-bit binary up/down counter whose UP/DN input is fed with the pulse train P, The counter isa negative edge triggered one. The counter starts with 0000 and will reach 0000 again at the x 1 1 5 (@) ISthclockpulse (b) 16th clockpulse (©) 44thclockpulse (d) 48th clockpulse www.digeademy.com ag digeademy @gmail.comCounters DIGEEMeELEGTRQNICS 2 4. Gare (1/2003/2) Ans.(c) x 1 1 5 Itis seen from given waveforms that the signal P, remains high for two clock pulses and low for one clock. pulse. So, the counter works like up counter for two clock pulses and then works like down counter for one clock pulse altematively. In one pulse of P, the counter output increases by one. If counter starts from 0000 it needs to be incremented sixteen time to reach again at the state 0000. If 0000 is initial state of the counter thenat the end of 14th pulse of signal P, the output of counter becomes 1110. As one pulse of P, consists of three clock pulses soat the end of 42nd pulse the output ofthe counter becomes 1110. Then during 15th pulse of P, the output is again incremented by two by 43rd and 44 th clock pulses and output of counter becomes 0000. So, the output of counter becomes 0000 after 44th clock pulse. In figure initially Q=A= =0. After three clock triggers, the states of Q, A and B will be respectively 1 Mod3 TQ Counter ctoaey 9 ce ko ty QO AB (@) 10 (® ou (© oo @ 101 Gare (1n/2004/2M) Ans.(a) 1 Mod3 1 @ Counter ctor] 4 rT ko ty QO AB A MOD-3 counter is made up of 2 FFs. Hence we can redraw this circuit as follows 1 ce Initially all flip flopsare in the logical O state Q 0 Timing diagram www.digcademy.com | foa\eaia digcademy @gmail.comCounters DIGITAL ELECTRONICS 13 A negative transition (I to 0) in clockinput which drives flip flop-1 causes to change from Oto 1. FF2 doesnot change its state since it also requires negative transition at its clock input. After! clock pulse Q changes to 0 and A changes to | and B remains in state 0 because it also requires a negative transitionat its clockinput. After 34 clock pulse Q again becomes | and A remains | and B also remains 0. Hence the state of the counter after 3# clock pulse is 110, 6 For the digital counter shown in figure with outputs Q,, Q,, Q,, ... where Q, indicates the LSB of the count value, the correct statement when the switch SW is closed, is Vox (2) Counter outputs are both even and odd numbers (b) Counter outputs are only odd numbers (©) Counter outputs are only even numbers (@ Counter stops counting Gare (1N/2005/2M) Ans.(B) The output of J-K flip-flop togglesat arrival of every clock pulse when both input of flip-flop are “I” Output of OR gate, Y= AQ,+A(Clock) ‘When the switch SW is connected to the ground, the singals A and PR become ‘0’ and output Q, becomes ‘1” ag digeademy @gmail.comCounters DIGITAL ELECTRONICS “ inrespective of the clock signal. If is ‘0’ then signal A is ‘1’. When Ais ‘0’, Q is ‘0’ and A is‘l’ , the output of AND 1 becomes ‘0’ and output of AND 7 is same the value of clock. So, the output of OR gate is sameas the clock signal. As output of OR gate is connected at the clock of flip-flop with output Q, and QI is connected at clock input ofnext flip-flop so the output Q, toggles with clock signal and ouptut Q, toggles with signal Q,. Therefore, the output Q, remains continuously at logic ‘1’ and outputs Q, and Q, toggle with clock signal. The signal Q, is LSB of the count value. When ever LSB of a binary number is ‘I’ , the number is always odd. So, the counter counts odd number only. 7. Given that the initial state (Q,Q,) is 00, the counting sequence of the counter showm in the following figureis, AQ cK (@) 00-11-01-10-00 (b) 00-01-11-10-00 (©) 00-11-10-01-00 (@) 00-10-01-11-00 Gare (IN/2006/2™) 7. Ans.(a) cuK ‘The present state-next state table of J-K flip flop is shown below P| Q Operation NC Reset Set Toggle NC Reset Set Toggle +] oo} -] of fof fof of +] -|-] =] o] off Initially Q Present state of FF-1 Present state of FF2 www.digeademy.com ag digeademy @gmail.comCounters DIGITAL ELECTRONICS Is Now J, =K,= G1 geling from Oto 1 (Given) toggling from 0 to 1 Thus second state of counter is 11 ‘Now present state of FF-1=1 Present state of FF- J =K- Qo 3, = Ky=1 (given) Thus next state of FF-1 will be same as present state 1 due to inputs ‘Next state of FF-2 will toggle from 1 to 0 due to inputs J, ‘Thus third state of the counter will be 01 ol ‘Now present state of FF-1=01 Present state of FF-2 =00 J, -K,-Q -01 J, = K,=1 (given) ‘Next state of FF-1 will toggle from I to 0 due to input J,=K,= The next state of FF-2 will toggle from 0 to 1 due to Hence fourth state of the counter will be (10) ‘Now present state of FF-I=0 present state of FF 0, J, = K.=1(@ven) The next state of FF-1 wall be same as present state due to J,-K, The next state of FF-2 will toggle from I to 0 due to J,=K, Hence fifth state will be 00 Thus the counting sequence of the given counteris 00-11-01-10-00 ‘Statement for Linked Answer Questions 8 & 9: Consider the circuit shown inthe following figure. 8. The correct input-output relationship Y and (X, X,)is www.digeademy.com ag digeademy @gmail.comCounters DIGITAL ELECTRONICS 16 8 10 @Y=X+X O Y=%% ()Y=X,@X, (@) Y=X,OY, GATE (1N/2007/2M) Ans.(@) ox! Fromthe circuit diagram, Barca) barca } Y (GS ) (GD = +E) 0 +H) =%%)+ hh = XOX) Refer Digital Circuits and Design by S.Salivahanan, 2 edition Page 83, 3.3.5, Page-44, (2.5) The D flip-flops are initialized to Q,Q,Q,= 000. After 1 clock cycle, QQ,Q,is (@) O11 (b) o10 (©) 100 @ 101 GATE (1N/2007/2M) Ans.(B) From the circuit diagram, D, =Q, XOX, = GQ and DR = Q State table of the circuit can be drawn by using above relations as under, FS Tapats WS QQ Qs{Di Dr Ds |Q Q oo 0 fot ofei o Thus if intial state of the circuit is O00 then the next state after 1 clock cycle becomes 010 Refer Digital Circuits and Design by S.Salivahanan, 2* edition Page 329,(8.15.6) The pulse width 7 of an asynchronous pulse is measured by a counter with an edge-triggered clock of known frequency fas shown in thefigure below. www.digeademy.com ag digeademy @gmail.comCounters DIGITAL ELECTRONICS v | = Clot eounter Enable The pulse, whose widthisto be measured, isapplied to the Enable pin ofthe counter. The counter counts while the Enableis high andis held reset to zero otherwise. The counter outputislatched by the negative edge of the Enable signal. The measured pulse width is taken to be times the clock period, where Nis the count reached at the end of count cycle Assuming no overflow, the measurement error will be limited tox% of T if 100 100 (a) Toe ®

|—4> dx, de | } dx zo ZF] 3 ee This circuit works as MOD-8 binary counter. It goesall the states from 0 to 7 (000 —> 001 > 010 > 011 -> 100+ 101 > 110 + 111 + 000. ‘Now we considera O to 6 counter, it will go through the following sequence (000 —> 001 > 010 -> 011 > 100+ 101 — 110 + 000. ‘Assuming that all the flip-flop have active HIGH clear inputs. www.digeademy.com ag digeademy @gmail.comCounters DIGITAL ELECTRONICS a GG alk 700 fo o 0 1 |o 0 1 0 fo o 1 1 |o 1 0 0 |o 1 01 |o 1 1 0 |o riih = R=3 QQ ‘As the counter state reaches 111, the AND gate output becomes HIGH making all the fip flop cleared Thus counter does not remain in 111 state and becomes 000 immediately. 1 1 Thus the combination circuit consists of two 2 input AND gates Refer Digital Circuits and Design by S.Salivahanan, 2 edition Page-299, (8.4) 7. AAbitripple counter anda 4 bit synchronous counter are made using fip flops havinga propagation delay of 10 ns each. Ifthe worst case delay in the ripple counter and the synchronous counter be Rand S respectively, then @ ) © @ GATE (2C/2003/2M) 7. Ans.(b) Ripple counter Ripple counter hasa cumulative settling time , Hence the n® flip flop can not change states for a period of nxt ,even after the clock pulses occurs Therefore, to allowall the fip flops ina n bit nipple counter to change states in response to. clock, the period ofthe clock should be Tea 2 0% ty For4 bit ripple counter, n=4 And T,, = 10ns R = 4 10=40ns ‘Synchronous Counter. Total delay =Propagation delay of one fip flop S = 10ns Refer Digital Circuits and Design by S.Salivahanan, Ch- 8 page -305 (8.8) & 307 (8.9) ag digeademy @gmail.com www.digeademy.comCounters DIGITAL ELECTRONICS 2B 8. Inthemodulo-6 ripple counter shownin figure, the output of the 2-input gateis used to clear the JK flip-flops 1 TH Pe TH aA Ic [crock ee KW [ z input input gate 7 The 2-input gateis (2) aNAND gate (0) a NOR gate (© anOR gate (@) an AND gate wl n Pl n GATE (BC/2004/2M) 8 Ans. () cab eb ye ic Oy iB KK or ‘input gee AMOD-6 ripple counteris shown above. Without the NAND gate this counter functions as a MOD-8 binary counter which counts from 000 to 111. The presence of the NAND gate alters this sequence as 000-+001-+010-+011-+100-+101-> 000+. —T 1) we should have Q= OQ; = Q5 +0, =O Q a—4 a — Hence the -? input gate is an OR gate [Refer Digital Circuits and Design by S.Salivahanan, Ch-8 page-299, (8.4)] 9. Fig showsaripple counter using positive edge triggered flip-flops. Ifthe present state of the counteris Q,Q,Q, =O11, then its next state (Q,Q,Q,) will be oo www.digeademy.com ag digeademy @gmail.comCounters DIGITAL ELECTRONICS » 10 Leahy Afr, af Ur, af Ur, op ox a a) aL (@) 010 (b) 100 @u @ 101 GATE (BC/2005/2M) Ans.(B) CLK Initial states of the flip flops are given Q.=0 Qy Timing diagrams : Operation: Initially Q=1,Q, = 1, Q=0 A positive transition (Oto 1)in clocleinput causes Qyto change fromlogical | to logic 0. Thusat each transition of clock input Q, changes its state altemately. NowFF2is driven by Q, of FF1. So we obtain Q, by complementing timing diagramof Q, ‘Nowa positive transition (0 to 1) in Q, causes Q,to change state from 1 to 0. At each positive transition of QQ changes its state altemately. Nowwe obtain Q by complementing Q,. A positive transition (0 to 1) in Q) which drives FF-3 causes Q,to change from logical 0 to logical 1. Thus we obtain timing diagram of Q, Initially Q,= 0, Q.= 1, Q,= | at first clock pulse next stateis 100 [Refer Digital Circuits and Design by S.Salivahanan, Ch- 8 page - 294 8.2)] Two D-fip-flops,as shown below, areto be connectedasa synchronous counter that goes through the following Q, Q, sequence 00> 01> 11510 00 The inputs D, and D, respectively should be connected as www.digeademy.com ag digeademy @gmail.comCounters DIGITAL ELECTRONICS 20 Dy Dr Qs LsB MsB cLock @ G andQ () QandQ, © Gand GA @ FF andaq GATE (EC/2006/2M) 10. Ans.(a) Dy Dr LsB MsB @ Qa cLock The synchronous under goes through the following sequence Q, Q, 00 01+ 11> 10+ 00 The counter under goes through four different states before retuming to initial state. So, it must bea MOD4 counter. The State table of D flip-flop is given as, Q 0 0 1 1 I oe oly Io olf State table for the counter with D flip-flops can be drawnas under, Present State] NectState | Taputs Qin Qonf ar Arf Pr De 0 1 1 0 1 1 0 0 K-map forD, = K-map forD, www.digcademy.com foa\eaia digcademy @gmail.comCounters DIGITAL ELECTRONICS a1 “lp u > D=-a Hence the inputs D, and D, respectively should be connected as @, and Q, (Refer Digital Circuits and Design by SSalivahanan, 2nd edition Ch-8, Pg. 312, 8.15.) Il. For the circuit shown, the counter state ( Q, Q,) follows the sequence ciock (@) 00,01, 10, 11,00 (b) 00,01, 10,00, 01 (©) 00,01, 11,00, 01 (@) 00,10, 11,00, 10. GATE (EC/2007/2M) Ht. Ans.(b) D, O. Do FFI FFD ciode From the circuit diagram, D, = &+Q, and dD, = Q The state table of flip flop, Im oe do Io - olf The state table of the circuit can be givenas, ag digeademy @gmail.com www.digeademy.comCounters DIGITAL ELECTRONICS 2 Prevent Slat | FlipFlop pas [Newt State TOF [D=0, D=Gral me Fl @Q) @Q) a Q oo | o 7 | o 3 1 | 3 o [i oo 1 o | 0 0 fo oo o of o 1 Jo 2 3 | o |i oo Hence the counter state (Q, Q,) follows the sequence 00, 01, 10, 00, 01 12. What are the counting states (Q,,Q,) for the counter shown in the figure below? a Q 1! eT r, Cos) xe] (4 TKEF ko, AK, 6. 7 (@) 11, 10,00, 11, 10, (b) 01,10,00,01, 10, (©) 00, 11,01, 10, 00, (@ 01,10,00,01, 10, GATE (EC/2008/2M) 2D. Ans.(a) Teo Hl oor, | /7g i 3 The state table for J-K flip flop is as shown below, O. [ft E[Gn [Operation ajo ofo | Ne oT fo tf 0 | Reet Cs Cc oft t|1 | Teese Tjoofiy| ne To i] 0 | Reet Tit o;i| se T[t if 0 [ Toggle Let us assume that any instant the state of counter is 00. From the circuit diagram, we observe 3 = K=G,.4=Q andk, Now state table of the circuit can be drawn as under, www.digeademy.com ag digeademy @gmail.comCounters DIGITAL ELECTRONICS B Presat Stat | FF-1 | FF=2_ | Newt State ao. 12 =)® ®lo., o & 1@ @(@ ol To re TT TH vo [on 10 10 ti [ot oo oo rit [at Tt Thus from the above table we observe that the counting states (Q, Q,) for the counter shown are 00,11, 10,00,11,10,00.... or 11,10,00,11,10, 13, Assuming that all flip-flops are in reset condition initially, the count sequence observed at Qg in the circuit shownis Oxy C | p. apt, @ be. zy Tv q Goer (a) 0010111 (b) 001011 (© 0101 @ 0110100. GATE (EC/2010/2M) 13. Ans.(@) Clack From the circuit diagram, we observe that, Da = Qa ©Q¢ .Dg = Qu, De=Q5 Truth table of Ex-NOR gate, www.digeademy.com ag digeademy @gmail.comCounters DIGITAL ELECTRONICS a Inputs [ Outputs Qs Oe Da oO 1 o 1 0 on) 0 1 1 State table ofD flip flop, QD | Qua 0 o| 0 0 1{[i 1 ofo 1 tft Initially all the flip flops are in reset conditioni.e. Q, =Qg=Qe The operation ofthe counter is explained in the following table Present State_| Flip Mopimputs | Next State k 5B C |D, D, DA 5B C Q) Qo QD Hence the count sequence observed at Qy in the circuit shown is 0110100 14, The output ofa 3-stage Johnson (twisted-ring) counter is fed to a digital-to-analog (D/A) converter as shown inthe figure below Assumeall states of the counter to be unset initially. The waveform which represents the D/ A converter output V, is DIA Converter D, D, D, oo Johnson Clock| Counter (Dae digeademy @gmail.comCounters DIGITAL ELECTRONICS 38 () oa © @ ss GATE (BC/2011/2M) 14, Ans.(a) Johnson Counter is obtained from serial -in serial - out shift register by providing feedback from the inverted output of the last flip-flop to input of first flip-flop. The logic circuit and timing diagram ofa 3 bit Johnson counter as shown below, Clock www.digeademy.com CADEMY digeademy@email.comCounters DIGITAL ELECTRONICS 36 Sequence table and output of D/A converer can be given as under, Output of counter] Outputs of Clock 59. —@, PDA converter ‘Wave form of output of D/A converter pinion > 15. TwoD flip-flops are connected asa synchronous counter that goes through the following Q, Q, sequence 00 sils01>10s005 The connections to the inputs D, and D, are @ Dy= Qs, Ds=Q @) Dy=Qq, Dy =Oy © Da =@aQp +O,Qz), Da = @ Da=(QaQn +O, 0p). Da =a A GATE (EC/2011/2M) 1S. Ans.(@) The state transition table of the flip-flop can be written as under, www.digcademy.com | foa\eaia digcademy @gmail.comCounters DIGITAL ELECTRONICS Qu Qin [Oren 2 1 [Ds Da 1 pia a T [io T o [ot a o [oo K-maps for D, and D, can be drawn using above table as under, Boolean expression for D,and Dy , Dy = Q,0,+0,0, (Q,02,) Dy = a The logic circuit of counter: ave 3% 5, Clock: 16. When the output ¥ in the circuit belowis “1” it implies that data has Dete_JD,_Q J eo a Covi > 6 af (@) changed from“0" to“1" (b) changed from“1” to “0” (©) changedin either direction (@) not changed 16, Ans.(a) GATE (BC/2011/1M) www.digeademy.com CADEMY digcademy@gmail.comCounters DIGITAL ELECTRONICS 38 De Output y is “I” only when both Q, & Q, are ‘I’. For D flip-flop Q=D. So, Q =D, and Q, is complement of Q, So, Q, can not be equal to Q, Output ‘Y" canbe’ only momentarily when input data changes either from Oto 1 or from I to 0. Lett, is delay ofeach flip-flop. Case-I If inital D, = 1: When input data is 1, Q,= 1 and Q, =0 so, output of gate is “0”. When input changes from | to 0 the output Q, becomes ‘0’ after delay oft, Whereas output Q, becomes ‘I’ after delay of 2t,, Both Q, and Q, remains low for a period of ty during which Y is ‘0’. So, output ‘Y’ remains zero when input changes from “Tto 0" Case-II :- If initial D, = 0: When data ="0", Q, is zero and Q, is ‘1’ So, output of AND is “O°. When input is changed from ‘O" to 1. Output Q, becomes ‘I’ after delay oft, and Q, becomes ‘0’ after delay of 2t, So, both Q,and Q, are high fora period of t, during which output of AND gateis‘1”. So, output “Y” of circuit “1 when input data changes from Otol Q.AsQ 1. Thethree stage Johnson ring counter shown in figureis clocked ata constant frequency of f, fromthe starting state of Q,Q,Q, = 10. The frequency of outputs Q,,Q,,Q, will be f f @+ os & & oF OF GATE (EE/1991/2M) 1 Ans.) www.digcademy.com | foa\eaia digcademy @gmail.comCounters DIGITAL ELECTRONICS 2» Truth table of JK flip - flop TET Qa o ofa ool 0 1 0 1 111/1Q CLK. K QWli KQ A kA 0 fro 1 oft oo Hho Lot 1 fro: of: oy oft oD 1 a fo Qi of os oft i o 3 fo r%o ifo 1 oft oS o fede of Sy fo Seo s fr obo ipo 1) ro 10 1 6 hh ot: oft oy oft oD 1 \ SET Ns 7 |r od opt oS: opt oot s fo iti obi os 0 ~ \ oo pe oNt oe 9 Jo 1 “o ipo 1 of: oo ‘Waveform : Itis observed from above waveform that iff, is frequency of clock signal then frequency of Q,, Q, and Q, isf/6 2. Atwo-bit counter circuit is shown below e 7H fn y i Ifthe state Q,, Qg of the counter at the clock time t, is “10” then the state Q,Q, of the counter at t,+ 3 (after three clock cycles) will be cK @ 00 () OL © 10 @u www.digcademy.com foa\eaia digcademy @gmail.comCounters DIGITAL ELECTRONICS 0 GATE (BE/2011/2M) 2 Ans(c) cK From logic circuit, J= Q5,K =Qy T=Qy Clock Q, Q, J K T t 1 0 1 0 1 tel ool 1 oo 1 t+2 0 0 1 0 0 en) 1 0 1 www.digcademy.com digcademy @gmail.comCounters DIGITAL ELECTRONICS a 4l 41 a 21. a 21. 51 51. 50. Therefore, output Q, Q, after three clock pulses becomes 10, A 10-bit rippte carry adder is realized using 16 identical full adders (FA) as shown in the figure. The carry- propagation delay of each Ais 12 ns and the sum-propagation delay of each FAis 15s. The worst case delay (inns) of this 16-bit adder will be AB AB, 1 11 FA A.B, | GATE (EC-1V/2014/2M) Ans : 194.9 to 195.1 A cascade of three identical modulo-5 counters has an overall modulus of @)5 (b) 5 (© 135 @ 05 GATE (EE~1/2014/1M) Ans. (o) Which of_~—sthe_~— following = is_-=s an_—invalid ~— state. = sin. aan 8-4-2-1 Binary Coded Decimal counter (a) 1000 (b) 1001 (©) oll @ 100 GATE (EE-T1/2014/1M) Ans. (@) A 3-bit gray counteris used to control the output of the multiplexeras shownin the figure. The initial state ofthe counter is 000,. The output is pulled high The output of the circuit follows the sequence A. 3-bit gray} + counter E R 15 bod sa 4 Output ak b— @ hLLLLLLL @ HELE LET O LBL DLL @ behbb bh bb GATE (EE-TT1/2014/2M) Ans 0) The number of clock cycles for the duration ofan input pulse is counted usinga cascade of N decade counters (OC 1 to DC N)as shown in the figure. Ifthe clock frequency in mega hertz.is f the resolution and range of measurement of input pulse width, both in ps, are respectively, www.digcademy.com | foa\eaia digcademy @gmail.comCounters DIGITAL ELECTRONICS 2 N-dight display N-night register Clock Generator] ” ER: Enable/ Reset t Pulse shapping| Input pulse 1g oD @ 7 F ») Lang AOD Jang G2) @ ana 10" ng QOD Opens GATE (1N/2015/2M) Ans. @) 26. A mod. counter usinga synchronous binary up-counter with synchronous clear input is shown in the figure The value of 7 is GATE (EC-T1/2015/1M) TErbaay On Qn Comter Qa} 4 Qn cLoce poke ree crERR Ti Qo —d 47. The figure shows bianry counter with synchronous clear input. With the decoding logic shown, the counter works as a www.digcademy.com | foa\eaia digcademy @gmail.comCounters DIGITAL ELECTRONICS 6B Binary Cotes s —cik & ae oR QPL (a) mod-2 counter (®) mod-4 counter (©) mod-5 counter Ans. (¢) (@ mod-6 counter GATE (EC-11/2015/2M) 24, The circuit shown consists of J-K flip-flops, each with an active low asynchronous reset (R, input). The counter correspondingto this circuit is GATE (EC-TI1/2015/1M) Q@ isi Clock—4 IK G (@a modulo-5 binary up counter ()a modulo-6 binary down counter ()a modulo-S binary down counter (@amodulo-6 binary up counter Ans. (@) 48. For the circuit sho GATE (EC-TI1/2015/1M) ywn in the figure, the delay of the bubbled NAND gate is 2 ns and that of the counter is assumed to be zero Qo(LSB) 3-bit Q@ Synchronous [——_] Counter Jo, asa) ck J RESET If the clock (Clk) frequency is 1 GHz, then the counter behaves as a @ mod-5 counter www.digcademy.com | foa\eaia digcademy @gmail.comCounters DIGITAL ELECTRONICS “ (®) mod-6 counter (©) mod-7 counter (@ mod-8 counter GATE (EC-1T1/2016/2M) Ans. (@) 45. A synchronous counter using two J -K flip flops that goes through the sequence of states QQ =00- 10-01-1100... isrequired. To achieve this, the inputs to the flip flops are h Qy bh Q GATE (1N/2016/2M) Ans. @) 44. A 2bit synchronous counter using two J-K flip flops is shown. The expressions for the inputs to the J-K flip flops are also shown in the figure. The output sequence of the counter starting from Q,Q, = 00 is Ore pa pe 0, +0—K ard] cir Q| Toa (@) 00> 11+ 10-01-00 (b) 00-01-10 11-4 00 (©) 00-01 11 1000 (@ 00-10 11-01-00 GATE (1N/2018/2M) 44, Ans.(c) 17. Forthe 3-bit binary counter shown in the figure, the output increments at every positive transition in the clock: (CLK), Assume ideal diodes and the starting state of the counter as 000. If output high is 1 V and output low is OV, the current I (in mA) flowing through the 50 Qresistor during the 5% clock cycle is (up to one decimal place) www.digcademy.com | foa\eaia digcademy @gmail.comCounters DIGITAL ELECTRONICS 6 Shi binary counter MSE f ‘00a <1 00 1000 LSB CLK GATE (1N/2018/1M) 17, Ans.(10 to 10) 36. Which one of the following statementsiss true about the digital circuit shown in the figure é (@) It can be used for dividing the input frequency by 3 (b) It can be used for dividing the input frequency by 5 (0) It can be used for dividing the input frequency by 7. (@) It cannot be reliably used as a frequency divider due to disjoint intemal cycles. GATE (BE/2018/2M) 36. Ans.(b) 25. Inthe circuit shown, the clock frequency, ie, the frequency of the Clk signal, is 12 kHz, The frequency of the signal at Q, is KHz D, Qk Dp. 2 ° CLE all CLE O. 12H GATE (EC/2018/1M) 25, Ans.(4 to 4) www.digcademy.com | foa\eaia digcademy @gmail.comCounters DIGITAL ELECTRONICS 6 Fr, LI CLE © 1 Output of AND gate, D= 2a Input ofFF2,D, = Q State table ofthe given circut, Present Next State State Qrivet) Sieve It is observed from the above table that the state of the circuit repeats after 3 clock pulse. There The ‘waveform of CLK and Q,, can be drawn with the help of state table as under, LiF LF ti fl, It is observed that there is one pulse of Q, for three pulse of CLK so the frequency of Q, is one third of frequecy of CLK. Frequency of CLK = 12 KHz 1 Frequency of Q, = Kz www.digcademy.com | foa\eaia digcademy @gmail.com