VHDL Prei Nforme 4

AUX. UNIV.
Joel Bautista España Ulloa laboratorio 4 ETN – 601
PRE INFORME
CIRCUITOS ARITMETICOS
VHDL DIAGRAMA ESQUEMATICO
a) DISEÑO DE SUMADORES BCD*

Diseñe e implemente un circuito sumador/restador para dos números con signo de 2 dígitos cada uno, del
código BCD 7421, tal que la información de entrada y salida debe ser representada en binario decimal a
través de Display’s de 7 Segmentos. El circuito debe ser capaz de realizar operaciones con números en el
rango de  99 99 =  198.
PAQUETE 1
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
--DECLARAMOS LA ENTIDAD
ENTITY TRASCOD IS
PORT(A: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
BCD: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END TRASCOD;
--DEFINICION DEL COMPORTAMIENTO
ARCHITECTURE FUNCION OF TRASCOD IS
BEGIN
WITH A SELECT
-- 7421
BCD<= "0000" WHEN "0000",
"0001" WHEN "0001",
"0010" WHEN "0010",
"0011" WHEN "0011",
"0100" WHEN "0100",
"0101" WHEN "0101",
"0110" WHEN "0110",
"0111" WHEN "1000",
"1000" WHEN "1001",
"1001" WHEN "1010",
"0000" WHEN OTHERS;
END FUNCION;
PAQUETE 2
LIBRARY IEEE;
ENTITY SUMCUA IS
PORT(A,B: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
CI: IN STD_LOGIC;
S: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
COUT: OUT STD_LOGIC);
END SUMCUA;
ARCHITECTURE FUNCION OF SUMCUA IS
SIGNAL CARRYS: STD_LOGIC_VECTOR(2 DOWNTO 0);
COMPONENT SUMCOM IS
PORT(A,B,CI: IN STD_LOGIC;
S,CO: OUT STD_LOGIC);
END COMPONENT;
BEGIN
AUX. UNIV. Joel Bautista España Ulloa laboratorio 4 ETN – 601
SUM1: SUMCOM PORT MAP(A(0),B(0),CI,S(0),CARRYS(0));

SUM2: SUMCOM PORT MAP(A(1),B(1),CARRYS(0),S(1),CARRYS(1));
SUM4: SUMCOM PORT MAP(A(3),B(3),CARRYS(2),S(3),COUT);
END FUNCION;
PAQUETE 3
LIBRARY IEEE;
ENTITY CORRECTORBCD IS
PORT(X: IN STD_LOGIC_VECTOR(4 DOWNTO 0);
Y: OUT STD_LOGIC_VECTOR(4 DOWNTO 0));
END CORRECTORBCD;
ARCHITECTURE FUNCION OF CORRECTORBCD IS
BEGIN
Y <= "10000" WHEN X="01010" ELSE
"10001" WHEN X="01011" ELSE
"10010" WHEN X="01100" ELSE
"10011" WHEN X="01101" ELSE
"10100" WHEN X="01110" ELSE
"10101" WHEN X="01111" ELSE
"10110" WHEN X="10000" ELSE
"10111" WHEN X="10001" ELSE
"11000" WHEN X="10010" ELSE
"11001" WHEN X="10011" ELSE X;
END FUNCION;
LIBRARY IEEE;
PACKAGE COMPONENTE IS
COMPONENT CORRECTORBCD IS
Y: OUT STD_LOGIC_VECTOR(4 DOWNTO 0));
END COMPONENT;
END COMPONENTE;
PAQUETE 4
LIBRARY IEEE;
ENTITY COMPLE IS
PORT(BS,NOU: IN STD_LOGIC;
A: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
C: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COMPLE;
ARCHITECTURE FUNCION OF COMPLE IS
BEGIN
C <= A WHEN (BS = '0') ELSE
"1001" WHEN (A="0000" AND NOU='1') ELSE
"0000" WHEN (A= "0000") ELSE
"1001" WHEN (A= "0001") ELSE

"1000" WHEN (A= "0010") ELSE
"0111" WHEN (A= "0011") ELSE
"0110" WHEN (A= "0100") ELSE
"0101" WHEN (A= "0101") ELSE
"0100" WHEN (A= "0110") ELSE
"0011" WHEN (A= "0111") ELSE
"0010" WHEN (A= "1000") ELSE
"0001" WHEN (A= "1001") ELSE "0000";
END FUNCION;
PAQUETE 5
LIBRARY IEEE;
ENTITY SUMCOM IS
END SUMCOM;
ARCHITECTURE FUNCION OF SUMCOM IS
BEGIN
S <= A XOR B XOR CI;
CO <= (A AND B) OR (A AND CI) OR (B AND CI);
END FUNCION;
PAQUETE 6
LIBRARY IEEE;
ENTITY MULTI IS
PORT(X,Y: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END MULTI;
ARCHITECTURE FUNCION OF MULTI IS
SIGNAL P1,P2,P3,P4: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL S1,S2,S3: STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL AUX: STD_LOGIC_VECTOR(3 DOWNTO 0);
COMPONENT ANDS IS
M: IN STD_LOGIC;
P: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COMPONENT;
COMPONENT SUMCUA IS
CI: IN STD_LOGIC;
END COMPONENT;
BEGIN
BLOQUE1: ANDS PORT MAP(X,Y(0),P1);
AUX <= '0'&P1(3 DOWNTO 1);
SUMADOR1: SUMCUA PORT MAP(AUX,P2,'0',S1(3 DOWNTO 0),S1(4));
SUMADOR2: SUMCUA PORT MAP(S1(4 DOWNTO 1),P3,'0',S2(3 DOWNTO 0),S2(4));
S <= S3&S2(0)&S1(0)&P1(0);
END FUNCION;
PAQUETE 7
LIBRARY IEEE;
ENTITY SIGNOBCD IS
PORT(BSA,BSB,CARRY: IN STD_LOGIC;
BS: OUT STD_LOGIC;
DIGITO: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END SIGNOBCD;
ARCHITECTURE FUNCION OF SIGNOBCD IS
SIGNAL SEL: STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL SALIDA: STD_LOGIC_VECTOR(4 DOWNTO 0);
BEGIN
SEL <= BSA&BSB&CARRY;
WITH SEL SELECT
SALIDA <= "00000" WHEN "000",
"00001" WHEN "001",
"11001" WHEN "010",
"00000" WHEN "011",
"11001" WHEN "100",
"00000" WHEN "101",
"11000" WHEN "110",
"11001" WHEN "111",
"00000" WHEN OTHERS;
DIGITO <= SALIDA(3 DOWNTO 0);
BS <= SALIDA(4);
END FUNCION;
PAQUETE 8
LIBRARY IEEE,WORK;
USE WORK.COMPONENTE.ALL;
ENTITY SUMADORA IS
PORT(BSA,BSB,CARRY,NOU: IN STD_LOGIC;
A,B: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
CARRYBCD: OUT STD_LOGIC);
END SUMADORA;
ARCHITECTURE FUNCION OF SUMADORA IS
SIGNAL A1,B1,A2,B2,DIGA,DIGB: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL RESULTADO,CORREGIDO: STD_LOGIC_VECTOR(4 DOWNTO 0);
--SUMADOR DE 4 BITS
COMPONENT SUMCUA IS
CI: IN STD_LOGIC;
END COMPONENT;
--TRANSCODIFICADOR A BCDN
COMPONENT TRASCOD IS
END COMPONENT;
--COMPLEMENTO A 10
COMPONENT COMPLE IS
PORT(BS,NOU: IN STD_LOGIC;
END COMPONENT;
--FUNCIONAMIENTO
BEGIN
--TRANSCODIFICACION DE LOS DIGITOS
TRANSCOD1: TRASCOD PORT MAP(A,A1);
TRANSCOD2: TRASCOD PORT MAP(B,B1);
--COMPLEMENTO DE LOS DIGITOS
COMPLEMENTO1: COMPLE PORT MAP(BSA,NOU,A1,A2);
COMPLEMENTO2: COMPLE PORT MAP(BSB,NOU,B1,B2);
--SUMA
SUMADOR: SUMCUA PORT MAP(A2,B2,CARRY,RESULTADO(3 DOWNTO 0),RESULTADO(4));
--CORRECCION
CORRECCION: CORRECTORBCD PORT MAP(RESULTADO,CORREGIDO);
--ASIGNACION DE SALIDAS
S(3 DOWNTO 0) <= CORREGIDO(3 DOWNTO 0);
CARRYBCD <= CORREGIDO(4);
END FUNCION;
PAQUETE 9
LIBRARY IEEE;
ENTITY ANDS IS
M: IN STD_LOGIC;
END ANDS;
ARCHITECTURE FUNCION OF ANDS IS
BEGIN
P <= X WHEN M='1' ELSE "0000";
END FUNCION;
--UNION DE LOS PAQUETES--
LIBRARY IEEE,WORK;
USE WORK.COMPONENTE.ALL;
ENTITY SUMADOR_BCD IS
PORT(BSA,BSB: IN STD_LOGIC;
A,B: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
BS: OUT STD_LOGIC);
END SUMADOR_BCD;
ARCHITECTURE FUNCION OF SUMADOR_BCD IS

SIGNAL A1,B1,A2,B2,DIGA,DIGB: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL RESULTADO,CORREGIDO: STD_LOGIC_VECTOR(4 DOWNTO 0);
COMPONENT SUMCUA IS
CI: IN STD_LOGIC;
END COMPONENT;
COMPONENT TRASCOD IS
END COMPONENT;
COMPONENT COMPLE IS
PORT(BS: IN STD_LOGIC;
END COMPONENT;
COMPONENT SIGNOBCD IS
PORT(BSA,BSB,CARRY: IN STD_LOGIC;
BS: OUT STD_LOGIC;
DIGITO: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COMPONENT;
BEGIN
TRANSCOD1: TRASCOD PORT MAP(A,A1);
TRANSCOD2: TRASCOD PORT MAP(B,B1);
COMPLEMENTO1: COMPLE PORT MAP(BSA,A1,A2);
COMPLEMENTO2: COMPLE PORT MAP(BSB,B1,B2);
SUMADOR: SUMCUA PORT MAP(A2,B2,'0',RESULTADO(3 DOWNTO 0),RESULTADO(4));
CORRECCION: CORRECTORBCD PORT MAP(RESULTADO,CORREGIDO);
SIGNO: SIGNOBCD PORT MAP(BSA,BSB,CORREGIDO(4),BS,S(7 DOWNTO 4));
S(3 DOWNTO 0) <= CORREGIDO(3 DOWNTO 0);
END FUNCION;
SUMADOR con su bit de signo
DIAGRAMA DE TIEMPO Y RTL

b) LÓGICA COMBINACIONAL CON SUMADORES*
b.1) Diseñe un transcodificador de código Binario Natural de 7 bits a BCD AIKEN con 2 dígitos,
utilizando circuitos sumadores (7483 y 74283). Implemente un diseño parecido, pero solo de binario
natural 6 bits a BCD dos dígitos desplegados en display’s de 7 segmentos.
LIBRARY IEEE;
ENTITY BN_a_BCD IS
PORT (A: IN STD_LOGIC_VECTOR (6 DOWNTO 0);
F:OUT STD_LOGIC_VECTOR (6 DOWNTO 0));
END BN_a_BCD;
ARCHITECTURE FUNCION OF BN_a_BCD IS
BEGIN
WITH A SELECT
F<= "0000000" WHEN "0000000",--0
"0000001" WHEN "0000001",--1
"0000010" WHEN "0000010",--2
"0000011" WHEN "0000011",--3
"0000100" WHEN "0000100",--4
"0001011" WHEN "0000101",--5
"0001100" WHEN "0000110",--6
"0001101" WHEN "0000111",--7
"0001110" WHEN "0001000",--8
"0001111" WHEN "0001001",--9
"0010000" WHEN "0001010",--10
"0010001" WHEN "0001011",--11
"0010010" WHEN "0001100",--12
"0010011" WHEN "0001101",--13
"0010100" WHEN "0001110",--14
"0011011" WHEN "0001111",--15
"0011100" WHEN "0010000",--16
"0011101" WHEN "0010001",--17
"0011110" WHEN "0010010",--18
"0011111" WHEN "0010011",--19
"0100000" WHEN "0010100",--20
"0100001" WHEN "0010101",--21
"0100010" WHEN "0010110",--22
"0100011" WHEN "0010111",--23
"0100100" WHEN "0011000",--24
"0101011" WHEN "0011001",--25
"0101100" WHEN "0011010",--26
"0101101" WHEN "0011011",--27
"0101110" WHEN "0011100",--28
"0101111" WHEN "0011101",--29
"0110000" WHEN "0011110",--30
"0110001" WHEN "0011111",--31
"0110010" WHEN "0100000",--32
"0110011" WHEN "0100001",--33
"0110100" WHEN "0100010",--34
"0111011" WHEN "0100011",--35
"0111100" WHEN "0100100",--36
"0111101" WHEN "0100101",--37
"0111110" WHEN "0100110",--38
"0111111" WHEN "0100111",--39
"1000000" WHEN "0101000",--40
"1000001" WHEN "0101001",--41

"1000010" WHEN "0101010",--42
"1000011" WHEN "0101011",--43
"1000100" WHEN "0101100",--44
"1001011" WHEN "0101101",--45
"1001100" WHEN "0101110",--46
"1001101" WHEN "0101111",--47
"1001110" WHEN "0110000",--48
"1001111" WHEN "0110001",--49 hasta 7bits AIKEN
END FUNCION;
VHDL COMBINACIONAL
RTL
b.3) Sintetice las siguientes funciones utilizando únicamente sumadores:
F1 =∑4 (0,2,4,6,8,12,13) + ∑ø4 (10)
F2 =∑4 (0,2,5,6,11,12,14) + ∑ø4 (1,4,10)
F3 =∑4 (0,4,6,9,13) + ∑ø4 (8,12,15)

LIBRARY IEEE;
ENTITY FUNCIONES IS
PORT( A,B,C,D : IN STD_LOGIC;
F1,F2,F3 : OUT STD_LOGIC);
END FUNCIONES;
ARCHITECTURE FUNCION OF FUNCIONES IS
BEGIN
F1 <=((NOT D)AND ((NOT A) OR (NOT B))) OR (A AND B AND (NOT C));
F2 <=(A AND(NOT B)AND C) OR ((NOT A)AND(NOT C))OR((NOT D)AND(B OR C));
F3 <=((NOT A)AND B AND(NOT D))OR((NOT C)AND(A OR(NOT D)));
END FUNCION;
Tabla de verdad de las funciones
c) DISEÑO DE UNIDAD ARITMÉTICA LÓGICA (ALU) DE USO ESPECIFICO*

Diseñar una ALU con las especificaciones siguientes:

• A y B son números de 4 bits en Binario Natural.
• Consta de tres entradas de selección C2, C1 y C0 que permite controlar las distintas
operaciones.
• Los diferentes resultados deben ser desplegados en display’s de 7 segmentos y LED’s
necesarios, respetando la numeración hexadecimal.
C2 C1 C0 Función Observación
0 0 0 COMP_9 (A-B+3) Complemento a 9
0 0 1 A and B AND (Operación lógica)
0 1 0 A nor B NOR (Operación lógica)
0 1 1 –B Complemento a 2
1 0 0 A–B Resta Aritmética
1 0 1 B+A Suma Aritmética
1 1 0 A–B–1 A – B – 1 (Operación Aritmética)
1 1 1 (A) Transcodificar a código 5421 Transcodificar de BN a BCD
• Implemente un diseño parecido para laboratorio, tomando solo 2 entradas de selección.
--ALU B-A, A NOR B, A AND B, A+B

LIBRARY IEEE;
ENTITY ALU IS
PORT ( A,B :IN STD_LOGIC_VECTOR (3 DOWNTO 0);
S: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
F: OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
COUT : OUT STD_LOGIC);
END ALU;
ARCHITECTURE ALU_ESTRUCTURAL OF ALU IS

SIGNAL M : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL N : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL P : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL Q : STD_LOGIC_VECTOR(3 DOWNTO 0);
COMPONENT B_A
PORT (A,B :IN STD_LOGIC;
F: OUT STD_LOGIC);
END COMPONENT;
COMPONENT A_nor_B
PORT ( A,B :IN STD_LOGIC;
F : OUT STD_LOGIC);
END COMPONENT;
COMPONENT A_and_B
PORT ( A,B :IN STD_LOGIC;
F : OUT STD_LOGIC);
END COMPONENT;
COMPONENT fulladd_4b
PORT( A, B : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
CIN : IN STD_LOGIC;
S : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
END COMPONENT;
COMPONENT mux4a1
PORT(D0,D1,D2,D3: IN STD_LOGIC;
S:IN STD_LOGIC_VECTOR(1 DOWNTO 0);
F:OUT STD_LOGIC);
END COMPONENT;
BEGIN
GEN_BA : FOR i IN 3 DOWNTO 0 GENERATE
CNXBA : B_A PORT MAP (A(i),B(i),M(i));
END GENERATE;
GEN_NOR : FOR i IN 3 DOWNTO 0 GENERATE

CNXNOR : A_nor_B PORT MAP (A(i),B(i),N(i));
END GENERATE;
GEN_AND : FOR i IN 3 DOWNTO 0 GENERATE

CNXAND : A_and_B PORT MAP (A(i),B(i),P(i));
END GENERATE;
CNXFA : FULladd_4b PORT MAP (A,B,'0',Q, COUT);
GEN_MUX : FOR i IN 3 DOWNTO 0 GENERATE

cnxSIG_MUX : MUX4a1 PORT MAP (M(i),N(i),P(i),Q(i),S,F(i));
end generate;
END ALU_ESTRUCTURAL;
PAQUETE 1
LIBRARY IEEE;
ENTITY B_A IS
F: OUT STD_LOGIC);
END B_A ;
ARCHITECTURE ESTRUCTURAL OF B_A IS
BEGIN
F<= ( B OR( NOT A) );
END ESTRUCTURAL;
PAQUETE 2
LIBRARY IEEE;
ENTITY A_nor_B IS
F: OUT STD_LOGIC);
END A_nor_B;
ARCHITECTURE ESTRUCTURAL OF A_nor_B IS
BEGIN
F <=(A NOR B);
END ESTRUCTURAL;
PAQUETE 3
LIBRARY IEEE;
ENTITY A_and_B IS
F: OUT STD_LOGIC);
END A_and_B;
ARCHITECTURE ESTRUCTURAL OF A_and_B IS
BEGIN
F<= A AND B;
END ESTRUCTURAL;
PAQUETE 4
LIBRARY IEEE; --LIBRERIA IEEE
USE IEEE.STD_LOGIC_1164.ALL;--PAQUETE STD_LOGIC
ENTITY FULLADD_4B IS --INICIO DE LA ENTIDAD

PORT( A, B:IN STD_LOGIC_VECTOR(3 DOWNTO 0);--PUERTOS DE ENTRADA/SALIDA
CIN:IN STD_LOGIC; -- A, B, COUT ENTRADAS Y SALIDA
S:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- DE TIPO VECTOR DE 4 BITS
END FULLADD_4B; --FIN DE LA ENTIDAD
ARCHITECTURE SUMADOR4B OF FULLADD_4B IS
--ARQUITECTURA
SIGNAL M : STD_LOGIC_VECTOR(2 DOWNTO 0);
--DECLARACION DE LA SEÑAL M
COMPONENT FULLADD_1B
--DECLARACION DE LOS COMPONENTES A
PORT( A,B : IN STD_LOGIC;
--UTILIZAR EN LA AQUITECTURA
CI : IN STD_LOGIC;
S : OUT STD_LOGIC;
END COMPONENT;
BEGIN --INICIO DE LA ARQUITECTURA
--CONEXION DE LAS ENTRADAS,

CNXIN_FA0: FULLADD_1B PORT MAP (A(0),B(0),CIN,S(0),M(0));
--SALIDAS Y SEÑALES INTERNAS CNXFA0_FA0: FULLADD_1B PORT MAP
(A(1),B(1),M(0),S(1),M(1));
--MEDIANTE LAS INTRUCCIONES

CNXFA1_FA2: FULLADD_1B PORT MAP (A(2),B(2),M(1),S(2),M(2));
-- "PORT MAP"
CNXFA2_FA3: FULLADD_1B PORT MAP (A(3),B(3),M(2),S(3),COUT);
END SUMADOR4B;
PAQUETE 5
LIBRARY IEEE; --LIBRERIA IEEE
USE IEEE.STD_LOGIC_1164.ALL; --PAQUETE STD_LOGIC
ENTITY fulladd_1b IS --INICIO DE LA ENTIDAD

PORT( A,B : IN STD_LOGIC; --PUERTOS DE ENTRADA/SALIDA
CI : IN STD_LOGIC; --
S : OUT STD_LOGIC;
END fulladd_1b; --FIN DE LA ENTIDAD
ARCHITECTURE SUMADOR OF fulladd_1b IS --ARQUITECTURA

BEGIN
S <= A XOR (B XOR CI); --CUERPO DE LA ARQUITECTURA
COUT <= (A AND B) OR (B AND CI) OR (A AND CI);
END SUMADOR;
PAQUETE 6
LIBRARY IEEE;
ENTITY mux4a1 IS
PORT(D0,D1,D2,D3: IN STD_LOGIC;
S:IN STD_LOGIC_VECTOR(1 DOWNTO 0);
F:OUT STD_LOGIC);
END mux4a1;
ARCHITECTURE comportamiento OF mux4a1 IS
BEGIN
WITH S SELECT
F<= D0 WHEN "00",
D1 WHEN "01",
D2 WHEN "10",
D3 WHEN OTHERS;
END comportamiento;
VHDL de ALU con funciones F1, F2, F4 Y F8

d) CIRCUITO MULTIPLICADOR*
Diseñe en base a circuitos sumadores, un circuito multiplicador combinacional para los siguientes dos
números (83 𝑝𝑜𝑟 68) de código BCD 8421 (de dos dígitos cada uno), además del bit de signo. El
resultado debe ser desplegado en display’s de 7 segmentos. Implemente un diseño para un dígito, por
ejemplo (7 𝑝𝑜𝑟 9).
PAQUETE 1
LIBRARY IEEE;
ENTITY ANDS IS
M: IN STD_LOGIC;
END ANDS;
ARCHITECTURE FUNCION OF ANDS IS
BEGIN
P <= X WHEN M='1' ELSE "0000";
END FUNCION;
PAQUETE 2
LIBRARY IEEE;
ENTITY SUMCUA IS
CI: IN STD_LOGIC;
END SUMCUA;
ARCHITECTURE FUNCION OF SUMCUA IS
SIGNAL CARRYS: STD_LOGIC_VECTOR(2 DOWNTO 0);
COMPONENT SUMCOM IS
END COMPONENT;
BEGIN
SUM1: SUMCOM PORT MAP(A(0),B(0),CI,S(0),CARRYS(0));
SUM4: SUMCOM PORT MAP(A(3),B(3),CARRYS(2),S(3),COUT);
END FUNCION;
PAQUETE 3
LIBRARY IEEE;
ENTITY SUMCOM IS
END SUMCOM;
ARCHITECTURE FUNCION OF SUMCOM IS
BEGIN
S <= A XOR B XOR CI;
CO <= (A AND B) OR (A AND CI) OR (B AND CI);
END FUNCION;
PAQUETE COMPLETO
LIBRARY IEEE;
ENTITY CIRCUITO_MULTIPLICADOR IS
PORT(X,Y: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END CIRCUITO_MULTIPLICADOR;
ARCHITECTURE FUNCION OF CIRCUITO_MULTIPLICADOR IS
SIGNAL P1,P2,P3,P4: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL S1,S2,S3: STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL AUX: STD_LOGIC_VECTOR(3 DOWNTO 0);
--BLOQUES ANDS
COMPONENT ANDS IS
M: IN STD_LOGIC;
END COMPONENT;
--SUMADOR DE 4 BITS
COMPONENT SUMCUA IS
CI: IN STD_LOGIC;
END COMPONENT;
--FUNCIONAMIENTO
BEGIN
--CREACION DE LOS BLOQUES AND
--LA PRIMERA ENTRADA
AUX <= '0'&P1(3 DOWNTO 1);
--CREACION DE LOS BLOQUES DE SUMA
SUMADOR1: SUMCUA PORT MAP(AUX,P2,'0',S1(3 DOWNTO 0),S1(4));
--CONCATENACION PARA LA SALIDA
S <= S3&S2(0)&S1(0)&P1(0);
END FUNCION;
VHDL multiplicación
RTL en del código vhdl

e) CIRCUITO DIVISOR*
Diseñe en base a circuitos sumadores, un circuito divisor combinacional para un dividendo de 4 bits
con un divisor de 3 bits. de código BCD Exceso de 3 Desplegar el cociente y el residuo en display’s
de 7 segmentos.
LIBRARY IEEE;
USE IEEE.NUMERIC_STD.ALL;
ENTITY CIRCUITO_DIVISOR IS
GENERIC (SIZE: NATURAL := 4);
PORT (
A: IN STD_LOGIC_VECTOR(SIZE-1 DOWNTO 0);
B: IN STD_LOGIC_VECTOR(SIZE-1 DOWNTO 0);
Q: INOUT STD_LOGIC_VECTOR(SIZE-1 DOWNTO 0);
R: INOUT STD_LOGIC_VECTOR(SIZE-1 DOWNTO 0);
Q7SEG: OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
R7SEG: OUT STD_LOGIC_VECTOR(6 DOWNTO 0));
END CIRCUITO_DIVISOR;
ARCHITECTURE FUNCION OF CIRCUITO_DIVISOR IS

SIGNAL AUNS, BUNS, QUNS, RUNS: UNSIGNED(SIZE-1 DOWNTO 0);
BEGIN
AUNS <= UNSIGNED(A);

BUNS <= UNSIGNED(B);
QUNS <= AUNS/BUNS;

RUNS <= AUNS REM BUNS;
Q <= STD_LOGIC_VECTOR(QUNS);
R <= STD_LOGIC_VECTOR(RUNS);
WITH Q SELECT
Q7SEG<=
"0000001" WHEN "0011",
"1001111" WHEN "0100",
"0010010" WHEN "0101",
"0000110" WHEN "0110",
"1001100" WHEN "0111",
"0100100" WHEN "1000",
"0100000" WHEN "1001",
"0001111" WHEN "1010",
"0000000" WHEN "1011",
"0000100" WHEN "1100",
WITH R SELECT
R7SEG<=
"0000001" WHEN "0011",
"1001111" WHEN "0100",
"0010010" WHEN "0101",
"0000110" WHEN "0110",
"1001100" WHEN "0111",
"0100100" WHEN "1000",
"0100000" WHEN "1001",

"0001111" WHEN "1010",
"0000000" WHEN "1011",
"0000100" WHEN "1100",
END FUNCION;
VHDL divisor de 4 bits con un divisor de 3 bits
RTL del Código VHDL

VHDL Prei Nforme 4

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VHDL Prei Nforme 4

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AUX. UNIV.

Joel Bautista España Ulloa laboratorio 4 ETN – 601

a) DISEÑO DE SUMADORES BCD*

SUM1: SUMCOM PORT MAP(A(0),B(0),CI,S(0),CARRYS(0));

"1001" WHEN (A= "0001") ELSE

--UNION DE LOS PAQUETES--

ARCHITECTURE FUNCION OF SUMADOR_BCD IS

SUMADOR con su bit de signo

DIAGRAMA DE TIEMPO Y RTL

b) LÓGICA COMBINACIONAL CON SUMADORES*

"1000001" WHEN "0101001",--41

b.3) Sintetice las siguientes funciones utilizando únicamente sumadores:

F1 =∑4 (0,2,4,6,8,12,13) + ∑ø4 (10)

F2 =∑4 (0,2,5,6,11,12,14) + ∑ø4 (1,4,10)

F3 =∑4 (0,4,6,9,13) + ∑ø4 (8,12,15)

Tabla de verdad de las funciones

c) DISEÑO DE UNIDAD ARITMÉTICA LÓGICA (ALU) DE USO ESPECIFICO*

Diseñar una ALU con las especificaciones siguientes:

--ALU B-A, A NOR B, A AND B, A+B

ARCHITECTURE ALU_ESTRUCTURAL OF ALU IS

GEN_NOR : FOR i IN 3 DOWNTO 0 GENERATE

GEN_AND : FOR i IN 3 DOWNTO 0 GENERATE

CNXFA : FULladd_4b PORT MAP (A,B,'0',Q, COUT);

GEN_MUX : FOR i IN 3 DOWNTO 0 GENERATE

ENTITY FULLADD_4B IS --INICIO DE LA ENTIDAD

BEGIN --INICIO DE LA ARQUITECTURA

--CONEXION DE LAS ENTRADAS,

--MEDIANTE LAS INTRUCCIONES

ENTITY fulladd_1b IS --INICIO DE LA ENTIDAD

ARCHITECTURE SUMADOR OF fulladd_1b IS --ARQUITECTURA

VHDL de ALU con funciones F1, F2, F4 Y F8

RTL en del código vhdl

ARCHITECTURE FUNCION OF CIRCUITO_DIVISOR IS

AUNS <= UNSIGNED(A);

QUNS <= AUNS/BUNS;

"0100000" WHEN "1001",

VHDL divisor de 4 bits con un divisor de 3 bits

RTL del Código VHDL

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