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System Verilog for DV Interns

1. What is the difference between wire and reg?

2. Difference between task and function?
3. Difference between inter statement and intra statement delay?
4. Difference between $monitor, $display & $strobe?
5. Difference between Synchronous and Asynchronous?
6. Given the following Verilog code, what value of "a" is displayed?
always @(clk) begin
a = 0;
a <= 1;
$display(a);
end
7. Write Difference between “fork… join, join_any, join_noon” with example?
8. Draw the Circuit diagram for the following Verilog codes:

(a) module target (clk, regA, regB, mask); (b) module vector_operand (Bi,stdy,tap);
input [0:3] Bi,stdy;
input clk;
output [0:3] tap;
input [3:0] regA, mask;
output [3:0] regB;
assign tap = Bi ^ stdy;
reg [3:0] regB;
endmodule
Always @ (posedge clk)
regB <= regA & mask;

endmodule

9. Difference b/w bit and logic?

10. Difference between reg, wire, logic?
11. List out different types of arrays?
12. Difference b/w byte and [7:0] bit?
13. Difference b/w structures and unions?
14. Explain polymorphism, inheritance, and encapsulation?
15. What is semaphore, mailbox, and events?
16. Difference b/w rand, randc?
17. What is the difference between shallow and deep copy ? Explain with an example.
18. Explain Difference Between Local and Protected with example?
19. What are different types of constraints? Explain with an example.
20. Why do you need to write super.new() as first line of constructor in extended
classes? When do you need to pass any arguments to this function - super.new().
21. What is Virtual Method and Abstract Class?
22. Write interface for the following sequential Single port memory
module spmemory(
address,
data_in,
data_out,
read_write,
clk,
rst );