a Stereo, 24-Bit, 192 kHz, Multibit
 DAC

AD1853
FEATURES
5 V Stereo Audio DAC System
Accepts 16-/18-/20-/24-Bit Data
Supports 24 Bits and 192 kHz Sample Rate
Accepts a Wide Range of Sample Rates Including:
32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz and 192 kHz
Multibit Sigma-Delta Modulator with “Perfect Differential
Linearity Restoration” for Reduced Idle Tones and
Noise Floor
Data Directed Scrambling DAC—Least Sensitive to Jitter
APPLICATIONS
Hi End: DVD, CD, Home Theater Systems, Automotive
Audio Systems, Sampling Musical Keyboards, Digital
Mixing Consoles, Digital Audio Effects Processors
PRODUCT OVERVIEW
The AD1853 is a complete high performance single-chip stereo
digital audio playback system. It is comprised of a high per-

Differential Output for Optimum Performance
120 dB Signal to Noise (Not Muted) at 48 kHz
(A-Weighted Mono)
117 dB Signal to Noise (Not Muted) at 48 kHz
(A-Weighted Stereo)
119 dB Dynamic Range (Not Muted) at 48 kHz Sample
Rate (A-Weighted Mono)
116 dB Dynamic Range (Not Muted) at 48 kHz Sample
Rate (A-Weighted Stereo) LE
–107 dB THD+N (Mono Application Circuit, See Figure 30)
–104 dB THD+N (Stereo)
115 dB Stopband Attenuation (96 kHz)
On-Chip Clickless Volume Control
Hardware and Software Controllable Clickless Mute
Serial (SPI) Control for: Serial Mode, Number of Bits,
SO
Interpolation Factor, Volume, Mute, De-Emphasis, Reset
Digital De-Emphasis Processing for 32, 44.1 and 48 kHz
Sample Rates
Clock Auto-Divide Circuit Supports Five Master-Clock
Frequencies
Flexible Serial Data Port with Right-Justified, Left-
Justified, I2S-Compatible and DSP Serial Port Modes
28-Lead SSOP Plastic Package
B
TE
formance digital interpolation filter, a multibit sigma-delta
modulator, and a continuous-time current-out analog DAC
section. Other features include an on-chip clickless stereo at-
tenuator and mute capability, programmed through an SPI-
compatible serial control port. The AD1853 is fully compatible
with all known DVD formats and supports 48 kHz, 96 kHz and
192 kHz sample rates with up to 24 bits word lengths. It also
provides the “Redbook” standard 50 µs/15 µs digital de-emphasis
filters at sample rates of 32 kHz, 44.1 kHz and 48 kHz.
The AD1853 has a very flexible serial data input port that
allows for glueless interconnection to a variety of ADCs, DSP
chips, AES/EBU receivers and sample rate converters. The
AD1853 can be configured in left-justified, I2S, right-justified,
or DSP serial port compatible modes. The AD1853 accepts
serial audio data in MSB first, twos complement format.
The AD1853 operates from a single +5 V power supply. It is
fabricated on a single monolithic integrated circuit and is housed in
a 28-lead SSOP package for operation over the temperature
range 0°C to +70°C.

FUNCTIONAL BLOCK DIAGRAM

CONTROL DATA DIGITAL CLOCK

INT2 INT4 INPUT SUPPLY IN
VOLUME
O

MUTE 3 2

AD1853 SERIAL CONTROL VOLTAGE AUTO-CLOCK

INTERFACE REFERENCE DIVIDE CIRCUIT

DIGITAL ATTEN/ 8  FS MULTIBIT SIGMA-

DELTA MODULATOR IDAC
DATA INPUT MUTE INTERPOLATOR
SERIAL ANALOG
DATA OUTPUTS
INTERFACE
SERIAL 2 ATTEN/ 8  FS MULTIBIT SIGMA-
MODE DELTA MODULATOR IDAC
MUTE INTERPOLATOR

2 2
RESET MUTE DE-EMPHASIS ANALOG ZERO
SUPPLY FLAG

REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 1999
AD1853–SPECIFICATIONS
TEST CONDITIONS UNLESS OTHERWISE NOTED
Supply Voltages (AVDD, DVDD) +5.0 V
Ambient Temperature +25°C
Input Clock 24.576 MHz (512 × FS Mode)
Input Signal 996.094 kHz
–0.5 dB Full Scale
Input Sample Rate 48 kHz
Measurement Bandwidth 20 Hz to 20 kHz
Word Width 20 Bits
Input Voltage HI 3.5 V
Input Voltage LO 0.8 V

ANALOG PERFORMANCE (See Figures)

Min Typ Max Units
Resolution 24 Bits
Signal-to-Noise Ratio (20 Hz to 20 kHz)

TE
No Filter (Stereo) 114 dB
No Filter (Mono—See Figure 30) 117 dB
With A-Weighted Filter (Stereo) 117 dB
With A-Weighted Filter (Mono—See Figure 30) 120 dB
Dynamic Range (20 Hz to 20 kHz, –60 dB Input)
No Filter (Stereo) 107.5 113 dB
No Filter (Mono—See Figure 30) 116 dB
With A-Weighted Filter (Stereo)
With A-Weighted Filter (Mono—See Figure 30)
Total Harmonic Distortion + Noise (Stereo)

Total Harmonic Distortion + Noise (Mono—See Figure 30)

LE 110

–94
116
119
–104
0.00063
–107
dB
dB
dB
%
dB
0.00045 %
Analog Outputs
Differential Output Range (± Full Scale w/1 mA into IREF) 3.0 mA p-p
SO
Output Capacitance at Each Output Pin 30 pF
Out-of-Band Energy (0.5 × FS to 75 kHz) –90 dB
CMOUT 2.75 V
DC Accuracy
Gain Error ± 3.0 %
Interchannel Gain Mismatch –0.15 0.01 +0.15 dB
Gain Drift 25 ppm/°C
Interchannel Crosstalk (EIAJ Method) –125 dB
B

Interchannel Phase Deviation ± 0.1 Degrees

Mute Attenuation –100 dB
De-Emphasis Gain Error ± 0.1 dB
NOTES
O

Single-ended current output range: 1 mA ± 0.75 mA.

Performance of right and left channels are identical (exclusive of the Interchannel Gain Mismatch and Interchannel Phase Deviation specifications).
Specifications subject to change without notice.

DIGITAL I/O (+25C–AVDD, DVDD = +5.0 V  10%)

Min Typ Max Units
Input Voltage HI (VIH) 2.4 V
Input Voltage LO (VIL) 0.8 V
Input Leakage (IIH @ VIH = 3.5 V) 10 µA
Input Leakage (IIL @ VIL = 0.8 V) 10 µA
Input Capacitance 20 pF
Output Voltage HI (VOH) DVDD–0.5 DVDD–0.4 V
Output Voltage LO (VOL) 0.2 0.5 V
Specifications subject to change without notice.

–2– REV. A
 AD1853
POWER
Min Typ Max Units
Supplies
Voltage, Analog and Digital 4.5 5 5.5 V
Analog Current 12 15 mA
Digital Current 28 33 mA
Dissipation
Operation—Both Supplies 200 mW
Operation—Analog Supply 60 mW
Operation—Digital Supply 140 mW
Power Supply Rejection Ratio
1 kHz 300 mV p-p Signal at Analog Supply Pins –77 dB
20 kHz 300 mV p-p Signal at Analog Supply Pins –72 dB
Specifications subject to change without notice.

TE
TEMPERATURE RANGE
Min Typ Max Units
Specifications Guaranteed 25 °C
Functionality Guaranteed 0 70 °C
Storage –55 125 °C
Specifications subject to change without notice.

DIGITAL FILTER CHARACTERISTICS

Sample Rate (kHz)
44.1
Passband (kHz)
DC–20
LE
Stopband (kHz)
24.1–328.7
Stopband Attenuation (dB)
110
Passband Ripple (dB)
± 0.0002
48 DC–21.8 26.23–358.28 110 ± 0.0002
96 DC–39.95 56.9–327.65 115 ± 0.0005
SO
192 DC–87.2 117–327.65 95 +0/–0.04 (DC–21.8 kHz)
+0/–0.5 (DC–65.4 kHz)
+0/–1.5 (DC–87.2 kHz)
Specifications subject to change without notice.

GROUP DELAY
Chip Mode Group Delay Calculation FS Group Delay Units
B

INT8x Mode 5553/(128 × FS) 48 kHz 903.8 µs

INT4x Mode 5601/(64 × FS) 96 kHz 911.6 µs
INT2x Mode 5659/(32 × FS) 192 kHz 921 µs
Specifications subject to change without notice.
O

DIGITAL TIMING (Guaranteed Over 0C to +70C, AVDD = DVDD = +5.0 V  10%)
Min Units
tDMP MCLK Period (With FMCLK = 256 × FLRCLK)* 54 ns
tDML MCLK LO Pulsewidth (All Modes) 0.4 × tDMP ns
tDMH MCLK HI Pulsewidth (All Modes) 0.4 × tDMP ns
tDBH BCLK HI Pulsewidth 20 ns
tDBL BCLK LO Pulsewidth 20 ns
tDBP BCLK Period 140 ns
tDLS LRCLK Setup 20 ns
tDLH LRCLK Hold (DSP Serial Port Mode Only) 5 ns
tDDS SDATA Setup 5 ns
tDDH SDATA Hold 10 ns
tPDRP PD/RST LO Pulsewidth 5 ns
*Higher MCLK frequencies are allowable when using the on-chip Master Clock Auto-Divide feature.
Specifications subject to change without notice.

REV. A –3–
AD1853
ABSOLUTE MAXIMUM RATINGS* PIN CONFIGURATION
Min Max Units
DVDD to DGND –0.3 6 V DGND 1 28 DVDD
AVDD to AGND –0.3 6 V MCLK 2 27 SDATA
Digital Inputs DGND – 0.3 DVDD + 0.3 V CLATCH 3 26 BCLK
Analog Outputs AGND – 0.3 AVDD + 0.3 V CCLK 4 25 L/RCLK
AGND to DGND –0.3 0.3 V CDATA 5 24 RST
Reference Voltage (AVDD + 0.3)/2 INT4 6 23 MUTE
Soldering +300 °C INT2 7
AD1853
TOP VIEW 22 ZEROL
10 sec ZEROR 8 (Not to Scale) 21 IDPM0

*Stresses greater than those listed under Absolute Maximum Ratings may cause DEEMP 9 20 IDPM1
permanent damage to the device. This is a stress rating only; functional operation IREF 10 19 FILTB
of the device at these or any other conditions above those indicated in the AGND 11 18 AVDD
operational section of this specification is not implied. Exposure to absolute
OUTL+ 12 17 OUTR+
maximum rating conditions for extended periods may affect device reliability.
OUTL– 13 OUTR–

TE
16

FILTR 14 15 FCR
PACKAGE CHARACTERISTICS
Min Typ Max Units
θJA (Thermal Resistance
[Junction-to-Ambient]) 109 °C/W
θJC (Thermal Resistance
[Junction-to-Case]) 39 °C/W

Model Temperature
LEORDERING GUIDE

Package Description Package Options

AD1853JRS 0°C to +70°C 28-Lead Shrink Small Outline RS-28
AD1853JRSRL 0°C to +70°C 28-Lead Shrink Small Outline RS-28 on 13" Reels
SO

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. WARNING!
Although the AD1853 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD ESD SENSITIVE DEVICE
precautions are recommended to avoid performance degradation or loss of functionality.
B
O

–4– REV. A
 AD1853
PIN FUNCTION DESCRIPTIONS

Pin Input/Output Pin Name Description

1 I DGND Digital Ground.
2 I MCLK Master Clock Input. Connect to an external clock source. See Table II for allowable
frequencies.
3 I CLATCH Latch input for control data. This input is rising-edge sensitive.
4 I CCLK Control clock input for control data. Control input data must be valid on the rising edge
of CCLK. CCLK may be continuous or gated.
5 I CDATA Serial control input, MSB first, containing 16 bits of unsigned data. Used for specifying
control information and channel-specific attenuation.
6 I INT4× Assert HI to select interpolation ratio of 4×, for use with double-speed inputs (88 kHz or
96 kHz). Assert LO to select 8× interpolation ratio.
7 I INT2× Assert HI to select interpolation ratio of 2×, for quad-speed inputs (176 kHz or 192 kHz).

TE
Assert LO to select 8× interpolation ratio.
8 O ZEROR Right Channel Zero Flag Output. This pin goes HI when Right Channel has no signal
input for more than 1024 LR Clock Cycles.
9 I DEEMP De-Emphasis. Digital de-emphasis is enabled when this input signal is HI. This is used to
impose a 50 µs/15 µs response characteristic on the output audio spectrum at an assumed
44.1 kHz sample rate. Curves for 32 kHz and 48 kHz sample rates may be selected via
SPI control register.
10
11
12
13
14
I
I
O
O
O
IREF
AGND
OUTL+
OUTL–
FILTR
LE
Connection point for external bias resistor. Voltage held at VREF.
Analog Ground.
Left Channel Positive line level analog output.
Left Channel Negative line level analog output.
Voltage Reference Filter Capacitor Connection. Bypass and decouple the voltage refer-
ence with parallel 10 µF and 0.1 µF capacitors to the AGND (Pin 11).
15 I FCR Filter cap return pin for cap connected to FILTB (Pin 19).
SO
16 O OUTR– Right Channel Negative line level analog output.
17 O OUTR+ Right Channel Positive line level analog output.
18 I AVDD Analog Power Supply. Connect to analog +5 V supply.
19 O FILTB Filter Capacitor connection, connect 10 µF capacitor to FCR (Pin 15).
20 I IDPM1 Input serial data port mode control one. With IDPM0, defines one of four serial modes.
21 I IDPM0 Input serial data port mode control zero. With IDPM1, defines one of four serial modes.
22 O ZEROL Left Channel Zero Flag output. This pin goes HI when Left Channel has no signal input
B

for more than 1024 LR Clock Cycles.

23 I MUTE Mute. Assert HI to mute both stereo analog outputs. Deassert LO for normal operation.
24 I RST Reset. The AD1853 is placed in a reset state when this pin is held LO. The AD1853 is
reset on the rising edge of this signal. The serial control port registers are reset to the
O

default values. Connect HI for normal operation.

25 I L/RCLK Left/Right clock input for input data. Must run continuously.
26 I BCLK Bit clock input for input data.
27 I SDATA Serial input, MSB first, containing two channels of 16/18/20/24 bit twos-complement
data.
28 I DVDD Digital Power Supply Connect to digital +5 V supply.

REV. A –5–
AD1853
L/RCLK LEFT CHANNEL RIGHT CHANNEL
INPUT

BCLK
INPUT

SDATA LSB MSB MSB–1 MSB–2 LSB+2 LSB+1 LSB MSB MSB–1 MSB–2 LSB+2 LSB+1 LSB
INPUT

Figure 1. Right-Justified Mode

L/RCLK LEFT CHANNEL RIGHT CHANNEL

INPUT

BCLK
INPUT

TE
SDATA MSB MSB–1 MSB–2 LSB+2 LSB+1 LSB MSB MSB–1 MSB–2 LSB+2 LSB+1 LSB MSB
INPUT

Figure 2. I2S-Justified Mode

L/RCLK
INPUT

BCLK
INPUT

SDATA
INPUT
MSB MSB–1 MSB–2
LEFT CHANNEL

LSB+2 LSB+1 LSB

LE MSB MSB–1 MSB–2
RIGHT CHANNEL

LSB+2 LSB+1 LSB MSB MSB–1

Figure 3. Left-Justified Mode

SO

L/RCLK RIGHT CHANNEL

LEFT CHANNEL
INPUT

BCLK
INPUT

SDATA MSB MSB–1 LSB+2 LSB+1 LSB MSB MSB–1 LSB+2 LSB+1 LSB MSB MSB–1
B

INPUT

Figure 4. Left-Justified DSP Mode

O

L/RCLK
INPUT LEFT CHANNEL RIGHT CHANNEL

BCLK
INPUT

SDATA LSB MSB MSB–1 MSB–2 LSB+2 LSB+1 LSB MSB MSB–1 MSB–2 LSB+2 LSB+1 LSB MSB MSB–1
INPUT

Figure 5. 32 × FS Packed Mode

–6– REV. A

OPERATING FEATURES
Serial Data Input Port
The AD1853’s flexible serial data input port accepts data in
twos-complement, MSB-first format. The left channel data field
always precedes the right channel data field. The serial mode is
set by using either the external mode pins (IDPM0 Pin 21 and
IDPM1 Pin 20) or the mode select bits (Bits 4 and 5) in the SPI
control register. To control the serial mode using the external
mode pins, the SPI mode select bits should be set to zero
(default at power-up). To control the serial mode using the SPI
mode select bits, the external mode control pins should be
grounded.
In all modes except for the right-justified mode, the serial port
will accept an arbitrary number of bits up to a limit of 24 (extra
bits will not cause an error, but they will be truncated inter-
AD1853
Figure 1 shows the right-justified mode. LRCLK is HI for the
left channel, LO for the right channel. Data is valid on the rising
edge of BCLK.
In normal operation, there are 64-bit clocks per frame (or 32
per half-frame). When the SPI word length control bits (Bits 8
and 9 in the control register) are set to 24 bits (0:0), the serial
port will begin to accept data starting at the 8th bit clock pulse
after the L/RCLK transition. When the word length control bits
are set to 20-bit mode, data is accepted starting at the 12th bit
clock position. In 16-bit mode, data is accepted starting at the
16th-bit clock position. These delays are independent of the
number of bit clocks per frame, and therefore other data formats
are possible using the delay values described above. For detailed
timing, see Figure 6.
Figure 2 shows the I2S mode. L/RCLK is LO for the left chan-

nally). In the right-justified mode, control register Bits 8 and 9
are used to set the word length to 16, 20, or 24 bits. The default
on power-up is 24-bit mode. When the SPI Control Port is not
being used, the SPI pins (3, 4 and 5) should be tied LO.
Serial Data Input Mode
The AD1853 uses two multiplexed input pins to control the
mode configuration of the input data port mode.
TE
nel, and HI for the right channel. Data is valid on the rising
edge of BCLK. The MSB is left-justified to an L/RCLK transi-
tion but with a single BCLK period delay. The I2S mode can be
used to accept any number of bits up to 24.
Figure 3 shows the left-justified mode. L/RCLK is HI for the
left channel, and LO for the right channel. Data is valid on the
rising edge of BCLK. The MSB is left-justified to an L/RCLK

IDPM1
(Pin 20)
Table I. Serial Data Input Modes

IDPM0
(Pin 21)
0 0
0 1
1 0
SO
1 1
Serial Data Input Format
LE transition, with no MSB delay. The left-justified mode can
accept any word length up to 24 bits.
Figure 4 shows the DSP serial port mode. L/RCLK must pulse
HI for at least one bit clock period before the MSB of the left
channel is valid, and L/RCLK must pulse HI again for at least
Right Justified (24 Bits) Default one bit clock period before the MSB of the right channel is
I2S-Compatible valid. Data is valid on the falling edge of BCLK. The DSP serial
Left Justified
port mode can be used with any word length up to 24 bits.
DSP

tDBH tDBP
BCLK

tDBL

tDLS
B

L/RCLK

tDDS
SDATA
LEFT-JUSTIFIED MSB MSB-1
O

MODE
tDDH
tDDS
SDATA
I2S-JUSTIFIED MSB
MODE
tDDH

tDDS tDDS
SDATA
RIGHT-JUSTIFIED MSB LSB
MODE
tDDH tDDH
8-BIT CLOCKS
(24-BIT DATA)

12-BIT CLOCKS
(20-BIT DATA)

16-BIT CLOCKS
(16-BIT DATA)

Figure 6. Serial Data Port Timing

REV. A –7–
AD1853
Table II.
Chip Mode Allowable Master Clock Frequencies
INT8× Mode 256 × FS, 384 × FS, 512 × FS, 768 × FS, 1024 × FS
INT4× Mode 128 × FS, 192 × FS, 256 × FS, 384 × FS, 512 × FS
INT2× Mode 64 × FS, 96 × FS, 128 × FS, 192 × FS, 256 × FS
In this mode, it is the responsibility of the DSP to ensure that
the left data is transmitted with the first LRCLK pulse, and that
synchronism is maintained from that point forward.
Note that the AD1853 is capable of a 32 × FS BCLK frequency
“packed mode” where the MSB is left-justified to an L/RCLK
transition, and the LSB is right-justified to the opposite L/RCLK
transition. L/RCLK is HI for the left channel, and LO for the
right channel. Data is valid on the rising edge of BCLK. Packed
mode can be used when the AD1853 is programmed in right-
justified or left-justified mode. Packed mode is shown is Figure 5.
Master Clock Auto-Divide Feature
The AD1853 has a circuit that autodetects the relationship
between master clock and the incoming serial data, and inter-
modulator. The allowable frequencies for each mode are shown
above.
Serial Control Port
The AD1853 serial control port is SPI-compatible. SPI (Serial
LE
nally sets the correct divide ratio to run the interpolator and
Peripheral Interface) is an industry standard serial port protocol.
The write-only serial control port gives the user access to: select
SO
input mode, soft reset, soft de-emphasis, channel specific at-
tenuation and mute (both channels at once). The SPI port is a
3-wire interface with serial data (CDATA), serial bit clock
(CCLK), and data latch (CLATCH). The data is clocked
into an internal shift register on the rising edge of CCLK.
The serial data should change on the falling edge of CCLK and
be stable on the rising edge of CCLK. The rising edge of
B
t CHD
CDATA D15 D14
t CCH
O
CCLK
t CCL t CSU
CLATCH
Figure 7. Serial Control Port Timing
–8–
Nominal Input Internal Sigma-Delta
Sample Rate Clock Rate
48 kHz 128 × FS
96 kHz 64 × FS
192 kHz 32 × FS
CLATCH is used internally to latch the parallel data from the
serial-to-parallel converter. This rising edge should be aligned
with the falling edge of the last CCLK pulse in the 16-bit frame.
The CCLK can run continuously between transactions.
The serial control data is 16-bit MSB first, and is unsigned. Bits
0 and 1 are used to select 1 of 3 registers (control, volume left,
TE
and volume right). The remaining 14 bits (bits 15:2) are used to
carry the data for the selected register. If a volume register is
selected, then the upper 14 bits are used to multiply the digital
input signal by the control word, which is interpreted as an
unsigned number (for example, 11111111111111 is 0 dB, and
01111111111111 is –6 dB, etc.). The default volume control
words on power-up are all 1s (0 dB). The control register only
uses bits 11:2 to carry data; the upper bits (15:12) should al-
ways be written with zeroes, as several test modes are decoded
from these upper bits. The control register defaults on power-up
to 8× interpolation mode, 24-bit right-justified serial mode,
unmuted, and no de-emphasis filter. The intent with these reset
defaults is to enable AD1853 applications without requiring the
use of the serial control port. For those users that do not use the
serial control port, it is still possible to mute the AD1853 output
by using the MUTE pin (Pin 23) signal.
Note that the serial control port timing is asynchronous to the
serial data port timing. Changes made to the attenuator level
will be updated on the next edge of the LRCLK after CLATCH
write pulse as shown in Figure 6.
D0
t CLH
t CLL
REV. A
 AD1853
Table III. Digital Timing

Min Units
tCCH CCLK HI Pulsewidth 40 ns
tCCL CCLK LOW Pulsewidth 40 ns
tCSU CDATA Setup Time 10 ns
tCHD CDATA Hold Time 10 ns
tCLL CLATCH LOW Pulsewidth 10 ns
tCLH CLATCH HI Pulsewidth 10 ns

SPI REGISTER DEFINITIONS VOLUME LEFT and VOLUME RIGHT Registers

The SPI port allows flexible control of many chip parameters. A write operation to the left or right volume registers will acti-
It is organized around three registers; a LEFT-CHANNEL vate the “auto-ramp” clickless volume control feature of the
VOLUME register, a RIGHT-CHANNEL VOLUME register AD1853. This feature works as follows. The upper 10 bits of

and a CONTROL register. Each WRITE operation to the
AD1853 SPI control port requires 16 bits of serial data in
MSB-first format. The bottom two bits are used to select one
of three registers, and the top 14 bits are then written to that
register. This allows a write to one of the three registers in a
single 16-bit transaction.
The SPI CCLK signal is used to clock in the data. The incom-
TE
the volume control word will be incremented or decremented by
1 at a rate equal to the input sample rate. The bottom 4 bits are
not fed into the auto-ramp circuit and thus take effect immedi-
ately. This arrangement gives a worst-case ramp time of about
1024/FS for step changes of more than 60 dB, which has been
determined by listening tests to be optimal in terms of pre-
venting the perception of a “click” sound on large volume

to latch the data internally into the AD1853.

Register Addresses
LE
ing data should change on the falling edge of this signal. At the
end of the 16 CCLK periods, the CLATCH signal should rise

The lowest two bits of the 16-bit input word are decoded as
changes. See Figure 8 for a graphical description of how the
volume changes as a function of time.
The 14-bit volume control word is used to multiply the signal,
and therefore the control characteristic is linear, not dB. A con-
stant dB/step characteristic can be obtained by using a lookup
follows to set the register into which the upper 14 bits will be table in the microprocessor that is writing to the SPI port.
written.
SO

Bit 1 Bit 0 Register 0

VOLUME REQUEST REGISTER
0 0 Volume Left
LEVEL – dB

1 0 Volume Right
–60
0 1 Control Register
0
ACTUAL VOLUME REGISTER
B

–60

20ms TIME
O

Figure 8. Smooth Volume Control

REV. A –9–
AD1853
Control Register
The following table shows the functions of the control register. The control register is addressed by having a “01” in the bottom 2 bits
of the 16-bit SPI word. The top 14 bits are then used for the control register.

Bit 11 Bit 10 Bit 9:8 Bit 7 Bit 6 Bit 5:4 Bit 3:2
INT2× Mode INT4× Mode Number of Soft Reset. Soft Mute OR’d Serial Mode OR’d De-Emphasis Filter
OR’d with Pin. OR’d with Pin. Bits in Right- Default = 0 with Pin. with Mode Pins. Select.
Default = 0 Default = 0 Justified Serial Default = 0 IDPMI:IDPM0 0:0 No Filter
Mode. 0:0 Right-Justified 0:1 44.1 kHz Filter
0:0 = 24 0:1 I2S 1:0 32 kHz Filter
0:1 = 20 1:0 Left-Justified 1:1 48 kHz Filter
1:0 = 16 1:1 DSP Mode Default = 0.0
Default = 0:0 Default = 0:0

Mute
The AD1853 offers two methods of muting the analog output.
By asserting the MUTE (Pin 23) signal HI, both the left and
right channel are muted. As an alternative, the user can assert
the mute bit in the serial control register (Bit 6) HI. The AD1853
has been designed to minimize pops and clicks when muting
and unmuting the device by automatically “ramping” the gain
up or down. When the device is unmuted, the volume returns to
the value set in the volume register.
Analog Attenuation
The AD1853 also offers the choice of using IREF (Pin 10) to
attenuate by up to 50 dB in the analog domain. This feature can
be used as an analog volume control. It is also a convenient
LE
place to add a compressor/limiter gain control signal.
Output Drive, Buffering and Loading
SO
The AD1853 analog output stage is able to drive a 1 kΩ (in
series with 2 nF) load. The analog outputs are usually ac
coupled with a 10 µF capacitor.
TE
De-Emphasis
The AD1853 has a built-in de-emphasis filter that can be used
to decode CDs that have been encoded with the standard
“Redbook” 50 µs/15 µs emphasis response curve. Three curves
are available; one each for 32 kHz, 44.1 kHz and 48 kHz sam-
pling rates. The external “DEEMP” pin (Pin 9) turns on the
44.1 kHz de-emphasis filter. The other filters may be selected
by writing to control Bits 2 and 3 in the control register. If the
SPI port is used to control the de-emphasis filter, the external
DEEMP pin should be tied LO.
Control Signals
The IDPM0 and IDPM1 control inputs are normally con-
nected HI or LO to establish the operating state of the AD1853.
They can be changed dynamically (and asynchronously to
LRCLK and the master clock), but it is possible that a click
or pop sound may result during the transition from one serial
mode to another. If possible, the AD1853 should be placed in
mute before such a change is made.

Figures 9–14 show the calculated frequency response of the plots is higher than the actual noise floor of the AD1853. This is
digital interpolation filters. Figures 15–27 show the performance caused by the higher noise floor of the “High Bandwidth” ADC
B

of the AD1853 as measured by an Audio Precision System 2 used in the Audio Precision measurement system. The two-tone
Cascade. For the wideband plots, the noise floor shown in the test shown in Figure 18 is per the SMPTE standard for measur-
ing Intermodulation Distortion.
O

0.001 0

0.0008
–20
0.0006
–40
0.0004
ATTENUATION – dB

0.0002 –60
dB

0 –80

–0.0002
–100
–0.0004
–120
–0.0006
–140
–0.0008

–0.001 –160
0 2 4 6 8 10 12 14 16 18 20 0 50 100 150 200 250 300 350
FREQUENCY – kHz FREQUENCY – kHz

Figure 9. Passband Response 8× Mode, 48 kHz Sample Figure 10. Complete Response, 8× Mode, 48 kHz
Rate Sample Rate

–10– REV. A
 Typical Performance Characteristics–AD1853
0.5 0

0.4
–20
0.3
–40
0.2

0.1 –60
dB

dB
–80

–0.1
–100
–0.2
–120
–0.3

–0.4 –140

–0.5 –160
–10 5 10 15 20 25 30 35 40 0 50 100 150 200 250 300
FREQUENCY – kHz FREQUENCY – kHz

TE
Figure 11. 44 kHz Passband Response 4× Mode, 96 kHz Figure 14. Complete Response, 4× Mode, 96 kHz
Sample Rate Sample Rate

2.0 0

1.5 –20

1.0

0.5
LE dB
–40

–60
dB

0 –80

–0.5 –100

–1.0 –120
SO
–1.5 –140

–2.0 –160
0 10 20 30 40 50 60 70 80 0 50 100 150 200 250
FREQUENCY – kHz FREQUENCY – kHz

Figure 12. 88 kHz Passband Response 2× Mode, 192 kHz Figure 15. Complete Response, 2× Mode, 192 kHz
Sample Rate Sample Rate
B

–50 0

–10
–60
–20
O

–70 –30

–40
–80
–50
dBr

dB

–60
–90
–70
–100 –80

–90
–110
–100

–120 –110
10 100 1k 10k –120 –100 –80 –60 –40 –20 0
FREQUENCY – Hz dBFS

Figure 13. THD vs. Frequency Input @ –3 dBFS, SR 48 kHz Figure 16. THD + N Ratio vs. Amplitude Input 1 kHz,
SR 48 kHz, 24-Bit

REV. A –11–
AD1853
2 –90

0 –100

–2 –110

–4 –120
dBr

dBr
–6 –130

–8 –140

–10 –150

–12 –160
10 100 1k 10k 0 2 4 6 8 10 12 14 16 18 20 22
FREQUENCY – Hz FREQUENCY – kHz

TE
Figure 17. Normal De-Emphasis Frequency Response Figure 20. Noise Floor for Zero Input, SR 48 kHz,
Input @ –10 dBFS, SR 48 kHz SNR –117 dBFS A-Weighted

–10 0
–10
–30 –20

–50

–70
LE –30
–40
–50
–60
–70
dBr

dBr

–80
–90
–90
–100
–110
–110
SO
–120
–130 –130
–140
–150 –150
0 2 4 6 8 10 12 14 16 18 20 22 0 2 4 6 8 10 12 14 16 18 20 22
FREQUENCY – kHz FREQUENCY – kHz

Figure 18. SMPTE/DIN 4:1 IMD 60 Hz/7 kHz @ 0 dBFS Figure 21. Input 0 dBFS @ 1 kHz, BW 10 Hz to 22 kHz,
SR 48 kHz, THD+N 104 dBFS
B

0 –50

–60
–20
–70
O

–40 –80

–90
–60
–100
dBr

dBr

–80 –110

–120
–100 –130

–140
–120
–150
–140 –160
–140 –120 –100 –80 –60 –40 –20 0 0 2 4 6 8 10 12 14 16 18 20 22
dBFS FREQUENCY – kHz

Figure 19. Linearity vs. Amplitude Input 200 Hz, Figure 22. Dynamic Range for 1 kHz @ –60 dBFS,
SR 48 kHz, 24-Bit Word 116 dB, Triangular Dithered Input

–12– REV. A
 AD1853
–60 0
–10
–20
–30
–70 –40
–50
–60
–70
dBr

dBr
–80 –80
–90
–100
–110
–90 –120
–130
–140
–150
–100 –160
10 100 1k 10k 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80
FREQUENCY – Hz FREQUENCY – kHz

TE
Figure 23. Power Supply Rejection vs. Frequency Figure 26. Wideband Plot, 25 kHz Input, 2× Interpolation,
AVDD 5 V dc + 100 mV p-p ac SR 192 kHz

0 0
–10 –10
–20
–20
–30
–30
–40
–50
–60
LE –40
–50
–60
–70
dBr

dBr

–70 –80
–80 –90
–100
–90
–110
–100
–120
SO
–110 –130
–120 –140
–130 –150
–140 –160
20 40 60 80 100 120 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80
FREQUENCY – kHz FREQUENCY – kHz

Figure 24. Wideband Plot, 15 kHz Input, 8× Interpolation, Figure 27. Wideband Plot, 75 kHz Input, 2× Interpolation,
SR 48 kHz SR 192 kHz
B

0
–10
–20
–30
O

–40
–50
–60
dBr

–70
–80
–90
–100
–110
–120
–130
–140
20 40 60 80 100 120
FREQUENCY – kHz

Figure 25. Wideband Plot, 37 kHz Input, 4× Interpolation,

SR 96 kHz

REV. A –13–
AD1853
STEREO MODE OUTPUT FILTER

HDR2 DVDD
1
EXT SDATA HDR3 FN 1 2
EXT L/RCLK 44/48 0 0
DVDD DVDD
EXT SCLK 96 1 0
R17 R18 192 0 1
EXT MCLK 10k 10k NO 1 1
R24 R25 R26 R27 9 8
100 100 100 100 S2B IDPM0 S2C IDPM1 DVDD
EXT I/F 2 3
IN R12 R13 R14 R15 SAMPLE RATE
10k 10k 10k 10k R6 R5 MODE
C37 C35 C36 C34 10k 10k
47pF 47pF 47pF 47pF DVDD HDR3
C11
100nF
DVDD DVDD

U4 1 0
SPDIF/EXT R11 PALCE22V10-J U2 DATA SOURCE 1 S2A
10k SPDIF/EXT FB2
I/F
600Z I2S SERIAL S2B

TE
EXT MCLK 2
SELECT 10 C5 C6 CLK/I0
S2A DATA MODE 3 S2C
100nF 100nF EXT SCLK
1 I1 I /O9 DEEMPH OFF 4 S2D
EXT L/RCLK MUTE OFF 5 S2E
I2 I/O8
EXT SDATA
VA+ VD+ I3 I /O7
SDATA I4 I /O6 DVDD AVDD
SIGNAL FS
SOURCE FSYNC I5 I /O5
J1 64FS C9 C8
SPNIF 1 S1 C1 SCK I6 I /O4
10nF 100nF 100nF
IN 256FS
0 RXP MCK I7 I /O3
R1
75
C2
10nF
RXN
U2
CS8414-CS
M0
M1
M2

M3
LE I8
I9
I10
I11
I /O2
I/O1
I/O 0
DVDD AVDD
U5
AD1853JRS
INT4
INT2
OUTR+ ROUT+

SDATA OUTR– ROUT–

C R23
DS4 DVDD L/RCLK
500mVp-p U 274
BCLK LOUT+
SO
R19 OUTL+
CBL VERF
DVDD VREF 10k MCLK
Q1
VERF 2N2222
FB1 IDPM0
ERF OUTL– LOUT–
600Z MCLK IDPM1
C4 R2 C0/E0
100nF DEEMP VREF
3.40k FILTR
Ca/E1 U3A MUTE +2.7V
74HC00D CLATCH
Cb/E2 CLATCH
PREEMPH 1 CCLK IREF
Cc/F0 3
DVDD FILT 2 CCLK
CDATA FILTB
OUT Cd/F1 CDATA +
TOSLINK C26
U1 R4 DVDD ZR 10F
IN 1k Ce/F2 ZEROR –
TORX173 ZL
B

R3 SEL ZEROL C56

SHLD DGND 750 RST 100nF
CSI2/FCK RST FCR
C24 AGND DGND
DGND AGND R28
47nF 2.67k
DGND DGND AGND
O

FB3 SET Ib = 1mA

600Z
DVDD DVDD

C10
R16 R10 100nF
10k 10k DEEMPH U3D DS1
74HC00D
R20 ZERO
ON MUTE ZL 12
OFF 7 11 274 LEFT
S2D OFF 13
DEEMPH 4 ON 6 HDR1 DVDD DS2
S2E U3C
1 74HC00D ZERO
MUTE 5 R21 RIGHT
ZR 9
CDATA 8 274
10
CCLK
EXT C
I/F CLATCH
NOTE: DVDD
MCLK U3B DVDD
= DGND R7 R8 R9 74HC00D
R22 DS3 C12
10k 10k 10k 4 274 DEEMPH
= AGND 6 100nF
5
#98107-02-3 REV. 1.1

Figure 28. Digital Receiver, MUX and AD1853 DAC

–14– REV. A
 AD1853
R48
4.12k
OUTPUT BUFFERS AND LP FILTERS

C46 –AVSS
330pF, NP0 C23
100nF
R34 C38
R33 2.74k 220pF
ROUT+ R29
2.74k 2.94k NP0
C52*
NP U6A
OP275 C43
C57 680pF
C21 R41
220pF 100nF NP0 J2
NP0 604 1 RIGHT
U8B OUT
C50 0
+AVCC C42 R43
680pF OP275 2.2nF 49.9k
OP275 R35 R30 NP0
ROUT– NP0 2.94k
2.74k
C53*
NP U6B
C39
C47 R36 220pF
R52 330pF, NP0 2.74k
NP0

TE
402
VREF
+2.7V R49
4.12k R50
C7 + C25 4.12k GAUSSIAN FILTER RESPONSE
100nF – 10F –3dB CORNER FREQUENCY: 75kHz

C48 –AVEE
R53 330pF, NP0 C22
402 100nF
C40
R38
2.74k 220pF
LOUT+ R37 R31 NP0 –AV

C58
220pF
NP0
C54*
NP U7A
LE OP275
C20
100nF

+AVCC
2.74k

C45
680pF
NP0

C44
2.94k

U8A
SS
C18
100nF

C19
OP275
R42
604

C51
2.2nF
R44
1
J3

0
LEFT
OUT

R39 680pF R32 49.9k

LOUT– OP275 NP0 100nF NP0
2.74k 2.94k
C55*
NP U7B
SO
C49
R40 C41 +AVCC
330pF, NP0 220pF
2.74k
*NOT POPULATED NP0

R51
4.12k

RESET GENERATOR VOLTAGE REGULATORS AND SUPPLY FILTERING

DVDD J6
+15V dc +AVCC
U11 + C32
C17 FB4 ADP3303-5.0 – 10F
B

100nF 600Z
VCC IN OUT +5V REG
U10 CR2 AVDD
ADM707AR 1SMB15AT3 IN OUT
C16 R47
ERR NR 100nF 332
PFI RESET C15
100nF + C31
RESET RST SD GND DS5
O

+ C30 C3 – 10F
MR PFO J7 10nF POWER
– 10F AGND
S3 GND 0V
RESET AGND
+ C33
J8 – 10F
–15V dc –AVSS

U9
CR3 FB5 LM317
+9V dc J4 1N4001 600Z
+5V REG
TO VIN VOUT DVDD
+15V dc R45
GND
NOTE: C27 + 243
C14
CR1 10F – 100nF
= DGND + C29
1SMB15AT3 C13
100nF + C28 R46 – 10F
= AGND
J5 – 10F 715
0V
DGND DGND

Figure 29. DAC Output LP Filter, Power and Reset

REV. A –15–
AD1853

I/V CONVERTERS AND LP FILTER

R9*
2.87k
GAUSSIAN FILTER RESPONSE
C6 –3dB CORNER FREQUENCY: 75kHz
R11
68pF, NP0 100

C3503a–8–4/99
R4 C1
PIN 12 R3 2.74k 220pF
R1
LOUT+ 2.74k 2.94k NP0
U2
PIN 13
C4
LOUT– AD797 680pF
NP0 R7 J1
604 1 OUT
U1 6Vrms
C3
C5 R8 0
R5 680pF R2
AD797 2.2nF 49.9k
2.74k NP0 2.94k NP0
U3
PIN 17 C2

TE
ROUT+ AD797 R6 220pF
2.74k NP0
PIN 16 C7 R12
ROUT– 68pF, NP0 100
VREF
R10* NOTES:
+2.78V 2.87k
C8 + C15 1. R9, R10 MUST BE LOW NOISE TYPES.
10F METAL FILM IS RECOMMENDED.
100nF –
TANT 2. RIGHT CHANNEL DIGITAL DATA MUST BE INVERTED.

J2

NOTE:
= AGND
LE +AVCC

–AVSS
C10
100nF

C9
100nF
C12
100nF

C11
100nF
C14
100nF

C13
100nF
+ C16
–
10F
TANT

+ C17
–
10F
TANT
J3

J4
+16.5V dc

0V
AGND

–16.5V dc

Figure 30. Mono Application Circuit

SO

OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
B

28-Lead Shrink Small Outline Package (SSOP)

(RS-28)

0.407 (10.34)
O

0.397 (10.08)

28 15

0.311 (7.9) 0.212 (5.38)

PRINTED IN U.S.A.
0.301 (7.64) 0.205 (5.21)

1 14

0.078 (1.98) PIN 1 0.07 (1.79)

0.068 (1.73) 0.066 (1.67)

8° 0.03 (0.762)
0.008 (0.203) 0.0256 0.015 (0.38)
SEATING 0.009 (0.229)
0° 0.022 (0.558)
(0.65) 0.010 (0.25)
0.002 (0.050) BSC PLANE
0.005 (0.127)

–16– REV. A