Syniotic design systems

What is lumped matter discipline?
Define an ideal voltage sources?
What is power density?
Why can we ignore inductance of wires within
today’s chips?
What are the various types capacitances wires
exhibit in chips?
What is Elmore delay? Explain
The circuit parasitic of wire are distributed in
nature along its length and are not lumped into
single position .To make analysis simple we
represent different fractions into a single circuit
element .ex : R and C are total resistance and
capacitance of a wire for length L.
A voltage sources is defined as ideal when its
internal resistance is zero.it supplies constant
voltage irrespective of the amount of current
drawn.
It is power unit area
Because the wire lengths are very small in the
order of few microns and the frequencies are
not too high Ldi/dt is negligiable .Hence the
inductance effect can be ignored
1.Area capacitance ,this is capacitance from
length and width w.r.t to substrate or ground
.CA=E W.L/H.(E=Epsilon, material property,
L is length of wire ,W is width the wire ,H is
height from substrate)
2.Side wall capacitance or fringing capacitance
,it is the capacitance from from side walls to
the substarate.CF=2.E.L T/H
3.Coupling capacitance , CC=L.T/D. Where L
is length of overlap between adjacent wires ,T
is think ness of the wire and D is distance
between the wires .Coupling capacitance also
exists between orthogonal routing layers this
CC=e .W .L/H
Elmore has proposed an approx. way of
calculating delays on networks consisting of
resistors and capacitors. When there are
resistors and capacitors connected in a
network,if you want to find out the delay from
start point to a node in the network, you move
from this node to the start point and see what
resistances are charging what all capacitances
and sum all those time constants to find out
delay from start point to that node. Following
this, we can derive the delay of wire by
dividing the wire into small segments with
out loosing much of the accuracy .For a wire
length of L ,If r is the resistances of the wire
per unit length nad c is the capacitance per
unit length ,Elmore delay =rcL’2/2.if was
lumped mode the delay would have been

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What is velocity saturation?
What is Electro migration?
What is static discipline?
What is/are the sources of the noise within the
chip?
What is a glitch? How is it harmful?
Two important properties of MOSFET that
enable us to connect the gates one after another
W/o Worrying about whether the driven gate
causes any issue to the driving gate?
2’s compliment representation of a number is
100000. What is that number?
Define threshold voltage of a MOSFET?
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RC=r.L,C=c.L.
In short channel MOS transistors, as VDS
increase for a particular VGS, The velocity of
the majority
Carriers reaches a saturation point(due to
scattering effects etc..)even before
VDS>=VGS-VT Point .So the current stays
constant from that point onwards .This is called
velocity saturation.
The current density(current per unit area) in a
metal wire is limited due to an effect called
Electro migration. A direct current in a metal
wire that is more than the current carrying
capacity of the wire running over a substantial
time period causes transport of the metal ions.
Eventually this causes the wire to break or
short to another wire. To avoid this effect
current density of a wire is kept under limits
usually power wires will tend to be effected by
electro migration the reason is current flows
always in the same direction. Usually signal
wires will not get affected by electro migration
because they carry currents in both
directions(one direction for charging of
capacitances and the opposite direction for
discharging of capacitance)
This is a specification for digital circuits.it says
for valid inputs valid outputs must be
generated.
Switching noise (x talk noise).Thermal noise
,power supply noise, noise due to inductances
effect Ltd/dt on`i/o signals and IR drops
noise .All these will impact the over all delays
in the circuit.
It is momentary output changes when no
output changes should occur . the response to
the glitch depends on glitch amplitude and
glitch width.
Gate terminals are isolated from the output
The current drawn by the gate terminals iss
almost zero
It is minus 32
It is defined as the minimum gate source
voltage at which the channel is completely
 Syniotic design systems
How do u bult the 2 i/p NOR gate using
PMOStransistor
Advantages of CMOS logic family over
NMOS only or PMOS –only logic family?
What is Dynamic Power consumption ?
What is Leakage Power consumption
What is short circuit power consumption
How do the transition time of nets/signals
affect the short circuit power consumption
What are rise and fall delay of NMOS inverter,
RON is ON resistance of NMOS and RL is the
load resistance of NMOS and RL is the load
resistance and driving a capacitance of CL?
On what factor Cell delay depends on and
how?
What is the Timing Arc ? how many types of
arc does a 2 i/p Mux have
Can you make (worst case) rise delay and fall
delay of 2-i/p NAND gate exactly equal to
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inverted.for a N channel MOSFET number of
electron in the channel is just to the no of
acceptor
It is connecting two PMOS transistor in series
through a series resistor from drain terminal to
ground . O/P is taken from the drain terminal
of the bottom CMOS transistor.
Negligible Static power
O/P will get Rail to Rail swing
When high it is VDD, When low it is equal to
ground hence provides more Noise margin O/P
is connected to VDD and Ground through low
impedance path
Power consumed during Switching of the input
signal
It is the power consumed when the input are
static
It is power consumed when the both CMOS
and NMOS are ON. This happen during input
transistor .if input transitions slowly more short
circuit Power
More transition time would cause the more
short circuit power .Because of more transition
time would make Both CMOS and NMOS are
ON simultaneously there going to exist direct
low impedance paths from VDD to VSS
Tr= 0.69RLCL TF=0.69RonCL (This is the
time difference from 50% of inputs signal
transistor to 50% of the Output signal transistor
)
Input transistor Time and Output Load
Capacitance
PVT conditions
The delay of the cell depends upon input
transition time longer the input transition more
the delay
If an input change cause an output change then
there exists a timing Arc from the input to the
output .Every timing arc is associated with
Two delays i:e rise delay and fall delay . Mux
has A-Y,B-Y, Sel-Y rise and Fall arc total 6
timing arc it has
It is not possible to make rise and fall delays of
2 i/p NAND gate exactly same. Because the
 Syniotic design systems
each other? If u can how? If u can’t,Why?
Why do the circuits having EX-OR gate
consume more power ?
Why don’t we see 8 i/p or 10 i/p NAND or
NOR gates in std cell library
Which among NMOS inverter and NMOS
buffer consume more static power and why?
How static Power in CMOS logic is almost
eliminated?
How can u eliminate the short circuit power
in CMOS logic gates
In CMOS inverter ,what kind of relationship
between Vtn, Vtp and VDD would eliminate
the short circuit power consumption?
Define propagation delay of a cell
How do you define the transition time of net
What is combinational Loop
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internal capacitance of the nodes are different
when the output is rising vs O/P is falling
Always the XOR Output switching probability
is ¼ irrespective of number of inputs
In the 8 i/p gate previous stage delay increases
because of more input pin capacitance Hence it
preferred to implement 8 i/p gate with 2 i/p
gate of multiple stages
NMOS buffer consume more Static Power.
NMOS buffer will have two Inverter inside
these two inverter will consume power one in
one cycle and the other I another cycle.
Whereas inverter will consumes power only
when the inputs is low
When the inputs are stable the o/p is connected
to VDD or VSS .there will be no direct path
from VDD to VSS .Hence the Static power is
almost zero
By having the sharp transition at input
By having more vtn and vtp Vtn +vtp>VDD
that makes the CMOS becomes on a later point
of time compared to lower value of vtn and vtp
.thus the duration of both NMOS and PMOS
ON simultaneously very less that eliminates
the short circuit power .suppose if Vtn is 4v
and vtp 4v NMOS is ON for 4 to 5v onwards
and PMOS is ON from 0 to 1v .Both PMOS
and NMOS together will be never ON hence
no short circuit power
It is measured the difference between 50% of
input transition time to 50% of output
transition time
It is the time difference 20-80% of transition
time when rising 80 – 20% when falling of a
signal on that net
When the output of the combinational gate is
connected to its input directly or indirectly . it
is said to be a combinational loop. There are
controllable combination loop and
uncontrollable combinational loop .for
example % inverter connected back to back is a
 Syniotic design systems
What is multi-driven net ?
What is tri-state logic
When 2 i/p CMOS NAND gate and NOR gate
transistor are sized in such a way that their rise
and fall delay more/less match with those
standard CMOS inverter which among NAND
or NOR will cause more delay to the circuit
practically?
What is static hazard
What is overshoot and undershoot
How many timing arc are present in
transparent latch has
How do u define setup and hold time of a latch
How do u define setup and hold time of a edge
triggered flop
What is synchronous sequential circuit ? What
is fully synchronous sequential circuit
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uncontrolabale loop .if the output of a NAND
gate is connected to its input is .it is equivalent
to stuck at 0
When a net is driven from more than one
source .it is said to multi driven net
It does not have low impedance path either to
VDD or VSDS .it doesn’t have logical voltage
significant. It is logically disconnected from
driving node.
NOR gate Because of NOR gate TWO PMOS
are in series whose width are 4w and 4w. hence
more internal capacitance and more delay
It is the unwanted change on the combinational
circuit o/p . to remain logic high state
momentarily .if the output goes to zero state
then it is said to be static 1 hazard vice versa
for static hazard 0
If the signal voltage level value goes above the
VDD value it is called overshoot and below
the GND level it said to be undershoot .one
reason this can happen is due to crosstalk noise
A latch has two timing arcs D to Q and clk to
Q every timing arc has two delays rise cdelay
and fall delay
Setup time: it is the time the stable valid data
to be present at the data input of the latch
before the closing edge of the latch
Hold Timing: it is the time the valid data to be
held at the data input pin of the latch after
closing edge of the latch
Setup time: it is the time the stable valid data
to be present at the data input of the latch
before the closing edge occur (clock
transiistion)
Hold Timing: it is the time the valid data to be
held at the data input pin of the latch after
closing edge occur (clock transistion)
Fully synchronous sequential circuit:
All the sequential elements are clocked by the
 Syniotic design systems
When do u call two clocks synchronous and
asynchronous circuit
Define Synchronous reset and asynchronous
reset
What is recovery and Removal times?
What is a timing path?
How do u define a single cycle behavior of a
sequential circuit ?
What are the two hold mantras
How do u define max and min path
How setup time requirement on D-pin wrt to
CK pin of the flop dependents on transition
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same clock
When the clock is generated by the same
source and their phase relationship is known is
called sequential circuit
The clock are called synchronous when their
sources are same and phase relationship is
fixed and known as synchronous
Asynchronous clocks: if the phase relationship
cannot be established or cannot be predicated
those clock are said to be Asynchronous clocks
Reset that works on the clock transition is
called Synchronous Reset .
Reset that does not depend on the clock
transition is called asynchronous Reset
Recovery and Removal check are done for
Asynchronous set and reset signals of a
sequential elements
Recovery time : it is the minimum time
required for deasseration of asynchronous
set/Reset signals before clock edges occurs
Removal: it is the minimum time required for
deasseration of asynchronous set/Reset signals
before clock edges occurs
Timing path have start point and endpoint .
start point of a timing path could be either
clock pin of a sequential element or a latch or
memory or block input port of a chip
.Endpoint of a timing path could be a non clock
input pin of sequential element or latch or
memory
In a single cycle behavior dat a launched by the
launch in current clock edge should be
captured by the capture flop in next clock edge
The data launched by the launched flop should
not captured by previous capture edge
The data launched by the launched flop should
not be captured in next clock edge
A timing path has multiple paths constitute
different delays . out of these multiple path
delays The path which exhibits highest delay is
called max
The path which exhibits least delay is called
min
When data transition time increases by
assuming clock transition time is fixed the
 Syniotic design systems
time of D and CK
How Hold time requirement on D-pin wrt to
CK pin of the flop dependents on transition
time of D and CK
What is cycle-to-cycle jitter
How does jitter will impact setup and hold
timing
What is skew how does it impact the setup and
hold timing
Why is hold violation seen on the chip after
manufactured fatal
How do the cell delays vary with process
voltage and temperature
What are PVT corners
How do setup and hold time vary with PVT
What is temperature inversion
What is IR drop
What happens to the chip functionality if IR
drop exceeds the target limit
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setup time requirement is increased
When data transition time fixed by assuming
clock transition time is increase the setup time
requirement is decreased
When data transition time increases by
assuming clock transition time is fixed the
Hold time requirement is decreased
When data transition time fixed by assuming
clock transition time is increase the Hold time
requirement is increase
The variations of occurrence of clock edge is
called jitter
PLL jitter will degrades setup timing it does
not affect hold timing
It is the difference in arrival time of two
talking flops .it effects either setup or hold .it
effects setup timing when launch clock edges
arrives before the capture clock edge and on
the other way for the hold timing
Because the chip can’t be usable in any way
otherwise there is no work around to overcome
the HOLD timing issues
Delay is more for slow process low voltage and
high temperature and Delay is less for fast
process and voltage is high and temperature is
low in lower technology nodes delay is
increased when temperature is low i:e
temperature inversion
Slow corner : more delay low voltage high
temperature
fast corner: less delay high voltage low
temperature
Typical corner: typical delay typical voltage
typical temperature
Slow corner : setup worst
fast corner : Hold worst
For 65 nm and below node cells delays will
reduce with temperature hence for these nodes
slow LT is the slow corner
It is the voltage drop because of the current
drawn by Std cell from Power supply . it
should be within the allowable range so that
the chip function properly
Cell delays will increase
Noise margins will reduce because of reduce in
 Syniotic design systems
voltage level
If IR drop exceeds the limit the chip
functionality is not guaranteed
What is logic synthesis It is process by which the RTL code is
converted to gate level for the target
technology by meeting ATP goals
What are the inputs required to perform logic RTL code
synthesis .libs
SDC constraints
What is PLE based synthesis Physical layout estimate this is called physical
synthesis for timing critical design PLE based
synthesis is used
What is zero wire load model synthesis ?how When this synthesis is started wire delays are
much margin you will shoot for this in this not known and hence optimization is not
case and why ? effective .To model wire delay PLL jitter
OCV impacts clock skew and xtalks .put
together usually we try to grt around 20%
margin .Total of 15% for wire delay and 5%
for all the impacts mentioned
What is custom wire load model synthesis The wire load derived based on design
specification are called custom wire loads
What sdc command you use to define derived Create_generate _clock command
clocks in your design
What is clock gating How it reduce dynamic Clock gating is switching off clock to those
power consumption flops where the D is input enable through a
control signal hence dynamic power
consumption is reduced (Sequential elements )
What is operand isolation how dynamic power By operand isolation dynamic power
consumption reduced consumption by combinational logic can be
reduced .By operand isolation unnecessary
switching of the signal to the logic blocks like
adders is minimized without implicit
functionality for example
Why implementing clock gating for one flop To implement clock gating an ICG cell is used
may not reduce the dynamic power ICG cell drives the clock input of flops ICG
consumption but in fact it increase cell consist of active low latch and followed by
an AND gate ICG cell has a load of 2 on clock
suppose if gating is implementing for a single
flop now overall load on the clock is
Hence it is optimum to use clock gating for 3or
more flops depending on technology
What are DRV constraints? Why do we have to Transition time capacitance and Fan-out are
meet them DRV constraints violating DRV’s transition
and capacitance he delays of the cell cannot be
trusted ,timing cannot be trusted and finally
chip functionality is affected .Because cell are

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 Syniotic design systems
What are interpolation and extrapolation
techniques that tools use for calculating the
delays
Why are extrapolation delays are inaccurate ?
what harm does inaccurate delays cause
What is net list unification why we need to do
before PNR
What are tie high and tie low cells why we use Tie high and tie low are used for pull up and
them
What harm can floating inputs pin on cell
cause
Can output of gate can be floating?
How are cell delays going to changes if u
increase the size of transistor
Why don’t we normally use low driver strength Xtalks impacts is relatively more in highly
cell in a timing critical highly utilized design s utilized design because cells are placed close to
What is utilizations
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characterized for a range of transition times
and capacitance value
Std vendor characterize the cells for a certain
range of transition and capacitance limits
Beyond and below those value of transition
and capacitance value the cell delays are not
trusted so std vendor provides a lookup tables
for a range of transition and capacitance values
something like 5x5,7x7
extrapolation delays is done for transition and
capacitance outside the characterized limits if
these values are beyond the characterized
limits actual cell delays will be more than the
calculated values hence is setup is optimistic
and Hold is pessimistic for the lower limit
actual values will be less than calculated values
here Hold is optimistic and setup is pessimistic
Net list unification is creating the number of
Verilog modules equal to number of instance
in PNR phase during optimation happens based
on instance placements location and port
location on the boundary.
pull down the inputs of the std cells because
the std input pin should not be connected
directly to the power pin because of static
discharge the gate gets damaged
It might pick the value of the noise margin to
the metastable state that can cause huge short
circuit current.
The o/p can go to metastable state.
Yes it can be floating it will not cause any
harm because it is not connecting.
Cell delays would get reduced because on
resistance of the transistor get decreased on
resistance of the transistor is inversely
proportional to their widths
each other
Not only that low driver strength cells get
impacted more by xtalk because they are
weekly driven. There o/p transition time is
more
Core utilizations: it is the total area including
standard cells macros memories
 Syniotic design systems
How do u define gate count and placeble
instances how these are usually related
What is area reclamations
Explain five delay optimizing techniques
Explain floor plan guidelines
Why successive metal layer are orthogonal to
each other
How do you calculate core power/gnd pads
and arrange the around the io ring
What is simultanesoly switching output
analysis
What is ground bounce
Why are top layer are used for PG planning
What are bond pad and bond wires
What is trail Route in SOC How it is usefull
What kind of trail Route congestion is green
signal for Routing
What value is used for set_max_transition in
sdc
List atleast 10 constraints in sdc
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standard cells utilizations: utilization of
standard cells exclude macros and memories
generally we aim for standard cells utilizations.
Gate count is defined as 3 to 5 times of
palceable instances or total area of placeable
instance /min area of 2 input Nand gate
Optimizing area without affecting timing
Upsizing Downsizing buffer inseration and
removal removing inverter pair pin swapping
Logic restricting
Cloning
Placing macros around the periphery of the
chip
Macro orientation should be towards the core
Between macros space should be left for
macros pins routing
PLL should be close to the clock port
To minimum the coupling capacitance
To increase rout ability
Depending upon the power consumed by the
chip we calculate the total current and decide
the number of pads .depending on which area
the of the chip consumes more power
SSO analysis is done for finding out the I/O
power requirements. From I/O power
calculation we figure out the number of pads to
be used and placed
It is the ground voltage going above the zero
level
This happens because of IR drop in ground
path
Top layer thickness is more hence resistance is
less in other words the number of stripes to be
used for limiting the IR drop is minimized
Bond pad are just metal pecie to enable the
connectivity from the chip package pin and the
I/O pads Bond wires is used to connect
package pin to bond pad
Trail route is quick and dirty routing .it may
not look for 100% RC clean .it is almost close
to final routing to get an idea about congestion
0.2 %to 0.3% routing congestion the design is
routable
70% of characterized
Create_clock create_generate_clock
 Syniotic design systems
set_input_delay set_output_delay
_set_max_delay set_min_delay
set_multicyclepath set_max_transition
set_max_fanout set_false_path
set_disable_timing set_clock_uncertinity
set_clock_latency
What is false path A path do not required to analyses timing
What is multicycle path A path by design take more than one clock
ccle is called multicycle path
What are Gcell Global cells entire routing area is divided into
small area called G-cell it consist of horizontal
and vertical tracks .tool will plan routing by
using the Horizontal and vertical tracks
What is manufacturing grid and what are Minimum manufacture able length of the metal
routing tracks Routing tracks are the imaginary lines that tool
would divide the whole routing area .Tools will
use this tracks as a reference for routing
How are standard cells height and width are Std cell width is integral multiple of metal to
decided pitch and height is integral multiple of metal
one pitch
What is latch up? It is distractive phenomenon which occurs
when a parasitic turns On
What are tap cells Tap cells are used to prevent the latch up there
are tapped library and tap less library .
What is clock tree synthesis what is its Clock is very high fan-out net . CTS tool will
objective buffer the clock net by meeting the CTS
objective
Min insertion delay
Min skew
Min leaf and non-leaf net transition
Min types of CTS buffer
Min dynamic power consumption
Why do u want to minimize the clock insertion To minimize OCV
delay To minimize the dynamic power
To reduced buffer count and area
What is useful skew and triggered skew Skew would help either for setup or hold
depending on the relative arrival times of
launch and capture edges in scenario where
path is very critical if it cannot be fixed by
standard method violations is fixed by
introducing the skew
Triggered : difference betwn rise clock edge
insertion delay and fall clock edge insertion
delay
What % of dynamic power is consumed by It is 30 to 40% by using clock gating
Clock tree how do u plan to reduce the By placing ICG near to the clock port

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 Syniotic design systems
power ?
What is an ICG cell
What is ideal placement for ICG cell in layout
in power and timing point of view
What is cell padding
What are the guide lines you follow to reduce
congestion
What do u understand by global and detail
routing
What is SMART routing
What are double cut vias y do u insert them
What are non-default rules where do u use
them
State at least two important uses of macro
modeling
What kind of transition time you target ton
achieve on non-leaf and leaf clock nets
Explain through pin and leaf pin concepts
Exclude pin and preserve pin concepts
What is scan chain reordering
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By reducing clock insertion delay
By having sharper clock transition
It is an integrated clock gater cell .it is used to
gate the clock signal where ever possible
.gating the clock gating using icg cell prevents
clipped and spurious clocks own the gate
output
Power point of view closer to the clock port
and timing point of view closer to the logic
For the cell that having more number of pins
to enable connections some room is to be
provided near those cells
Routing congestion can be reduced by
following floor plan guidelines
Global means planning and detail means real
routing without any DRC’s
Signal integrity and manufacture aware timing
driven routing
A via that is manufactured with two cuts is
called double cut via by using this
manufacturing yield will increase
A file that creates with no default rules like
width of the wire more that min width and
spacing btw the wire more than min spacing.
This file is usually used for clock routing
To create useful skew
It depends upon the technology node and the
clock frequency usually it is around 5 to 10%
of clock period
Through pin : defining default leaf pin as non-
leaf pin
Leaf pin : defining as non-leaf pin as leaf pin
Exclude pin is used to exclude some part from
CTS.if timing is not required to analyse from
the flop to processor and vise versa exclude pin
option for the processor clock pin can be used
Preserve pin would automatically compute the
clock path delay from that pin onwards
Usually scan chain stiched before PNR
steps .while inserting scain chain the function
timming is not considered .in PNR it is time
drivern placement that means talking flops is
paced together .while doing it so necessary
scain chain connectivity optimize to reduce
routing length on scan chains
 Syniotic design systems
How do u take care bogus in-to-reg and reg-to-
out timing slack after clocktree synthesis
What are cap tables what do they contain
What are tech.lef and stdcell.lef ? what do they
contain
What do timing library contains
What are qrc tech files
What is cock uncertainity state it uses
Why do u want to close hold timing with
certain margin
What is crosstalk
How does the cross talk tool filter non-
harmfull glitches
What are aggressor and victim nets define
virtual attacker
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By editing input output delays
Use set clock latency to clock inseration delay
and constrains all the input and output ports
wrt clock latency
Cap tables contains resistance and capacitance
of nets .there are two types of cap table normal
and advanced cap tables just captable contains
resistance and capacitance wrt width and
length and advanced cap table contains 3
dimensional capacitance and resistance
Tech.lef: it contains metal layer information
min space min width pitch information routing
direction via information and dimensions
thickness of metal information
Std cell.lef: Height and width of a cell, pin
coordinates obstruction information etc.
Cell footprints power numbers (leakage and
ststic power )cell delays transition and
capacitance values and cell functionality.
It is the file used to extrct sign off quality spef
form cadence QRC tool .it is used for final
extraction becuasse it is more accurate and
takes more time for extraction .they contain the
resistance and capacitance per unit dimensions
for each metal layer .they also contains inter-
meta-dielectric thickness information
Diff in clock edge arrival timing btw the
talking flops is tremed as skew usually for pre
layout design we use set_clock uncertainity in
sdc to model the effect of clokskew jitter xtalk
and ocv and wire delay effects
Hold violation are fatal in if we see any hold
violation after chip manufacturing simply chip
should be thrown out .hence to be on safer side
we close the hold with more margin
It is unwanted change occur on a particular net
because of switching the adjacent net . this
impact of xtalk is delay of the net that can be
effected by xtalk can be increased or decreased
momentarily input can be change the
functionality of the circuit
It uses cdb files .it filters non harmful glitches
from cell delays and static discipline values
that cdb file contains
When a net is switching it can impact the
adjacent nets electrical characteristic this is
 Syniotic design systems
What is incremental sdf
What are cdf file what does it contains
What is follow pin
What do u understand by filliped row what is
the advantages
What are parasitic corners
What is OCV why do we need to consider it
What is the typical OCV derating used for
65nm for setup and hold
What do I/O pads normally contains
What is multi VDD design
What is multi-VT flow how does it helps to
reduce leakage power
What is substrate biasing technique what
benefit does it provides
What are RC scaling factors how they are
useful
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called aggressor net and the impacted net is
called victim when multiple nets switching like
data nets individual nets xtalk impact is very
small but cumulative effect by combining the
effect of all nets could be considerable .
combining the xtalk effect of small attackers in
to a single net is called virtual attacker
Sdf file generated from xtalk analysis tool .it
contains rise delay increased fall delay
decreased and rise delay decreased and fall
delay decreased values
Cdb files are used by crosstalk analysis .this
contains static displine information and noise
margin
A follow connects VDD and VSS pins of aall
standard cells to power mesh
Standard cell are palced in rows the orientation
of the standard cell is flipped across the rows
to share VDD and GND follow pin of adjacent
rows to Save area
Cworst Cbest RCworst RCbest
Ocv is vartion in operation condition across the
cells when the chip is in operation OCV will
impact
5%for setup and 10% hold
Level shifter
ESD protection mechanism
signal buffer
The chip contains multiple voltage segments to
reduce the power consumption usually timing
critical part is operated at high voltages
compared to non timing critical part of the
design
Multi is used in the design to reduce the
leakage power std vendor will provide multiple
vt flavors of cells rvt lvt hvt . rvt and lvt has
less delay compared to hvt . hvt cells leakage
power is less
By substrate biasing technique the substrate is
tried to some voltages not to gnd for an nmos
and vdd to pmos .this reduces channel sub
threshold leakages
To correlate the delays bwt PNR tools and sign
off tools we use scaling factors by using
scaling factors correlation difference are
 Syniotic design systems
What is a synchronizer circuit
What is metastability
What factor MTBF depends
What do u understand by logically exclusive
clocks
In d flip-flops implementation as a master-
slave structure the setup /hold time
requirements of the flops setup/hold time
requirement of which latches
Can upsizing of the cell Eli mates max cap
explain
What are spare cells
What is metal density ? what are dummy metal
fills
What are dishing and erosion
What is process atenna affect ? tecniques to
elimate
What is antenna ratio
What is ESD
Interview question
www.syniotic.com
included in advanced in PNR tools so that in
sign off tools the timing and RC values almost
match with final sign off quality
When asignal cross clock domain and the clock
are asynchronous a synchronizer circuit is
used to clean the signal that passes through
metastable state
When input of the flop changes in the setup
/hold window of a flop can go through meta
stable state .when the flop is in meta stable
state the output cannot be predicted
Gain of the feedback loop of the flop
Setup and hold time requirements of the flops
Frequency of operation
Frequency of occurrence of source signal
Clocks that never gets enabled simultaneously
Master latch
No because max capacitance values
characterized in the library mostly same for all
the cells to fix max cap violations a buffer
should be inserted which drivers high cap
Extra cells placed in the chip and these cells
are used to fix functional bugs after chip is
fabricated .these fix are done by metal only
tape out without touching the base
To have uniform impact on metal because of
CMP polishing foundry rules suggest
minimum and maximum metal density per unit
area
While doing the cmp the reduction in thickness
is called dishing and erosion .Dishing is
reduction at the centre and erosion reduction of
thicknes at the sides
The charge accumulated on the metal wire
discharges through gate oxide while doing
CMP process is called antenna affect
Layer hopping and inserting antenna diode
It is ratio of area of metal to area of the gate
It is static charge that get discharged when the
human body touch chip pin hence in every I/O
signal Pad ESD protection mechanism is
provided
 Syniotic design systems
What are pad limiting and core limiting
designs
What kind of impact does the dummy metal
have on timing
What are manufacturing DRC ‘s
How do u run block level LVS
What is via array what is stack via
What do u understand by metal only tapeout
What are all the cell/instance whose status is
fixed in cts stage
What is the main usage of PLL on the chip
What are the audits that u perform before PNR
What is bus hold cell
What is pin swapping optimization technique
What is formal verification
Interview question
www.syniotic.com
I/O pads dedicates the DIE dimensions
Core limited designs core logic dedicates Die
size
Setup timing degrades because of increase in
net capacitance and hold timing improves
Min width min spacing via encoluser min area
of metal antenna latch up metal density rules
etc
Dump transistor level gatelevel netlist extrct
transistor level physical data base feed the
transistor level netlist and GDS along with
LVS extraction
One or more via used to connect the wider
metal is called via array.
Stack via : the via which is used to connect
from the top layer to the bottom layer
Without touching the base and respininng the
metal if changes need
Flops ICG clock buffers and inverters
High frequency should be generated from the
PLL on chip this prevent the clk disturbances
from external noise
Check design : it verifies multidriven inputs
floating inputs and output ports constant driven
flops tri-state buses assign statements unloaded
flops combinational loops
Check timing : it verifies timing loops input
delays output delays missing clock definition
Tri state logic share more number of o/p to
common bus and enable one o/p at a time
suppose the bus is not driven by any of the o/p
bus would be logically floating and equivalent
to a floating node to address this issues tri state
bus are driven by bus hold keeper cell .it drive
the bus with last driven logical value
The delay of the cell is not same from different
input to output cell delay is less from the input
that connected to NMOS transistor that is close
to its output PNR tool will interchange the
timing critical signal from more delay inputs to
less delay inputs
It is a logic equivalency check it make sure that
logic value will not change during optimization
.this is done during synthesis formality check is
verified with input net list and output net list.
 Syniotic design systems
What is the diff btw clock inverter and buffer
compared with normal inverter and buffers
Does duty cycle distortion on clock caused by
clock tree affect timing in a design
What are set don’t touch and set don’t use
commands
What are the sign –off check to be performed
before tape out
Interview question
www.syniotic.com
For clock inverter and buffers the rise and fall
are almost same. These helps in retaining
original inputs clock duty cycle
Duty cycle distortion doen’t affect timing as
long as both talking flops use same clock edges
Set_dont touch by this constraints optimization
shouldn’t happen to the logic or block that
constraints is applied
Set_dont _use :usually we use this to not use
few cells In the design while optimization
DRC LVS Timing IR drop usually following
things are reviewed manually before tape out .
net list version SDC constraints formalities
results all log files lib and lef version