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Published in IET Microwaves, Antennas & Propagation
Received on 20th June 2011
Revised on 4th September 2011
doi: 10.1049/iet-map.2011.0201

ISSN 1751-8725

Optimum design of a novel N-way planar power

divider/combiner with impedance matching
H. Oraizi S.A. Ayati
Iran University of Science and Technology, Narmak, Tehran, Iran
E-mail: h_oraizi@iust.ac.ir

Abstract: A novel N-way planar power divider/combiner with arbitrary power division/combination ratios incorporating
impedance matching among the ports is introduced, which is configured as the combination of Wilkinson and Bagley power
dividers and possesses the advantages of both structures and avoids their shortcomings. This device performs as a single-layer
planar Bagley power divider, which divides the input power among an arbitrary number of output ports and vice versa. It also
acts as a Wilkinson power divider, which provides impedance matching among its input/output ports and exhibits high
isolation among its output ports. The bandwidth of the proposed divider is much broader than that of the simple Wilkinson
power divider. An equivalent circuit model is derived for the proposed N-section divider – combiner configuration, which is
used for its design. Two prototype models are designed, fabricated and measured for the verification of the method.

1 Introduction In this paper, we show that the combination of Wilkinson

Power dividers and combiners have various applications in
microwave circuits and antenna array feed networks. The
return loss at the input port and the power division ratios at
the output ports are basic parameters of the power dividers,
whereas the return losses at the input ports and also the
isolation among them are crucial parameters for power
combiners. However, the common power dividers and
combiners, such as the Wilkinson [1] and Gysel [2]
dividers, possess some advantages as well as some
shortcomings, in their design frequency band. The return
losses at the input ports of dividers and combiners, and the
isolation among the combiner input ports are quite high.
However, the bandwidth of single-section dividers and
combiners are relatively narrow. Their wideband
performance may be obtained by cascading several sections
of them [3, 4]. On the other hand, the number of output
ports of the single-layer planar microstrip configurations of
such dividers is quite limited. They should be made in
multilayer structures. Such restrictions make the high-
frequency design of such devices with arbitrary number of
outputs very unwieldy.
An input power may be divided among several output ports
by the Bagley power divider [5], which may be realised by a
single-layer microstrip structure. Its input port return loss is
quite high and its bandwidth is better than that of the
Wilkinson and Gysel power dividers [6]. Its bandwidth can
be further increased by designing the characteristic
impedances (and widths) of its various microstrip line
sections [7]. However, the Bagley configuration may not be
used for power combiner functions, because its input port
isolations and return losses are not high.
and Bagley power dividers produce favourable results by
preserving the advantages of each configuration while
avoiding their shortcomings. The number of output ports of
the proposed divider may be arbitrarily selected and it may
be designed on a single-layer planar microstrip circuit. In
the case of power division, the return loss at the input port
is quite high and the input power may be arbitrarily divided
among the output ports. The bandwidth of proposed divider
is wider than that of the Wilkinson power divider. In the
case of power combining, the input port isolations and
return losses are quite high.
The operation of the proposed divider is similar to that of
the Bagley power divider, where the input power is divided
between two paths, from which the output powers are
branched out [8]. For the implementation of impedance
matching at the output ports and required isolation among
them, a Wilkinson power divider is also incorporated at its
output end. A strictly analytical method may not be applied
to it because of its complicated configuration.
Consequently, the following noteworthy points are
presented in this paper:
1. Presentation of a novel N-way planar power divider/
combiner as the combination of Bagley and Wilkinson
power dividers.
2. Derivation of an equivalent circuit for the proposed power
divider/combiner structure.
3. Development of an optimum design procedure.
4. Fabrication and measurement of its prototype models for
the verification of proposed device configuration and its
design procedure.

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2 Theory and analysis
The proposed power divider (or combiner) with three output
ports is shown in Fig. 1. Its equivalent circuit is shown in
Fig. 2, which is composed of microstrip line sections, chip
resistors, 908 bends, T junctions, and cross junctions [9].
The power divider configuration may divide the input
power into an even or odd number of output ports. For the
case of an odd number of output ports, two paths are
connected at their ends, as shown in Fig. 2.
For the simplicity of circuit analysis, we separate the output
port 4 into 4′ and 5′ and combine each line section series
admittances, as shown in Fig. 3. This 5-port network is
actually divided into a 3-port and a 6-port network as
shown in Fig. 3. In Fig. 3, the input port of each block is Fig. 1 Design parameters for the configuration of the 3-output
designated by an arrow. The directions of currents at the port power divider

Fig. 2 Equivalent circuit for the proposed 3-output ports power divider (combiner)

Fig. 3 Equivalent admittance matrices for the 3- or 4-output port power divider (combiner)

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input and output ports are adapted according to the accepted place of [T (1) (2) (3) (4)
H ], [T H ], [T H ] and [T H ] in (3), respectively.
convention for admittance and transmission matrix Now, the transmission matrix [T V ]8×8 in Fig. 3 is
characterisation of networks. The admittance matrix of the obtained as (see (4))
3-port network may be obtained as
where [U ] is the unity matrix, [0] is the zero matrix, and
⎡ ⎤ y(l)
V ,ij is the entry of ith row and jth column of the
y(1) (2)
H,11 + yH,11 y(1) y(2) admittance matrix [Y (l) V ]. Equation (4) is used to compute
H,21 H,21
⎢ ⎥
[Y R ]3×3 =⎢
⎣ y(1)
H,12 y(1)
H,22 0 ⎥
⎦ (1) [T V ](1) in Fig. 3 by the substitution of matrices [0]2×2 ,
y(2) 0 y(2) [Y (l)
V ]2×2 in Fig. 3 and [0]2×2 in place of [Y V ]2×2 ,
(1)
H,12 H,22 (2) (3)
[Y V ]2×2 and [Y V ]2×2 , in (4), respectively. Equation (4) is
also used to compute [T V ](3) in Fig. 3 by the substitution
where y(1) (2)
H,ij and yH,ij are the entries of admittance matrices
of matrices [Y (2) (3) (4)
V ]2×2 , [Y V ]2×2 and [Y V ]2×2 in Fig. 3 in
[Y (1) (2)
H ]2×2 and [Y H ]2×2 , respectively. We now obtain the place of [Y (1) (2)
V ]2×2 , [Y V ]2×2 and [Y (3)
V ]2×2 in (2),
admittance matrix of the 6-port network [Y S ]6×6 (in
Fig. 3), which is made into an 8-port network, as shown respectively. The resultant 8 × 8 order-transmission matrix
in Fig. 3. We first obtain the transmission matrices of the of the circuit in Fig. 3 may be obtained as
horizontal ([TH]) and vertical ([TV]) circuit blocks as
shown in Fig. 3 [T]8×8 = [T V ](1) (2) (3) (4)
8×8 ∗ [T H ]8×8 ∗ [T V ]8×8 ∗ [T H ]8×8 (5)

Its equivalent admittance matrix [Y ]8×8 of the 8-port

network may be obtained from its transmission matrix
[T]8×8 . Now, the 6-port network in Fig. 3 (denoted by
where (see (3)) [Y S ]6×6 ) may be obtained from the 8-port network in
Fig. 3, by connecting together the ports. Consequently, the
(l) admittance matrix of resultant 6-port network may be
where tH,ij is the entry of ith row and jth column of the
transmission matrix [T (l) derived as Eq. (6) where yij is the entry of the ith row and
H ] as shown in Fig. 3. Equation (2)
jth column of the admittance matrix [Y ]8×8 . (see (6))
is used to evaluate [T H ](2) in Fig. 3. Equation (2) is also We may now obtain the admittance matrix [Y R ]5×5 of the
used to compute [T H ](4) , but by the substitutions of unity 5-port network in Fig. 3 by the combination of admittance
matrix [U]2×2 , [T (5) (6)
H ]2×2 , [T H ]2×2 in Fig. 3 and [U]2×2 in matrices of 3-port network ([Y R ]3×3 ) and 6-port network

⎡ ⎤ ⎡ ⎤
(1)
tH,11 0 0 0 tH(1),12 0 0 0
⎢ ⎥ ⎢ ⎥
⎢ 0 t (2) 0 0 ⎥ ⎢ 0 t (2) 0 0 ⎥
⎢ H,11 ⎥ ⎢ H,12 ⎥
[A]4×4 = ⎢ ⎥ [B]4×4 = ⎢ ⎥
⎢ 0 (3)
0 tH,11 0 ⎦ ⎥ ⎢ 0 tH,12 0 ⎥
(3)
⎣ ⎣ 0 ⎦
(4) (4)
0 0 0 tH,11 0 0 0 tH,12
⎡ ⎤ ⎡ ⎤ (3)
(1) (1)
tH,21 0 0 0 tH,22 0 0 0
⎢ ⎥ ⎢ ⎥
⎢ 0 t (2) 0 0 ⎥ ⎢ 0 t (2) 0 0 ⎥
⎢ H,21 ⎥ ⎢ H,22 ⎥
[C]4×4 = ⎢ ⎥ [D]4×4 = ⎢ ⎥
⎢ 0 0 t (3)
0 ⎥ ⎢ 0 0 t (3)
0 ⎥
⎣ H,21 ⎦ ⎣ H,22 ⎦
(4) (4)
0 0 0 tH,21 0 0 0 tH,22

(4)

⎡ ⎤
y33 + 2 ∗ y34 + y44 y31 + y32 + y41 + y42 y38 + y48 y35 + y45 y37 + y47 y36 + y46
⎢ y31 + y32 + y41 + y42 y11 + 2 ∗ y12 + y22 y18 + y28 y15 + y25 y17 + y27 y16 + y26 ⎥
⎢ ⎥
⎢ y38 + y48 y18 + y28 y88 y58 y78 y68 ⎥
⎢
[Y S ]6×6 = ⎢ ⎥ (6)
⎢ y35 + y45 y15 + y25 y85 y55 y75 y65 ⎥ ⎥
⎣ y37 + y47 y17 + y27 y87 y57 y77 y67 ⎦
y36 + y46 y16 + y26 y86 y56 y76 y66

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([Y S ]6×6 ) in (7) (see (7))

where yR,ij and yS,ij are the entries in the ith row and jth
column of matrices [Y R ]3×3 and [Y S ]6×6 , respectively, and

  −1
p11 p21 y + yS,22 yR,23 + yS,21
= − R,22 (8)
p22 p22 yR,23 + yS,21 yR,33 + yS,22
Fig. 4 Combination of the admittance matrices [YR](m+2)×(m+2)
We have thus designed a 4-output port divider. We may and [YS]6×6
obtain a 3-output port divider by connecting two ports, for
example, 4′ and 5′ in Fig. 3. We may increase the number
of output ports of the divider by connecting a 6-port circuit output ports. If the nth and (n + 1)th port in an (n + 1) port
([Y S ]6×6 ) as in Fig. 3 to the above 5-port circuit, to obtain a network are connected together the admittance matrix of the
5- or 6-output divider. n-port network may be obtained as (11) (see (11))
In general, a 6-port circuit may be connected to an (m + 2)
port circuit (as shown in Fig. 4) to increase the number of where yR,ij is the entry of ith row and jth column of the
output ports by one or two. Note that here m is always an odd admittance matrix of [Y R ] in (9). The scattering matrix of the
number. Consequently, the admittance matrix of the (m + 4) network may be obtained from its admittance matrix as
port network, namely [Y R ](m+4)×(m+4) may be obtained from derived above [7].
the admittance matrices [Y R ](m+2)×(m+2) and [Y S ]6×6 as

[Y R ](m+4)∗(m+4) = [E] + [F] ∗ [P] ∗ [G] (9)

where (see (10))
and yR,ij and yS,ij are the ith row and jth column of the admittance
matrices of [Y R ] and [Y S ] shown in Fig. 4, respectively, and
[0]m×n is the zero matrix of order m × n. In this
configuration, the number of output ports is even. Two output
ports may be connected together to obtain an odd number of
3 Design procedure
An equivalent circuit for this power divider with an arbitrary
number of ports is developed in theory and analysis, where its
scattering parameters, such as return losses at all the ports
(Siik), the power division ratios and isolation among output
ports (Sijk) and also the phase difference (Dwijk) between
the ith and jth ports are obtained. They are used in the
construction of an error equation, which is a function of

⎡ ⎤ ⎡ ⎤ ⎡ ⎤ ⎡ ⎤
yR,11 0 0 0 0 yR,12 yR,13 0 0 0 p11 p21 0 0 0 yR,12 yS,32 yS,42 yS,52 yS,62
⎢ 0 yS,33 yS,34 yS,35 yS,36 ⎥ ⎢ 0⎥ ⎢p p 0 0 0⎥ ⎢ ⎥
⎢ ⎥ ⎢ yS,32 yS,31 0 0 ⎥ ⎢ 12 22 ⎥ ⎢ yR,13 yS,31 yS,41 yS,51 yS,61 ⎥
⎢ ⎥ ⎢ ⎥ ⎢ ⎥ ⎢ ⎥
[Y R ]5×5 = ⎢
⎢ 0 yS,43 yS,44 yS,45 yS,46 ⎥ ⎢
⎥ + ⎢ yS,42 yS,41 0 0 0⎥ ⎢
⎥∗⎢ 0 0 0 0 0⎥ ⎢
⎥∗⎢ 0 0 0 0 0 ⎥ ⎥
⎢ 0 yS,53 yS,54 yS,55 yS,56 ⎦ ⎢
⎥ ⎥
0⎦ ⎢ ⎥ ⎢ ⎥
⎣ ⎣ yS,52 yS,51 0 0 ⎣ 0 0 0 0 0⎦ ⎣ 0 0 0 0 0 ⎦
0 yS,63 yS,64 yS,65 yS,66 yS,62 yS,61 0 0 0 0 0 0 0 0 0 0 0 0 0
(7)

(10)

(11)

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the widths and lengths of line section. Table 2 Optimum dimensions (unit, mm) of the 3-output port
power divider

i
W1 W2 W3 W4 W5
error = Wtijk (Sijk − Gijk )2
k i=1 j=1 1.91 1.19 1.56 0.88 2

n W6 W7 W8 L1 L3 L7
+ W Dwijk (Dwijk − DwGijk )2 (12) 1.27 1.49 1.35 8.05 7.39 6.17
k i=2 j=i+1

where the specified frequency interval is divided to K discrete

frequencies and k denotes the kth frequency in the band,
Wtij( fk) and WDwij( fk) are weighting functions and Gijk and
Gw1jk are the design goals at frequency fk. The error is a
function of geometrical dimensions of the divider
configuration, such as the widths and lengths of the line
sections. The minimisation of the error equation provides the
optimum design of the divider, which is performed by a
combination of genetic algorithm (GA) and conjugate gradient
(CG) method. The GA is a slowly converging global extremum
seeking algorithm, which does not need a starting point. The
Matlab OPTIM toolbox [10] is used for the minimisation of
the error equation. We apply its default option for the
implementation of our proposed minimisation algorithm. The Fig. 5 Photograph of the fabricated 3-output port power divider
parameters of GA are as follows: mutation ratio is 0.5 and cross
over number is 1. The initial values for CG algorithm are
obtained after running GA. However, the minimisation of the Observe that the algorithm and computer programmes
error equation is performed under constraint, wherein the values determine the lengths and widths of line sections.
of widths and lengths of line section are constrained to lie A photograph of the fabricated power divider is shown in
between specified limits. This is required for the physical Fig. 5. The Agilent Network Analyzer E5071C is used for its
realisation of striplines (with the characteristic impedances test and measurement. Note that the phases of signals from
lying between 35 and 150 V). The lengths of line sections are the output ports are not identical, because the signal paths are
limited to about a quarter wavelength of the centre frequency. not equal. In order to correct and equalise the output signal
The stopping criteria for the minimisation algorithm are phases, some transmission line sections are included in the
specified on the minimum value of error equation and its output ports outside the dividers, in such a way that they do
gradient and also the increment between two successive not affect its magnitude of scattering parameters.
values of a variable (namely, widths and lengths of line section). Although the losses because of the substrate and resistors in
The minimisation of this error equation may be carried out the divider structure are considered in the error equation, they
by the appropriate toolboxes in HFSS or CST. However, such may not be separated and evaluated individually. However,
a procedure is very CPU time consuming and circuit designs they appear and are highlighted in the unbalance among the
based on them are quite heuristic. input and output power. Namely, the output power becomes
less than the input power. Consequently, the efficiency of
the divider will be less than 100%. For example, the
4 Example 1 efficiency of this divider is drawn against frequency in
Fig. 6, which is better than 95%.
We first design a power divider (or combiner) with three output
ports, having identical input/output port impedances of
50 V. The power division among the three output ports is
different. The divider is to operate in the frequency interval
5–7 GHz. The design goals of this divider are specified in
Table 1. The geometrical configuration of this divider (with
dimensions) is drawn in Fig. 1. The substrate RT5880 with
1r ¼ 2.2, h ¼ 31 mil and tan d ¼ 0.0009 is selected for the
design and fabrication. The chip resistors of divider circuit
are selected equal to 100 V. The geometrical dimensions of
the optimum design of divider are given in Table 2. All Wt’s
are equal to 1 except for Wt12 , Wt13. . .Wt16 are equal to 3.

Table 1 Design goals (dB) of the 3-output port power divider

G11 G22 G33 G44 G12

220 220 220 220 24.7

G13 G14 G23 G24 G34

27.7 23 220 220 220

Fig. 6 Efficiency of the 3-output power divider

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The return losses (Sii) at the divider ports as obtained by
the proposed design algorithm, HFSS full-wave simulation
software and measurement are all less than 220 dB in the
specified bandwidth (the curves are omitted for brevity).
The power division ratios (S1i) obtained from the proposed
algorithm and measurement are drawn in Fig. 7.
The variation of power division levels is less than 0.5 dB.
The isolations among the output ports (Sij ) are drawn
in Fig. 8. They are less than 220 dB in the design
frequency interval. The phase difference among the output
port signals is drawn in Fig. 9. It is less than 58 in the
design frequency interval. The variations of group delay
among the input and output ports are about 4 ps in the
design frequency interval.
The discrepancy between the simulation results and
measurement data is because of the approximate circuit Fig. 9 Signal phase differences among the output ports of the
model (which ignores the coupling among line sections), 3-output port power divider
tolerance of resistors, imperfect fabrication processes and
measurement errors.
70, 40, 60 and 50 V at ports 1, 2, . . . ,6, respectively. The
5 Example 2 geometrical dimensions of the divider configuration are
indicated in Fig. 10. The design frequency interval is
We next design a power divider (or combiner) with five 5 – 7 GHz. The chip resistors for this divider are selected
output ports, having different impedances equal to 50, 50, equal to 100 V. The substrate RT5880 is selected for the

Fig. 7 Insertion losses among the input and output ports of the 3-output port power divider

Fig. 8 Isolations among the output ports of the 3-output ports power divider

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Fig. 10 Design parameters for the configuration of the 5-output port power divider

Table 3 Design goals of 5-output port power divider to 3. A photograph of the fabricated prototype of the optimum
divider is shown in Fig. 11.
G11 G22 G33 G44 G55 G66 G12 The scattering parameters of the fabricated power divider
220 220 220 220 220 220 27 are measured by the Agilent Network Analyzer E5071C,
with assumed port impedance of 50 V. Then its admittance
G13 G14 G15 G16 G23 G24 G25 matrix is obtained, which is independent of port impedance.
27 27 27 27 220 220 220 Subsequently, the scattering parameters of the divider with
distinct and different port impedances are computed by
G26 G34 G35 G36 G45 G46 G56
appropriate relation [7, 11, 12].
220 220 220 220 220 220 220 The return losses (Sii) of this divider as obtained by three
sets of data through the proposed numerical design
algorithm, HFSS and measurement better than 220 dB in
the design frequency interval (the curves are omitted for
brevity). The power division ratios (S1i) for the above set of
data are drawn in Fig. 12. Their variations are less than
0.5 dB. The isolation among the output ports (Sij ) are better
than 220 dB inside the design frequency interval (the
curves are omitted for brevity).

Fig. 11 Photograph of the fabricated 5-output port power divider
design and fabrication of the 6-port divider. The design goals
and optimum dimensions of this divider are given in Table 3.
All Wt’s are equal to 1 except for Wt12 , Wt13. . .Wt16 are equal
6 Conclusions
A novel device configuration is presented for the arbitrary
division and combination of microwave power together with
the incorporation of impedance matching among its terminal
ports. The proposed single-layer planar structure is capable
of providing a much broader bandwidth than the Wilkinson
power divider for the division of input power among its
output ports and also combining several input powers into an
output port. In contrast, the N-way Wilkinson and Gysel
power dividers require a multi-layer structure to provide
several output ports. The proposed device may be obtained

Fig. 12 Insertion losses among the input and output ports of the 5-output port power divider

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& The Institution of Engineering and Technology 2012 doi: 10.1049/iet-map.2011.0201

for matched terminal ports and also high isolation among its
output ports. The proposed device configuration is quite
simple and may be readily used for the practical applications
of microwave power combination and division.
The circuit design by the proposed method is quite effective
and gives the optimum configuration. Further optimisation
by the available full-wave EM simulation softwares is not
needed. Other combinations of available power dividers may
be further investigated to obtain improved designs.
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