System Bus:

Bus is a group of wires or conductors used for communication between processor , memory and i/o
devices.
There are 3 types of buses. 1).Address bus 2). Data bus 3).Control bus
1. Address bus:
Purpose:
1.It is used to transfer the address of either memory or i/o from the processor.
2. It defines the maximum memory that can be connected to a processor given by the
Relation. 2n=N, Where, n= number address line, N= Number of address/memory locations.
Length: It is of 16 bits in length for 8085.
Direction: Address bus is unidirectional
2. Data bus:
Purpose: it is used to transfer data between processor, memory & i/o devices
Length: It is of 8 bits in length for 8085
Direction: Data bus is bidirectional.
Note: there is no separate data bus in 8085, the lower order address lines can be used either as
address or data bus, using a signal known as ALE- address latch enable.
3. Control bus: It is group of different control, timing & status for various operations of the processor
It doesn’t have any direction as every signal does different job.

Ex, RD, WR

Basic Interfacing components:

1. Tristate buffer—Used when more devices are connected to common bus to select one of them.
Tristate Buffer:
It is used when many devices are connected to common bus. It is used to amplify or increase the power or
current level of the bus.
It has three states 1). Logic 0 2). Logic 1 3).High impedance state (Z/ Tristate)
 In high impedance state, the line doesn’t draw any current from the system.
Circuit symbol of Tristate Buffer:
If E=0; Active/logic 0/1
=1; inactive/z/high impedance state/tristate

2. Decoder – Logic circuit , which can identify the combination of input signals and selects one of
the output signals. Used in decoding logic of memories & I/O devices.
3. Encoder – Logic circuit which can produce or generate the code of one of the input at o/p.
Used in communication systems and also to interface a keyboard to a computer.
4. Latch—used to to hold the lower byte of the address till read / write operations are completed.

Internal Architecture of 8085:

It is divided into 5 functional units:
1. Register Unit
2. ALU
3. Timing and control Unit
 4. Interrupt control Unit
5. Serial I/O control Unit

1. Register Unit:
There are two types of registers
1. General purpose Registers
2. Special purpose Registers
 General Purpose Registers:
There are 6, 8bit general purpose registers, namely
B, C, D, E, H &L . They can also be used as register pairs of 16bit length.
1. BC 2. DE 3. HL
Any of them can be used to point the memory but HL pair is also known as default memory or data
pointer.
Ex. MOV D,M
‘M’ –indicates memory content or memory location whose address is present in HL pair only.
Whichever the instructions have ‘M’, the reference of the memory should be considered as HL pair

 Special Purpose Registers:

Accumulator: 8-bit Multi-purpose register by which almost all ALU operations are performed. One
of the bytes must be present in ‘ACC’/’A’ , result is also stored in ACC.
 Program Counter:--PC
16 bit register which contains the address of the next instruction to be executed or it takes of the
program flow or control. It is automatically incremented by one after an operation depending on
the instruction.

Instruction Register:
It is an 8 bit register which contains the opcode of present instruction. It does not contain data.
Instruction decoder and machine cycle encoder:
After the opcode is accessed in to IR, it is decoded in this block with the help of Microprogram. The number
of operations is assigned according to the type of instruction.
Microprogram: It is a program written by chip designer to make the processor to understand what an
instruction is or it indicates the type of operation to be performed for an instruction. It is present inside the
processor. It is also called as control program.
 Stack Pointer: SP
It is a 16bit register which contains the address of the data present at the top of stack memory or it points
to top of the stack.
 Stack: It is a part of Read/Write memory, used to store temporary data and also the content of
program counter when subroutines are used.
 The technique involved in stack is LIFO i.e. Last in First out.
When data is stored in to STACK, SP is decremented, similarly SP is incremented when data is accessed
from stack. Only register pair contents can be stored into stack in 8085, a single register is not possible.
When a RP(register pair) content is stored into stack, first higher nibble is stored and then lower nibble is
stored.

Flag Register:
There are 5 flags or flip-flops in 8085 which give the status after an ALU operation. They are affected by the
content of Accumulator, except in few instructions where they may also be modified for general purpose
instructions like INR R & DCR R( increment and decrement instructions).
D7 D6 D5 D4 D3 D2 D1 D0
S Z X AC X P X CY

S- Sign; Z- Zero; AC – Auxiliary Carry; P- Parity;

Cy-Carry
S- 0/1 – Depending on the D7 bit of accumulator .In Signed operations S 0; +ve Result; S 1; -ve Result
Z 1; if result in ACC=00H
 0; Otherwise.
AC 1; if there is carry from D4 bitD3 bit or
Higher nibble  Lower nibble
0; otherwise
P1; if the number of binary 1’s in ACC=Even
0; if the number of binary 1’s in ACC=odd
CY 1; if there is a carry i.e out of D7 bit.
0; otherwise.

Temporary Registers:
W & Z are the two 8 bit temporary registers which cannot be accessible by programmer. They are used by
the processor in some instructions.

ALU: Arithmetic & Logic Unit:

It is the combination of ACC, Temporary register, Flag register & arithmetic and Logic circuits.
The various ALU operations possible in 8085 are:
Addition, subtraction, Increment, Decrement
AND, OR, EX-OR, COMPARE, COMPLIMENT & ROTATE
 Flags are modified only for ALU operations

Timing & Control Unit:

It is responsible for generating various control, timing and status signals used for the operations of the
processor, Like M/M Read , M/M Write.
X1 & X2 a crystal oscillator is connected between these pins, to provide stable oscillations.
 Operating frequency of 8085 is 3 MHz.( it is half of crystal frequency)
FCLK = 3MHz. Range 3 – 6 Mhz.
ALE—Address Latch enable
 1; all 16 address lines will act as address bus
 0; A15- A8 Address bus & AD7- AD0 Data bus
 Used to make AD7 – AD0 either as address or data bus.
RD Read control signal; low active signal; WR Write control signal; low active signal
0; Active 0; Active
I0/ M 0; Memory operation
1; I/O operation
S1 & S0 status signals which indicate the status of Bus cycle for an operation. They are used by other
systems to know the status of processor.

I0/ M S1 S0 STATUS
Z 0 0 HALT
0 0 1 M/M Write
0 1 0 M/M Read
0 1 1 Fetch
1 0 1 I/O Write
1 1 0 I/O Read
1 1 1 INTA
Z X X HOLD
Z X X RESET
Z-Tristate state/High impedance state

HOLD & HLDA:

Purpose of DMA : when more data has to be transferred between memory and I/O devices at a faster rate ,
Direct memory access operation is used with the help of DMA controller.
HOLD: High active input signal to the processor from DMA controller requesting buses for DMA operation.
 Sequence for the DMA operation (considering data to be accessed from memory to output device).
1. µp receives HOLD signal DMA controller.
2. µp Completes current operation and responds with HLDA.
3. The control of buses is given to DMA controller.
4. After completing data transfer, the control of buses is accessed by the µp.
This process of data transfer is known as DMA operation.
By using using DMA operation, there is no need of opcode fetch for every single data byte. Once the address and
count registers are loaded in DMA controller, the data is transferred till the count becomes 0.
HLDA: hold acknowledgement—out put signal in response to hold request.
Modes of DMA:
1. Burst mode:-- HOLD remains high until whole data is transferred between memory and I/O
Ex. Burning of CD or DVD.
2. Cycle stealing technique/ short burst mode: data is transferred in the form of blocks. Processor can take
the control of the buses after transferring a block of data.
3. Interleaved DMA: The buses of the Processor are used when it performs internal operations. In this
mode, one byte/ word is transferred per instruction. Ex. While decoding the opcode buses are used by
DMA controller.

 Reset-in—low active input signal to the processor to reset it. PC= 0000H
Reset out: o/p signal which indicates that the processor is reset. It can be used to reset the i/o devices.
Clock out: o/p pin on which same operating frequency of the processor is available.
Ready: i/p signal to the processor from a slow speed i/o device or memory.
Ready1; mp transfers or receives data from i/o
0; mp waits for the i/o device.
Interrupt control Unit:
Interrupt is an external signal or an instruction which may disturb or alter the sequence of execution of the
processor or it is a method by which an i/o informs the processor that it requires the service from the
processor.
Interrupts can be classified as :
1. Hardwired & software interrupts
2. Maskable & Non-Maskable interrupts
3. Vectored & Non- Vectored interrupts

1. Hardware interrupts: There are 5 hardware interrupts in 8085 according to priority. TRAP to INTR
Software interrupts: There are 8 software interrupts, which can be used either as instructions or
along with INTR interrupt. RSTn; n= 0- 7, RST0, RST 1--RST7
2. Maskable interrupts : Interrupts which can be ignored when they are triggered.
Non-Maskable Interrupts: Interrupts which can not be ignored when triggered. Ex: TRAP
It must be connected to highly prioritised events in practical applications like power failure issues.
3. Vectored Interrupts: Interrupts which have specific address location in memory to store ISR.
Non-Vectored Interrupts: Interrupts which do not have specific address location in memory.
Ex: INTR
Vector address Type of triggering
1. TRAP/NMI/RST 4.5 0024H Edge & level
2. RST 7.5 ----- 003CH Edge
3. RST 6.5 ----- 0034H Level
4. RST 5.5 ----- 002CH Level
5. INTR- ----- No address Level
INTR---Non-vectored interrupt( it does not have any specific location). 8 I/O devices can be connected
by using INTR with the help of priority encoder. It is also known as polled interrupt.
INTA- Interrupt acknowledgement- o/p signal in response to interrupt request.
It is required only for INTR interrupt not for vectored interrupts.
ISR/ISS: It is a program that is executed in response to an interrupt. Every vectored interrupt in 8085 is
allocated 8 bytes in memory to store the corresponding ISR. Programming logic can be used if the length of
program exceeds 15 bytes. In case of vectored interrupt there is a built in logic which loads the PC with the
vector address of the corresponding interrupt.

Serial i/o Control Unit:

Used for serial communication between mp and serial i/o devices. Bit by bit transmission is done in serial
communication. Ex: connection between computer and a printer( RS232 C-Serial communication standard)
SID- Serial i/p data pin—used to receive serial data
SOD- Serial o/p data pin – used to transmit serial data.
PIN LAYOUT:
 8085 is a 40 pin IC in DIP – dual in-line package, designed with NMOS technology( n-type metal
oxide technology)
 i/p pins----13/21, o/p pins----27.
PROGRAMMING MODEL:
Program: set of instructions
Instruction: it is a command given to a computer to perform a specific task.
Machine level language: Binary medium of communication with a computer through a designed set of
instructions, specific to a system.
Assembly level language: Instructions are written in separate words known as mnemonics.
Ex: MOV A,B ADD C
 Both assembly and machine level languages are known as low level languages
High level language: they are machine independent. Ex. C, C++, JAVA
Softwares:
Compiler: converts HLL to machine level language, where entire program is converted at a time
Ex; Turbo C, XLC, Javac
Interpreter: HLL—MLL line by line,Ex: M-BASIC
Assembler: Assembly program to Machine code, MASM—microsoft macro assembler.
Cross Assembler: It translates the opcodes of one processor in to opcodes of another processor.
Loader: used to load the program into memory, it also converts hex code to binary( ex; .EXE file)
Source code: Assembly program which is written for a certain application.
Object code: o/p of the assembler
Monitor/ control program: it is a program which is similar to OS (Operating system) software in
microprocessor environment. It takes care of initialization procedure and user interactions. It is present in
the external memory.
It loads the PC with the starting address of actual program when the “enter or execute” key is pressed.
 Note: Programmer cannot load the PC directly with the starting address of program.
Basic steps of execution: 1). Fetch 2). Decode 3). Execute

Instruction format:
Every instruction has two parts 1). Opcode 2). Operands.
Opcode: indicates the type of operation to be performed
Operands: It is the data on which operation is to be performed.
Instruction length: Number of bytes an instruction occupies in the memory.
There are 3 types of instructions classified according to the length:
1. 1 byte/word instructions 2. 2 byte/word instructions 3. 3Byte/Word instructions.
*****After decoding an opcode, the processor understands:
1. Length of instruction 2. Number of operations required for execution.
Addressing modes:
These are various formats specifying the operands or they indicate how data is accessed for an instruction
1. Immediate Addressing mode: Data is in the instruction. Ex. MVI B, 90H
2. Direct addressing mode: Address of the data is in the instruction. EX. LDA 6000H
3. Indirect addressing mode: Address of the data is present as the content of another register pair
EX. LDAX B
4. Register addressing mode: Data is transferred between registers. EX. MOV B,C
5. Implicit/ Implied addressing mode: Address of the data is in the instruction itself. EX. CMA,RAL

TIMING DIAGRAM: / Instruction execution with respect to various signals.

It is the pictorial representation of execution of an instruction with the help of various control ,timing and
status signals.
T-State: it is one subdivision of an operation performed in one clock period.
FCLK= 3 MHz, T=1/f=1/3 x 106 = 0.33µs.
Machine cycle: It is the time required to access memory or i/o ( either for read/write)
1 M/c may have 3 to 6 T-States.
Instruction cycle: It is the time required to complete the execution of an instruction.
1I/C may have 1 to 5 machine cycles.
Note: maximum T-State for an instruction in 8085 is 18. Ex. Call 16 bit address—3B,5 M/C’s, 18- T-States.

Instructions in 8085
1. Data transfer or copy instructions: data is transferred from source to destination.
2. Arithmetic instructions:
Perform operations like Addition, subtraction, increment & Decrement.
3. Logical instructions: AND, OR, EX-OR, Compare ,Compliment & Rotate
4. Branching Instructions: Program control is transferred from one location to another
conditionally or unconditionally .Ex: JUMP, CALL , RETURN & RST n.
5. Machine control Instructions: Used for internal machine control operations of processor.
Depending on the type of instruction, the number of operations may one or more.
How to read an instruction :
M—Move; [ ]—Content of ; [ [ ]] ---Reference or content of
I—Immediate; LD/L—Load ; Access data from memory to µp.
RP—Register pair ; ST/S—Store; Data from µp memory
‘X’- Cross—indicates operation is performed on a RP
RH- Higher byte of register pair; RL- Lower byte of register pair
Fields of an instruction:
• LABEL: MNEMONIC OPERANDS; STATEMENT
Between operands , must be used
Ex: L1: DCR C ; Decrement the content of Register ‘C’

Data transfer instructions

Instruction Meaning Example
MVI R, 8 Bit data Move immediate 8-bit data to register MVI C, 90H
MOV Rd ,Rs Move content of source register to destination MOV A,B
LXI RP, 16bit value Load immediate 16bit value into register pair LXI H, 8000H
MOV R, M Move content of memory to register i.e& ref of HL MOV D,M
pair
MOV M, R Move content of register to memory MOV M, E
MVI M, 8bit data Move immediate 8bit data to memory MVI M, 75H
LDA 16Bit address Load data @ 16bit address to accumulator LDA 4000H
STA 16bit address Store the content of ‘A’ @ 16bit address STA 3000H
LDAX Rp Load Accumulator with data , whose address @ LDAX B
reference of Rp.
STAX RP Store Accumulator content @address present in Rp. STAX D
PUSH RP Store the content of Rpinto stack memory. SPSP-2 PUSH D
POP RP Access data from top of stack in Rp. SPSP+2 POP H
IN 8-bit port address Read the data from 8bit port address in A IN 60H
OUT 8-bit port address Transfer the content of A to o/p port OUT 70H

ARITHMETIC INSTRUCTIONS
ADD R ADD M ADI 8 bit data
ADC R ADC M ACI 8-bit data
SUB R SUB M SUI 8-bit data
SBB R SBB M SBI 8-bit data
ANA R ANA M ANI 8-bit data
ORA R ORA M ORI 8-bit data
XRA R XRA M XRI 8-bit data
CMP R CMP M CPI 8-bit data
Compliment--CMA – compliment content of accumulator
 CMC – Compliment carry ; STC –Set carry---to set carry flag.
ROTATE ---RLC, RAL , RRC , RAR( rotate 1 bit left / right with orwithout carry)
Branching Instructions
JUMP : To transfer control of program from one location to another
There are conditional and unconditional instructions
Conditional: depend on status of flags
Ex: JZ 16bit address(if Z=1, in previous ALU operation, then jump to the address , else go to next
instruction in the program.)
Similarly all flags except AC have the instructions.
JNZ,JC,JNC,JPE,JPO,JM,JP
Unconditional Jump : JMP 16bit address—go to the address mentioned in the instruction without any
condition.
CALL : To call a subroutine within the main program.
Subroutine: A program which performs specific function can be written as a separate program away
from main program. It can be repeatedly used in the main program.
CALL also has conditional and unconditional instructions.
Unconditional CALL:- CALL 16bit address

When CALL (or interrupt is activated) is executed, the steps followed by processor:
1. Store/Save the address of next instruction(PC content) in the stack ,i.e SPSP-2 (so that it can
return from the function or subroutine by using a RET instruction.)
2. Go to the subroutine address and continue the program

Conditional CALL  operation is same as unconditional CALL, but flag condition is verified before the
control is transferred.
CZ,CNZ,CC,CNC,CPE,CPO,CM,CP

RETURN: used to return the control of a program from a subroutine or an interrupt service routine.
It also has conditional and unconditional .
Unconditional return RET
When RET is executed:
1. Processor accesses the data(2B) at top of stack in to PC, i.e SPSP+2
2. Program control is transferred to the 16bit address value
For conditional Return instructions also operation is same except that the flags condition is verified
before the transfer.
Ex. RZ,RNZ,RC,RNC,RPE,RPO,RM, RP.
RSTn—Software interrupts , where n=0-7
 Also known as 1Byte unconditional CALL instruction.
 Operation is similar to CALL instruction.

MACHINE CONTROL INSTRUCTIONS

HLT— stop the execution of a program.
NOP—No operation
DI—Disable maskable interrupts
EI- Enable maskable interrupts
SIM—Set interrupt Mask—to mask the interrupts or make them available & also for sending serial data
out of SOD pin.
RIM—Read interrupt mask—to know the status of pending interrupts and to receive serial data
through SID pin.

SPECIAL INSTRUCTIONS
LHLD 16bit address Load HL pair with the data @ 16bit address i.e 2bytes
SHLD 16bit address Store the contents of HL pair @ 16 bit address
PCHL Copy the content of HL pair to PC
 Also known as 1B JUMP instruction
SPHL Copy the content of HL to SP
XCHG Exchange the contents of DE & HL pairs
XTHL Exchange the contents at top of the stack with the HL pair.
 SP is unchanged
DAD RP Add the contents of Register pair to HL pair. Result is stored in HL Pair
only.
 DAA Decimal adjust Accumulator—Used in the BCD conversions.
*This is the only instruction which works with the status of AC flag
Converts 8bit value in Accumulator into two 4bit BCD values.

Important Interfacing IC’S which are used in a computer:

• 8251- USART- Universal synchronous asynchronous receiver and transmitter– Used for serial
communication . Ex. RS 232C
• 8253/54- Programmable timer / counter—To generateTime delays/counters, Real time clock .
• 8255-PPI/PIO-Parallel i/p o/p device- frequently used device for interfacing I/O devices.
• 8257/37- DMA controller– To transfer more data between memory and I/o at a faster rate.
Ex. Accessing the data from hard disk like CD/DVD writing.
• 8259-PIC-Priority Interrupt controller—to increase interrupt handling capability of a µp – maximum
of 64 i/o devices can be connected if used in cascade mode of operation i.e using 9(Nine), 8259’s
• 8279- Keyboard/Display controller.

Applications of Microprocessor:
1. Industrial process and control applications
2. Bio-medical instrumentation
 ECG and patient monitoring systems
 MRI, CT scanning systems.
3. Military and navigation equipment
 Radar control, communication
 Satellite and Rover systems in exploration.
4. Educational Institutes i.e laboratory purpose
5. Home appliances like TV, Intelligent washing machines, fridges etc.
6. Automobile industry – Car high end applications like- Anti braking system,
7. Audio speech processing.
8. Electronic gadgets
9. Robotics and neural networks
Assembler directives:
 These are hints given to assembler by programmer while writing an assembly language program.
 ORG--origin
 DB – define byte – 1byte memory space is allocated for the variable.
 Ex: x db 12h,34h/ x db 10h dup( )
 DW- define word –2bytes space
 DQ –define quad word
 End –end of program, ENDS—end of segment

Important questions in Microprocessors , Microcontrollers& PLC

1. INTEL 8085 is
a. 16 bit µp b. 8 bit µp c. 4 bit µp d. 32 bit µp
2. Internal memory of 8085 is
a. 64KB b. 0 KB c. Can be of any size d. none
3. If a memory has 256 registers & 4 bits per location then the capacity of the memory is
a.128B b. 256 B c. 512B d. 1KB
4. The data lines in 8085 processor are multiplexed with address lines.- true or false
5. Result of most of the ALU operations in 8085 is stored in
 a. ACC b. In any register c. PC d. SP
6. PC Contains
a. Address of previous instruction b. Address of the data in stack
c. current program d. Address of the next instruction to be executed
7. The technique involved in the stack for 8085 is
a. LIFO b. FIFO c. FILO d. None
8. After the processor is reset. The value in PC & SP are
a. 0000H, 0000H b.FFFFH, 0000H c. 0000H, user defined d. None
9. The sum of A & B, if they have 76H & 9DH. Also find the status of flags.
a. 13H & 84H b. 13H & 11H c. 1DH & 11H d. None
10. The operating frequency of 8085 is
a. 6 Mhz b. 3Mhz c. 2 Mhz d. None
11. The correct sequence for execution of an instruction in any processor is
1. opcode fetch 2. Execute 3. Decode
a. 2,3,1 b, 3,2,1 c. 1,3,2 d. No sequence while execution
12. A program is first stored in the processor, then only execution takes place---True / False
13. 8085 follows _____________ architecture for the memory connected to it
a. Harvard b. Princeton c. Both a & b d.none
14. The Multiplexing concept for bus is used in processors in order to
a. Reduce cost of design b. Complexity c. Both a & b d. Multiplexing is done in microcontrollers
15. In DMA operation, the data is transferred
a. Inside the processor only b. Between memory and microprocessor c. Memory and I/O d.none
16. Zero flag in 8085 is ‘1’ if result of some ALU operation is
a. 00H b. FFH only c. There is no zero flag in 8085. d.none
17. one of the following interrupt in 8085 is Non-maskable or can not be disabled
a. RST 7.5 b. RST 6.5 c. TRAP d. INTR
18. The only PIN in 8085, which can support more than one interrupt is
a. TRAP b. RST 5.5 c. RST 7.5 d. INTR
19. ISR/ISS with respect to interrupts stands for
a. Interrupt Service Range b. In Service route c. Interrupt Service Routine d. None
20. The correct sequence of priority in 8085 for interrupts is
1. TRAP 2. RST 5.5 3. RST 6.5 4.RST 7.5
a. 1,2,3,4 b.4,3,2,1 c. 2,3,4,1 d. 1,4,3,2
21. As compared to Parallel communication, Serial communication is
a. Faster b. Cheaper c. Logical d. Noise free
22. The maximum pins present in 8085 are
a. 50 b.45 c.40 d.100
23. Maximum of length of instruction in 8085 is 3Bytes, where as in 8086 , it is 6bytes. True / False
24. The instruction has two parts ---
a. Opcode & Operands b. 1st part & 2nd part c. 1st version& 2nd version d. None
25. READY pin of the processor, gets the signal from
a. High speed I/O b. Slow speed I/O c. Any one of a/b d. Can be from both a & b
26. Maximum memory that can be connected to 8085 is
a. 64KB b. 128KB c. 8KB d.none
27. The length of Instruction STA 8000H is
a. 2 Bytes b. 3bytes c. Instruction doesn’t have length d.none

28. The bus protocol which is generally used in automobiles is

a. USB b. I2c c. CAN d.none
29. If a program requires 90 T-states for execution in 8085 , find the total execution time
a. 15µs b. 45µs c. 30µs d.none
30. An interfacing component, which is used with bus when more devices are connected to common bus
a. Decoder b. Encoder c. Latch d. Tri-state Buffer
31. The data lines for a memory (RAM or ROM) depend on
a. Bits in each memory location b. total data c. Memory locations d.none
32. The principle involved in CD,DVD OR Blue raydisk writing is
a. Blue print b. Radiation c. Light d. Magnetism
 33. One of the main differences between a processor & Controller is
a. Internal memory b. Timers/counters c. ADC d.all
34. In 8051 microcontroller the internal ROM & RAM are
a. 4KB & 128 Bytes b. 128Bytes & 4KB c. 64Kb & 128 KB d.none
35. Microcontrollers are generally used for
a. Specific purpose only b. General purpose c. a/b d.none
36. In 8051, there is no separate ‘Z’( Zero) Flag---True / False
37. The Digital transmission of data has less affect due to
a. Wind b. Temperature c. Noise d. Light
38. Both RAM & ROM are
a. Random in accessing the data from memory b. Sequential in accessing
c. Non-volatile memories d. Temporary memory
39. RISC stands for----Reduced instruction set computer

Key:
1.B 2.B 3.A 4.TRUE 5.A 6.D 7.A
8.C 9.B 10.A 11.C 12.FALSE 13.B 14.C
15.C 16.A 17.C 18.D 19.C 20.D 21.
22. C 23. TRUE 24.A 25.B 26.A 27.B 28.C
29.C 30.D 31.A 32. C 33.D 34. A 35.A
36. TRUE
37. C
38. A