2019 6th International Conference on Signal Processing and Integrated Networks (SPIN)
FPGA Implementation of FEC Encoder with BCH &
LDPC codes for DVB S2 System
Durga Digdarsini, Deepak Mishra, Sanjay Mehta, TVS Ram
Space Applications Centre (SAC), Indian Space Research Organization (ISRO)
Ahmedabad, Gujarat, India
digdarsini@sac.isro.gov.in
Abstract—This paper gives the design and implementation of
Xilinx FPGA based Forward Error Correction (FEC) encoder for
DVB S2 system which includes BCH code followed by LDPC code
and finally bit mapped to constellation for QPSK modulation.
DVB-S2 FEC: (n=64800, k=32400) rate 1/2 code, with QPSK
modulation scheme is considered as target for FPGA
implementation. The architecture in this design efficiently uses
pipeline technique along with parallel processing to optimize the
hardware resources and overall latency, to accomplish FEC
encoding for DVB S2 system. Coding is completed in Verilog HDL
with Xilinx Virtex6 XC6VLX240T FPGA as target for hardware
realization and QuestaSim simulator is used to complete the
functional simulation.
Keywords—DVB-S2, FEC, LDPC, BCH, RAM, FPGA.
I. INTRODUCTION
Advanced satellite communication technology necessitates
proficient encoding technique to operate on high data rates, and
to achieve best signal transmission performance. Digital Video
Broadcasting Satellite Second Generation, DVB-S2 is the 2nd
generation satellite broadcasting standard, developed by the
European Digital Video Broadcasting (DVB) project group [1].
DVB-S2 is a digital television broadcast standard that has been
designed succeeding to the well-liked DVB-S system [2].
Channel encoding method consist low density parity check
(LDPC) codes. Modulation schemes are: QPSK, 8PSK,
16APSK, and 32APSK modulations. There is a flexible
framing structure for different types of applications.
LDPC codes are advanced class of block codes have sparse
parity-check matrices that contain only a very small number of
non-zero entries. This code is used, as the inner code for FEC
encoding in DVB-S2 system [1]. LDPC codes enable high data
rate for satellite communication system. So LDPC codes are
popular in satellite applications to transfer highly efficient
information over bandwidth in the occurrence of channel noise.
The Bose-Chaudhuri-Hocquenghem (BCH) codes random error
correcting cyclic code. It has property to correct multiple
errors. In BCH codes, there is an accurate control over the
number of symbol errors correctable by the particular code [3].
In DVB-S2 system, FEC Encoder consists of an outer BCH
code and inner LDPC code. This contains two kinds of code
length and 11 types of code rate. The defined, 11 different code
rates for LDPC codes are 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5,
5/6, 8/9 and 9/10. The normal frame length is of 64800 and the
short frame length is 16200 respectively. We have targeted to
implement FEC Encoder of DVB-S2, BCH code & LDPC code
followed by bit mapping to QPSK constellation in Xilinx
FPGA, to realize the system with efficient use of inbuilt
memories of FPGA.
978-1-7281-1380-7/19/$31.00 ©2019 IEEE
We have used ROM in FPGA, to store parity address
matrices for reading continuously throughout the operation at
specific intervals. Flexibility is incorporated in the design by
using, the read and write properties of RAM [5], to generate
LDPC parity bits as per requirement. For proof of concept
(POC) of the system we have targeted 64800bits code length
and 1/2 code rate normal frame LDPC code and bit mapping
for QPSK constellation. BCH code is the outer code followed
by LDPC as inner code in the design of FEC encoder for DVB
S2 system.
This paper is divided to further six sections as follows.
Section II gives the basic architecture of DVB S2 System along
with the brief description of major functional units followed by
details of FEC Encoder in DVB-S2 system. Section III
discusses the FPGA based implementation of BCH Encoder
used as outer code in FEC Encoder. Section IV illustrates the
design and generation of LDPC code in FPGA as inner code for
FEC Encoder which takes BCH coded data as input for further
processing. Section V gives the bit mapping of LDPC codes for
QPSK constellation. Section VI gives the conclusion about the
design and implementation.
II. BASIC ARCHITECTURE OF DVB S2 SYSTEM
Input
Stream
MODE
ADAPTATION
STREAM
ADAPTATION
Functional
Blocks
DVB-S2
FEC
ENCODING
MAPPING
PL
FRAMING
MODULATION
To RF
BASE BAND FRAME FEC FRAME
Fig. 1: Functional Modules of DVB S2 System
The functional units of DVB-S2 are shown in figure 1 as
above. These modules are described as below [1]. Mode
adaptation unit provides interfacing for input stream to the
system. Stream adaptation module provides padding to
complete a Base-Band Frame and Base-Band Scrambling.
Number bits per frame are defined by the system for various
applications.
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 2019 6th International Conference on Signal Processing and Integrated Networks (SPIN)
FEC Encoding is accomplished by the concatenation of BCH
as outer codes and LDPC as inner codes. This is followed by
interleaving of LDPC coded data. Bit Mapping into
constellations for QPSK, and other modulations is applied, as
per the required application. Physical layer framing followed
by Base-Band Filtering and Quadrature Modulation generates
the RF signal from the system.
Figure 2 illustrates the FEC Encoder for DVB-S2 system
which consists of three major functional modules. These are
BCH encoder as outer code, LDPC Encoder as inner code
followed by a block Interleaver. The encoded output from FEC
Encoder is provided to bitmapper for bit mapping to
constellation depending on the type of modulation.
BCH LDPC INTER
ENCODER ENCODER LEAVER
FEC ENCODER
BASE BAND FRAME FEC FRAME
Fig. 2: FEC Encoder for DVB S2 standard
The FEC encoder module does BCH coding as outer code,
followed by inner LDPC Coding and interleaving of coded bits.
As shown in figure 3 below, the input stream called as
Baseband frames (BBFRAME) and the output stream is named
as FECFRAMEs. Each BBFRAME (Kbch bits) shall be
processed by the FEC coding subsystem, to generate a
FECFRAME, nldpc bits. The parameters for each stage of
encoder are defined in DVB-S2 standard [1].
Nbch = Kldpc
Kbch Nbch-Kbch
BBFRAME BCHFEC
nldpc bits
Fig. 3: Data stream Format in BCH & LDPC Encoding
The parity check bits known as BCHFEC of the BCH outer
code are added at the end of each BBFRAME, and the parity
check bits called as LDPCFEC of the inner LDPC encoder are
be appended after the BCHFEC data. Figure 3 illustrates the
fields for insertion of parity bits of each code and the total
framing structure after coding.
The parameters of FEC encoding for DVB-S2 system for
normal FECFRAME (nldpc = 64 800 bits) with Rate ½ LDPC
is given in DVB-S2 standard given Ref [1]. This is considered
for FPGA implementation in this paper.
III. FPGA DESIGN FOR BCH ENCODER
The design of BCH code for FEC encoder in DVB-S2 is
shown in Figure 4 as below. As given in figure this module
consists of a type of linear feedback shift register (LFSR) of
192 bit where the final BCH parity bits are generated for each
frame.
BIT
MAPPER
TO
CONSTELLATION
P0 P1 P2 P190 P191
BB FRAME serial input for parity calculation
32208 bits
Fig. 4: FPGA Design for BCH Encoder
The parameters for BCH code for nldpc = 64800 are
mentioned in Table 1 as per Ref [1]. The first t polynomials in
Table 1 are multiplied to generate polynomial of the t error
correcting BCH encoder. All the polynomials given in Table 1
are multiplied in our design to achieve error correction as 12 as
mentioned in Ref [1]. BCH Encoding of k information bits is
nldpc-Kldpc obtained passing the total information bits serially through the
LFSR with number of flip-flops equal to the number of parity
bits in the code.
LDPCFEC
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 2019 6th International Conference on Signal Processing and Integrated Networks (SPIN)
As shown in the Figure 4, the parity bits in BCH code here is
192. So the output of BCH code will be 32400 bits for 32208
numbers of inputs bits in frame. The taps are chosen as per the
desired polynomial. The functional simulation of BCH code in
FEC DVB-S2 is shown in Figure 5. The BCH code targeted for
Xilinx FPGA is written Verilog HDL and simulation is
accomplished in QuestaSim simulator.
Table1: BCH Polynomials for nldpc= 64800
Fig. 5: Functional Simulation for BCH encoder
IV. DESIGN OF LDPC ENCODER IN FPGA
LDPC codes can be represented by a tanner graph [4]. A
LDPC code is shown by a bipartite graph, in which N variable
nodes and M check nodes corresponds to the code word and the
parity check constraints of M×N parity check matrix H
respectively. Edge presents a non-zero entry in the matrix H as
shown in Figure 6.
Fig. 6: Tanner graph for LDPC code
A (n, k) LDPC is a linear block code, in which n-bits
corresponds to codeword bits and p (= ník) is the number of
80
Parity bits. LDPC encoder processes an input block of size,
kldpc on to a code word of size nldpc.
Information bits kldpc , i = (i0 , i1…. ikldpc-1).
Code word nldpc= (i0 , i1…. ikldpc-1, p0 , p1…. pnldpc-kldpc-1).
While encoding of each data frame, the information (I) bits
are repeated and generally distributed to a set of accumulators.
Each accumulator is used to generate a parity symbol as shown
in Figure 7. The single copy of original information is provided
with the parity bits (P) to constitute the code symbols [4].
I
P
Fig. 7: Parity bit generation in LDPC
The location of ones in leading columns of each group in
matrix A for each code rate & frame type pair is defined by
DVB-S2 standard. Using these specification the number of
Information node groups & there weights can be found for
LDPC parity bits generation. In this case for normal frame
(N=64800) & rate 1/2 first 36 IN groups have weight 8 & next
54 IN groups have weight 3.This information of leading
columns are mapped into row & shift parameters required for
desired encoding is as per the formula specified by DVB-S2
standard in [1]. In this design kldpc = 32400, and nldpc = 64800.
By processing 32400 BCH coded bits 32400 LDPC parity bits
are genertaed. Before calculation of parity bits all the bits in
parity buffer are initialized to value zero. Each information bit
is accumulated in parity buffer as per the address in parity bit
accumulator specified by the Encoder parameters [1]. Once all
the information bits are processed, then following operation is
performed on the parity bits, pi = pi xor pi-1, i = 1, 2,
……… nldpc-kldpc-1.The final content in the parity buffer
gives the parity bits for the LDPC codeword.
Figure 8 illustrates the block diagram with functional
modules for design of LDPC Encoder for DVB-S2 in FPGA.
The parity bit accumulator addresses are generated in
MATLAB by writing code for the formula defined by DVB-S2
standard and theses addresses are stored in ROM in FPGA.
BCH coded bits are stored in RAM which are read serially to
give input to LDPC parity calculation. 1st 32400 coded outputs
of LDPC is same as BCH code output 32400 bits. 2nd 32400
bits of LDPC code are the parity bits calculated throughout the
process of encoding. For each input information bit to LDPC
encoder, the desired parity bit accumulator addresses are
retrieved from ROM and the parity bit accumulation takes
place in RAM.
 2019 6th International Conference on Signal Processing and Integrated Networks (SPIN)

V. BIT MAPPER CONSTELLATION

Address Encoder
LDPC Parity Address Each normal 64800 bits FECFRAME is serial-to-parallel
RAM
Generation
( ROM)
Parameters Generation
LDPC ( RAM)
converted depending on the type of modulation. Parallel factor
ROM
32400 bits
for QPSK modulation (ȘMOD) is two. (I, Q) sequence of
variable length is generated from each parallel sequence
depending on the parallelism factor ȘMOD. The input stream is
BCH Coded called a FECFRAME, the output stream is called as a
Parity
RAM
Generation/
LDPC coded bit XFECFRAME (compleX FECFRAME), consists of
Control
Logic 32400 bits
Data Shifting
64800/ȘMOD modulation symbols. Each generated modulation
for symbol is a complex vector in the format (I,Q). Two bits of
operations
FECFRAME are mapped to one QPSK symbol. Bit mapping
Address into the QPSK constellation in FPGA shall follow figure 10.
Generation
(BCH RAM )

Fig.8: LDPC Encoder design in FPGA
The functional modules in encoder operate as in a parallel
architecture. Pipelining technology is also adopted in the design
to improve the coding efficiency. The parity bit accumulator
addresses are divided in to several groups in ROM to utilize the
full parallel architecture for encoding. Memory related
operations are performed in ping pong technique to maintain
continuous processing of the input BBFRAMEs. Control logic
is implemented in the design to maintain the sequence of
operations in the total logic block modules synchronized with
each other. Both pipelining & parallel processing techniques
are incorporated in the design to meet the timing specifications
and increase the throughput.
QPSK I
LDPC coded bit Bit Mapping
To
Constellation
QPSK Q
Fig. 10: Bit Mapping to QPSK Constellation
VI. CONCLUSION
FEC Encoder consists of BCH code & LDPC code, for
DVB-S2 system is realized using Xilinx Virtex 6 FPGA in this
paper. This consists of BCH code as outer code and LDPC
code as inner code followed by bit mapping for QPSK
constellation. Code length of 64800bits and 1/2 code rate
normal frame LDPC code is considered for FPGA
implementation. The design is processed at a clock @ 122MHz
meeting the timing specifications requirements. Parallel
processing and pipeline technology are efficiently applied in
the design along with the use of multiple RAM in FPGA to
improve the coding efficiency.

REFERENCES

[1]
Fig.9: Functional simulation of LDPC encoder in FPGA
Figure 9 gives the functional simulation result of LDPC
Encoder DVB-S2 accomplished in QuestaSim simulator. The [2]
LDPC code is written in Verilog HDL for Xilinx FPGA and
simulation is accomplished in QuestaSim simulator. Dummy [3]
BBFRAMEs are provided through Verilog test bench to the [4]
FEC encoder to accomplish the complete end to end simulation [5]
of FEC encoder including BCH & LDPC code. Control logic is
implemented in the design to generate all the memory
addresses and maintain all the sequence of operations.
Final Draft ETSI EN 302 307 V1.2.1 (2009-04). European Standards
(Telecommunications series). Digital Video Broadcasting (DVB);
Second generation framing structure, channel coding and modulation
systems for broadcasting, Interactive Services, News Gathering and
Other Broadband Satellite Applications (DVB-S2).
A. Morello, et. al “DVB-S2: The Second Generation Standard for
Satellite Broad-Band Services,” Proceedings of IEEE, Vol: 94, Issue: 1,
Jan. 2006.
https://en.wikipedia.org/wiki/BCH_code.
https://en.wikipedia.org/wiki/Low-density_parity-check_code.
Datasheet, LogiCORE IP Block Memory
Generator,https://www.xilinx.com/support/documentation/ip_document
ation.

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