Altera. Direct Sequence Spread Spectrum (DSSS) Modem Reference Design. 2010

Direct Sequence Spread
Spectrum (DSSS) Modem

Reference Design
April 2003, ver. 2.0 Application Note 289
Introduction Much of the signal processing performed in modern wireless

communications systems takes place in the digital domain. Given the
increasing processing demands, the parallel processing capabilities of
Altera® programmable logic devices makes them an attractive technology
for baseband/intermediate frequency (IF) digital signal processing (DSP)
applications.
The Altera Stratix™ device family—with its dedicated DSP blocks,

TriMatrix™ memory, and on-chip PLLs—is particulary well-suited for the
demands of communications signal processing functions. In addition, by
combining the use of Altera parameterizable DSP cores and Stratix
devices, complex high performance DSP designs can be implemented in a
relatively short period of time. For digital modulator/demodulator
applications, Altera provides a direct sequence spread spectrum (DSSS)
reference design for use as either a design starting point or an
experimental platform.
The DSSS reference design implements a DSSS digital modem that

modulates direct sequence spread data onto an IF carrier. The modulated
data is input to a channel model and passed to a digital receiver, which
demodulates and recovers the data from the received IF signal (see
Figure 1). The DSSS reference design is implemented using a combination
of Altera intellectual property DSP megafunctions, the Altera library of
parameterizable modules (LPMs), and custom logic. The targeted device
on the Stratix EP1S25 DSP development board is the Altera
EP1S25F780C5. The targeted device on the Stratix EP1S80 DSP
development board is the Altera EP1S80F956C6.
f Refer to Stratix EP1S25 DSP Development Board Data Sheet for more
information on the Stratix EP1S25 DSP development board. Refer to
Stratix EP1S80 DSP Development Board Data Sheet for more information on
the Stratix EP1S80 DSP development board.
The DSSS modem reference design requires the following software:
■ Quartus II software, version 2.2

■ FIR Compiler MegaCore function, version 2.6.2
■ IIR Compiler MegaCore function, version 1.3.3
■ NCO Compiler MegaCore function, version 2.0.3
■ ModelSim PE or ModelSim SE software version 5.6 or higher
(optional)
Altera Corporation 1
AN 289-2.0
Direct Sequence Spread Spectrum (DSSS) Modem Reference Design
Figure 1. DSSS Modem
DCH0 DCH0
DCH1 DCH1
DCH2 DCH2
DSSS Channel DSSS
DCH3 DCH3
Modulator Model Demodulator
DCH4 DCH4
PCH PCH
Features
The DSSS modem reference design provides the following features:
■ Five independent data channels spread to 3.84 Mcps

■ Three-stage FIR interpolation-by-32
■ Root-raise cosine pulse shaping with 22% excess bandwidth
■ 112 dB SFDR 15.36 MHz quadrature carriers
■ 122.88 MSPS transmitter output with 5 MHz bandwidth and over
78-dB out-of-band rejection
■ Automatic gain control (AGC) compensating for channel attenuation
of up to 30 dB
■ Costas Loop carrier recovery
■ 4× Oversampling code synchronization
This application note discusses the implementation of the DSSS modem,

including:
■ DSSS modulator
■ Channel model
■ DSSS demodulator
■ System simulation & analysis
■ Design walkthrough
When you install the software from the DSP Development Kit, Stratix
Edition CD-ROM, the DSSS modem reference design is installed into the
directory structure shown in Figure 2.
2 Altera Corporation
Figure 2. Installation File Directory Structure

Stratix_DSP_kit-v<version> or Stratix_DSP_pro_kit-v<version>
The Stratix_DSP_kit-v<version> directory contains the files for the EP1S25 DSP development board and the
Stratix_DSP_pro_kit-v<version> directory contains the files for the EP1S80 board.
Reference_Designs
dsss
doc
Contains the reference design documentation
Projects
Contains the ModelSim, Quartus II, and RTL source files.
ModelSim
Contains the ModelSim files.
tcl
Contains the ModelSim Tcl scripts.
testbench
Contains the simulation testbench.
Quartus
Contains the Quartus II design files.
sof
Contains the SRAM Object File (.sof) for the design.
RTL_Source
Contains the RTL source files.
Related Links
■ Third Generation Partnership Project, www.3gpp.org
■ Altera web site, www.altera.com/products/devkits/altera/kit-
dsp_stratix.html
DSSS The input to the DSSS modulator, which is typically the output of an inner
channel coding layer in the system, is a set of five independent serial data
Modulator streams (i.e., DCH0 to DCH4). Additionally, there is a pilot channel (i.e.,
PCH), which consists of a known repeating pattern, and a synchronization
channel (i.e., SCH). The demodulated pilot stream in the receiver is
checked against a local pilot stream copy to determine if I-Q switching or
inversion occurs, while the information contained in SCH is used to
accomplish code synchronization in the receiver.
The modulator consists of a channelization section achieved by

orthogonal code spreading, a synchronization channel spreader, a 3-stage
FIR-based interpolator, a numerically controlled oscillator (NCO), and
mixer circuit to translate the filtered data stream from baseband up to the
intermediate frequency of 15.36 MHz. The resulting modulated signal is
required to have a bandwidth of 5 MHz with an adjacent channel rejection
of 78 dB outside the band. See Figure 3.
Figure 3. DSSS Modulator

DCH0
Cch,16,0 FIR3
RRC
Re{}
25-Tap
Σ
FIR Filter
DCH1 Interpolation x4
Ex BW: 22%
Cch,16,1 gi
K
DCH2
sin(wn)
FIR1 FIR2 NCO IF signal
Cch,16,2 LPF LPF Frequency
Length 256 2-Channel 2-Channel Resolution: 0.03Hz
SCH Gold Code 87-Tap 47-Tap SFDR: 112dB
Spreader FIR Filter FIR Filter
Interpolation Interpolation cos(wn)
x2 x4
Carrier Phase
Increment
DCH3
FIR3
Cch,16,8 RRC
gq 25-Tap
FIR Filter
Σ
Im{} Interpolation x4
DCH4 Ex BW: 22%
Cch,16,9
K
PCH
Cch,16,10
Orthogonal Variable Spreading Factor (OVSF) Code

Channelization
Each input data stream (DCHi) and the pilot channel (PCH) is spread by
channelization codes (cch,SF,i) where the spreading factor (SF) in the Altera
DSSS reference design is fixed to a value of 16. The channelization code
matrix is generated according to the following method as defined in the
3rd Generation Partnership Project (3GPP) TS 25.213 Technical
Specification:
C ch ,1 = 1
C ch ,1 C ch ,1
C ch ,2 = = 1 1
C ch ,1 – C ch ,1 1 –1
C ch ,n ⁄ 2 C ch ,n ⁄ 2
C ch ,n =
C ch ,n ⁄ 2 –C ch ,n ⁄ 2
The codes cch,16,i are then selected by row from the recursively-generated
Hadamard Matrix Cch,16 of dimension 16. Table 1 indicates the codes
selected for each of the channels.
Table 1. Channel Codes
Channel Code
DCH0 cch,16,0
DCH1 cch,16,1
DCH2 cch,16,2
DCH3 cch,16,8
DCH4 cch,16,9
PCH cch,16,10
Data channels DCH0, DCH1, and DCH2 are combined via addition to form
the I-component data. Data channels DCH3, DCH4, and the pilot channel,
PCH, are added to form the Q-component data. Prior to addition with the
complex Gold Code, the sequences are scaled by a non-linear factor K to
balance the signal level of the spread data amplitude relative to the
synchronization channel amplitude level. This ensures that both the
synchronization channel and data channels are decipherable in the
receiver.
Gold Code Generation
In 3G wireless modems, synchronization of the user equipment (UE) to

the base transceiver station (BTS) is usually accomplished by a
combination of information contained in message preambles and higher
level functions. 3G synchronization also involves the use of specific
synchronization channels in order to synchronize source and destination
prior to transmission. To emulate the receiver’s synchronization to the
transmitter at a low level, a length-256 complex Gold Code is used to form
a synchronization channel that the receiver uses to attain code
synchronization.
Gold Codes have excellent auto-correlative properties, and thus provide a

robust means of detecting the temporal offset between the expected data
sequence phase and the actual data received phase. Gold Codes are
formed by the addition (modulo 2) of two m-sequences. M-sequences are
balanced binary pesuedo-random sequences with equal
run-length-distributions of ones and zeros. To generate length-256
m-sequences, an 8-bit LSFR is used with particular feedback tap
connections, chosen from a set of allowable configurations. The complex
valued sequence gi + jgq, is generated by spreading the fixed sequence 1+j
with the generated Gold Code gci + jgcq. Figure 4 shows the
implementation of the complex spreading.
Figure 4. Synchronization Channel Generator
m-sequence 1
gci
gi
m-sequence 2
m-sequence 3
gcq
gq
m-sequence 4
Figure 5 shows the auto-correlation functions of Gold Codes gci and gcq.
Figure 5. Auto-Correlation Function of Gold Codes
Pulse-Shape Filtering and Interpolation

The 3.84 million samples per second (MSPS) spread sequences are
required to be up-sampled to 122.88 MSPS, a factor of 32. To perform the
interpolation, three FIR filter stages are cascaded together (see Figure 3).
Each filter was designed using the Altera FIR Compiler.
f Refer to FIR Compiler MegaCore® Function User Guide, for more information
on generating FIR filters customized for Altera devices.
The first filter stage is a 47-tap, half-band, low-pass filter designed with a
Hanning window. Figure 6 (FIR filter #1) shows the magnitude of the FIR
filter’s frequency response over the full bandwidth of the system.
1 To show the constituent effect of each of the filters in the multi-

rate, multi-stage interpolator, all reponses in Figure 6 are plotted
with respect to the Nyquist frequency of the modulator output of
61.44 MHz.
Figure 6. Frequency Response of FIR Filters
The filter has an input resolution of four bits and thus, a two-channel, fully
serial implementation is chosen, yielding a very efficient FIR filter in terms
of device resource usage. The I and Q channels are first multiplexed into
a single sample stream of 7.68 MSPS. The serial filter is clocked at
30.72 MHz and yields an up-sampled interpolated data, time-division
multiplexed stream of 15.36 MSPS at its output.
The second filter stage is an interpolation-by-four filter designed with a

Blackman window. Figure 6 (FIR filter #2) shows its frequency response.
The second filter is a 67-tap, low-pass filter with high (>80 dB) stop-band
rejection. The second filter’s input is the output of the first stage FIR filter
truncated to 16 bits. The coefficient resolution is also 16 bits. Due to the
higher input data rates and the relatively high input resolution required,
a muli-bit-serial FIR filter structure utilizing two serial units is selected
from within the FIR Compiler MegaWizard® Plug-In, see Figure 7. The
15.36 MSPS TDM input is up-sampled to a rate of 61.44 MSPS, with the
filter being clocked at 122.88 MHz.
Figure 7. FIR Filter Compiler Architecture Page Settings for FIR Filter Stage Two
The third and final filter stage is a root-raised cosine, pulse-shaping filter
with an interpolation factor of four. The third filter has 25-taps and its
input is the output of the second stage FIR filter truncated to 16 bits. The
coefficients are also 16 bits. Figure 6 (FIR filter #3) shows the frequency
response of the third FIR filter. The input stream is demultiplexed into the
individual I- and Q-channels, each with a sample rate of 30.72 MSPS. Each
channel is filtered by an individual filter clocked at 122.88 MHz to yield
the final 122.88 MSPS data streams to be modulated onto the IF carrier.
Because of the relatively higher input data rates, a multi-bit serial
architecture with four serial units is selected from within the FIR
Compiler wizard.
Figure 6 (Convolved Transmit Spectral Mask) shows the overall transmit

spectral mask of the 3-stage interpolator. The plot was generated by a
convolution of the individual FIR filter reponses.
Modulator NCO
An NCO is used to translate the base-band data up to an IF of 15.36 MHz.

Table 2 lists the required NCO specifications. Figure 8 shows the NCO
parameters.
Table 2. Required NCO Specifications
Specification Requirement
Output Frequency 15.36 MHz
Frequency Resolution 0.03 Hz
Spurious Free Dynamic Range 110 dB
Output Sample Rate 122.88 MSPS
The NCO was designed using the Altera NCO Compiler MegaCore
function. Figure 8 shows a screenshot of the NCO parameterization.
Figure 8. Modulator NCO Parameterization
Because the architecture is very efficient for the NCO’s high SFDR and
relatively high-performance requirements, a multiplier-based NCO is
selected in the MegaWizard. This architecture uses the Stratix device’s
DSP blocks to efficiently reduce the memory requirements for such a
highly-precise oscillator. Phase dithering is also employed to reduce the
harmonic spurs inherent in the fixed precision implementation of NCOs.
To achieve the optimum dithering level for the chosen architecture and
clock-to-output frequency ratio, the NCO Compiler allows you to tune the
dither level and observe the effects immediately in graphical
representation of the spectrum, as Figure 8 shows. The required phase
accumulator precision is deduced from the specification of the frequency
resolution.
Required resolution = log2 (fclk/fres) bits
Rounded to the nearest integer and substituting 122.88 x 106 and 0.03 for
fCLK and fRES, respectively, the required resolution of the phase
accumulator is 32 bits. Utilizing the spectral SFDR plot in the NCO
Compiler wizard, the following is required to meet the specification:
■ An angular precision of 18 bits

■ A dithering level of five
■ An output precision of 18 bits
Figure 9 shows a spectral plot of the NCO sine output.
Figure 9. Spectral Plot of NCO Sine Output
Mixer & Quadrature Combiner
To modulate the 122.88 MSPS pulse-shaped I and Q components onto the

generated sinusoidal carriers, the stage-three filter outputs are truncated
to 18 bits and multiplied with the quadrature outputs from the NCO. The
dedicated multiplier circuitry of the Stratix device family is used to
efficiently perform the mixing operation. The modulated outputs are
combined by addition before being sent to the channel model.
Modulator Design File Summary List

Table 3 lists the modulator design files.
Table 3. Modulator Design File List
Design Entity Description Function

dsss_modulator.vhd Top-level modulator entity Instantiates all DSSS modulator sub-entities
spreader.vhd DS spreader Spreads input data and pilot sequences
sequences_add_lut Add and scale Scales spread data channels and add Gold
Code spread synchronization channel
fir_st1_mux Multiplexer TDM I and Q channel data for stage one FIR
filter
fir_mod_2.vhd 2-channel interpolating by 2 FIR filters Interpolation by 2
fir_st1_demux De-multiplexer Demultiplexer TDM output of stage one FIR
filter
fir_st2_mux Multiplexer TDM I and Q channel data for stage two FIR
filter
fir_mod_4.vhd 2-channel interpolating by 4 FIR filters Interpolation by 4
fir_st2_demux De-multiplexer Demultiplex TDM output of stage two FIR
filter
fir_mod_4rrc Interpolating-by-4 RRC filter Interpolation by 4 RRC pulse shaping
delay_i_channel.vhd FIFO buffer Realigns I- and Q-components in time
nco_str_mod Numerically Controlled Oscillator Quadrature IF carrier generation
mult.vhd Stratix dedicated multiplier Modulator mixer
iqadd.vhd Adder Adds I- and Q-channel data to and from IF
signals
Channel Model The channel model is designed to exercise the symbol and carrier recovery
circuitry, AGC loop, and despreading code synchronization portions of
the receiver.
The channel output spectral response can be represented by the following

equation:
Y ( jω ) = X ( j ω ) H ( j ω ) + N ( j ω )
Where, H ( j ω ) = α e – j ω r and N j ω is the frequency domain

representation of the additive noise sequence, v(n).
Figure 10 shows the channel model.
Figure 10. Channel Model
x(n) z−r y(n)
α(n) v(n)
The attenuation α is a user-specifiable attenuation factor and r represents

a channel phase offset unknown a priori by the receiver. The noise
sequence v(n) is generated using a 16-bit linear feedback shift register
(LFSR). See “System Simulation & Analysis” on page 28 and “Hardware
Verification on the Stratix EP1S25 or EP1S80 DSP Development Board” on
page 38 for more information on inducing channel degradations.
Table 4 lists the channel model design entities.
Table 4. Channel Model Design Entities

channel_model RTL channel model Implements additive noise,
attentuation, and signal-nulling effects.
noise_generation Random signal Implements a 16-bit LFSR for noise
generator sequence generation.
DSSS The DSSS demodulator receives the channel-degraded signal from the IF
signal and recovers the original data transmitted. It consists of a down-
Demodulator conversion stage that is responsible for recovering the spread data from
the received modulated signal and a despreader unit, which is used to
despread the demodulated I-Q arms to render the transmitted data
streams. An AGC loop, a carrier recovery loop, and a PN synchronization
loop, work in concert with a pilot monitor and an I-Q derotation module
to maintain receiver synchronization, under channel degradations and
phase shifting. See Figure 11.
Figure 11. DSSS Demodulator
FIR
Altera RRC
31-Tap FIR Filter
8 pn_lock
Excess BW: 22%
Gold Code
Fixed Rate Peak max_index
Correlator
Detector
From IF 4x
NCO Oversampling
Frequency Carrier
AGC Recovery
Resolution: 0.03Hz Data
Channel
SFDR: 112dB Loop Outputs
1. . 5
Free-Running
Phase Increment
I-Q
Buffer Hadamard
Derotate
Despreader
FIR
Altera RRC 8
31-Tap FIR Filter

Pilot
Excess BW: 22% Output
Fixed Rate
Pilot Monitor
Automatic Gain Control (AGC)
To compensate for possible attenuation of the transmitted channel signal,

an AGC loop is implemented. The AGC circuit tracks the power level of
the received signal and applies a gain if the level is deemed to be outside
the range in which the receiver is able to demodulate the data correctly.
Figure 12 shows the AGC circuit. The AGC loop should be a slowly-
tracking loop, and not provide gain based on rapid fluctuations in the
received signal x[n]. The input is down-sampled by a factor of eight, and
then the down-sampled data is squared to yield a short-term power
estimate of the received signal.
Figure 12. AGC Circuit

Gain-Adjusted Output y[n]
Demodulator Input x(n) 8 ( )2

IIR IIR
Order 2 Order 1
K[n]
Dead-Bander
w[n]
Up/Down g[n]
Counter Gain
LUT
The loop filter is implemented as a cascade of two IIR filters, and both
filters are designed using the Altera IIR Compiler. The Altera IIR
Compiler allows you to analyze the floating-to-fixed point conversion of
coefficients and the widths and slices of interest of the feed-forward and
feedback paths in addition to saturation and rounding effects. Figure 13
shows a screenshot indicating these settings in the design of the first order
stage.
Figure 13. Altera IIR Compiler
The first filter stage is a second order low-pass filter, and the second stage
is a first order low-pass filter. The combined third order overall response
has a sufficiently narrow bandwidth to yield a long-term power level
estimate ensuring that rapid fluctuations in the received signal do not
cause a large shift in the applied gain. The magnitude response of the
overall AGC Loop filter is shown in Figure 14, which is generated by
multiplying the constituent responses of the two IIR filters and not taking
fixed-point quantization effects into account.
Figure 14. Overal AGC Loop Filter Response
A dead-band is applied to the loop filter output, which has the effect of
limiting the control signal’s swing to the up/down counter, preventing
oscillation of the loop. The deadband is chosen to be wide enough so in
the event that the deduced signal level of x(n) is not exactly at the
optimum point—but close enough to allow for correct demodulation—the
gain level is held constant.
The up/down counter scales the incoming signal in the opposite direction
of its deficit with respect to the optimum received signal level. Presented
with an attenuated input signal, the AGC loop recognizes that the
received signal level is below the optimum level. The deficit causes the
counter to increment, which applies increasing gain until the loop filter
output is once again within the dead-band region. If the loop filter output
signal level is forced above the dead-band region by the applied gain, the
counter decrements, which decreases the applied gain until the output is
again within the range where correct demodulation of the received signal
can occur.
The dead-bander outputs two control signals to the up/down counter:
■ Directional indicator, w[n]

■ AGC Loop gain accelerator, g[n]
The directional indicator control signal, w[n], indicates to the counter if

the received (filtered) signal level is below, within, or above the dead-
band (optimum) region. And, thus, if the required response is to
increment, hold, or decrement the value of the counter.
The loop gain accelerator control signal, g[n], is a non-linear function of

the filtered signal level. Given very low or very high estimated input
signal power levels, the increment and decrement values are scaled to
reduce the pull-in time required to increase/decrease the output gain,
k[n]—from its initial value to the point where the signal-scaling result
once again brings the estimated power level to within the dead-band
region. The acceleration is non-linear to prevent loop oscillation as the
optimum operation point is reached. As the signal level approaches the
optimum level range, the acceleration of the gain adjustment is reduced,
ensuring the overall stability of the loop. Figure 15 shows the relationship
between the gain acceleration g[n] and the normalized, estimated signal
power level.
Figure 15. Gain Acceleration Vs. Estimated Signal Power Level
Demodulator NCO & Mixer Circuitry
The demodulator NCO—which was designed with the Altera NCO

Compiler—has the same parameters as the modulator NCO, except that
the demodulator NCO has an additional input port that allows for
frequency modulation of the output carrier. The additional input port
feeds a built-in frequency modulator in the NCO, and is required so that
the output frequency can be varied about the free-running frequency
according to the output from the Costas Loop, as described in the “Carrier
Recovery Loop” section. The 18-bit precision 15.36 MHz quadrature
sinusoids are multiplied with the 122.88 MSPS incoming gain-adjusted
signal. The Stratix device’s dedicated multiplier circuitry is utilized to
perfom the mixing of the modulated signal with the NCO output.
Carrier Recovery Loop

A Costas Loop has been implemented to track and compensate for phase
and small frequency offsets between the demodulating carriers generated
in the receiver, and carriers generated in the modulator. Phase offsets
occur as a result of the misalignment in time of the received signal with
the carriers. Frequency offsets—between the two sets of carriers—can
occur for many reasons, including—but not limited to—clock frequency
discrepancies between the receiver and the transmitter NCOs or Doppler
shifts due to the motion of the receiver relative to the transmitter. The
Costas Loop tracks the phase offset ∆φ between the modulator and
demodulator quadrature carriers by computing a phase difference term
between the demodulated I and Q arms. Given demodulated values i[n]
and q[n], the phase difference Ψ d[n] is calculated by the following
equation:
Ψ d[n] = i[n]* sq[n] -q[n]* si[n]
Where si[n] and sq[n] are the signs of i[n] and q[n] respectively. The result
is low-pass filtered to remove higher order terms, which leaves a term
proportional to sin ( ∆φ ). The loop filter in Figure 16 is a second-order IIR
low-pass filter, designed using the Altera IIR Compiler. The filtered phase
difference is input to the frequency modulation input of the demodulator
NCO, varying its output frequency about its free-running frequency and
forcing ∆φ towards zero.
Figure 16. Costas Loop Carrier Recovery

i[n]
8
LPF
s [n]
i
From AGC Sign-detect
Loop
NCO Filter
sq [n]
Free-Running
Phase Increment Sign-detect
8
LPF q[n]
There exists an n π /2 radian ambiguity in the output detected phase

offset, ∆φ from the loop filter, i.e., the carrier recover loop may cause the
demodulator carriers to be offset in phase from the modulator carriers by
0 ° , 90 ° , 180 ° , or 270 ° . This ambiquity is resolved through the use of a
pilot channel monitor in conjunction with the I-Q derotator. Refer to “Pilot
Monitor” on page 26 and “I-Q Derotation” on page 27.
Low Pass Filter
To filter out higher order terms resulting from the mixing process, a pair
of root-raised, cosine filters is implemented on each of the I-Q arms,
following the demodulation multipliers. The root-raised cosine window
of the filter also provides an overall raised cosine response to the
transmitted pulse. The filters each have 31-taps, 8-bit input resolution and
9-bit coefficients with an excess bandwidth of 22%. The filters are
designed with the Altera FIR Compiler. Because of the relatively high
input data rates of 122.88 MSPS to the filters, a parallel architecture is
used. The filters are clocked at the sample rate and output is decimated by
a factor of 8 to bring the sample rate down to 4× the chip rate or 15.36
MSPS.
Gold Code Correlator

The decimated demodulated sequence is correlated against a local copy
of the complex Gold Code (cg = cgi + jcgq) where each bit of cg is repeated
four times in succession to account for the oversampling occurring in the
input sequence. The output of the correlator yields an estimation (i.e., to a
granularity of a ¼ chip interval) of the phase offset between the transmit-
ter and receiver. The 15.36 MSPS demodulated complex I-Q symbol
streams [n], are oversampled by a factor of four relative to the chip rate of
3.84 MSPS providing a processing gain of 4, where s[n] = i[n] + jq[n]. The
complex correlation is defined as:
1023
R sc [ k ] = ∑ s [ n ]cg∗ [ n – k ]
n=0
1023
= ∑ ( i [ n ] + jq [ n ] ) ( cgi [ n – k ] – jcgq [ n – k ] )
n=0
  1023  1023

 
=   ∑  i [ n ]c gi [ n – k ] + ∑ q [ n ]c gq [ n – k ]  +
 
n = 0 n=0 
 1023 1023 
 
j  ∑ i [ n ]c gq [ n – k ] – ∑ q [ n ]c gi [ n – k ] 
 
n = 0 n=0 
= ( R sci [ k ] + jR scq [ k ] )
It can be seen from the complex correlation equation that there are four
distinct correlation operations that must be performed. However, it
should also be noted that the real and imaginary parts are each required
to be correlated against the real and imaginary parts of the complex code.
The four continuous correlations can therefore be implemented as two
separate FIR filtering operations, one with a coefficient set consisting of
the values of cgi[n], while the other with a coefficient set consisting of
values of cgq [n]. The input values are alternatively taken from the input
streams i[n] and q[n], four samples at a time and multiplexed.
Because there are only 256 distinct values in each code, these filters can be
implemented very efficiently in a multi-channel FIR structure. Each group
of four over-sampled input data points is required to be multiplied by the
same coefficient value, so each oversampling phase of the input data is
assigned to an individual channel. Given that the input data is
oversampled by a factor of four and both quadrature arm components
(i.e., i[n] and q[n]) are required to be processed by each coefficient set, two
256-tap, 8-channel filters are required to compute the 1024 complex over-
sampling correlation lag results. The four TDM results from the filters for
each quadrature component are required to be added every four cycles
before being combined as per the complex correlation equation, which
yields the multiplexed lag outputs, Rsci and Rscq corresponding to the
1024 input samples of i[n] and q[n]. Figure 17 shows the implementation
of the complex correlation.
Figure 17. Implentation of the Complex Correlation
<i,ci> phases 0,1,2,3
D Q
i[n]
(i[n],q[n]) 8-channel Rsci[k]
256 Tap FIR
Coefficient Set Ci D Q
<q,ci> phases 0,1,2,3
<q,cq> phases 0,1,2,3
D Q Rscq[k]
8-channel
q[n] 256 Tap FIR
(q[n],i[n]) Coefficient Set Cq
D Q
<i,cq> phases 0,1,2,3
The fundamental input data rate to each of the filters is the system chip
rate of 3.84 MSPS. Because there are eight channels per filter, and the input
resolution to the filters is 8-bits, a mult-bit serial architecture utilizing two
serial units is chosen from within the FIR Compiler wizard. The filters are
required to be clocked at a rate of 122.88 MHz (8 x 4 x 3.84 MSPS) to
perform the complex correlation. The real and imaginary parts, Rsci and
Rscq, are truncated to 18 bits before being passed to the peak dector to
estimate the offset in time between the transmitter and receiver.
Peak Detector
The peak-detector circuit is responsible for the computation of the lag in

time between the received modulated signal and the local copies of the
channelization codes stored for use in the Hadamard Despreader. It takes
the real and imaginary outputs Rsci , Rscq, respectively, of the Gold Code
correlator and calculates the squared complex magnitude of the correlator
output at each sample instance k, by the following equation:
|Rsc[k]|2 = R2sci[k] + R2scq [k]2
At every sample instance k, over the window of the 1,024 oversampled

outputs, the complex magnitude is successively compared to the stored
maximum over the window. If the maximum value found over the 1,024
sample window is greater than a pre-defined, constant threshold, then the
receiver is assumed to have found PN-synchronization lock. Figure 18
shows the basic operation of the peak detector.
Figure 18. Peak Detector with PN Synchronization Lock
Rsci(k) ( )2 Maximum Index Tracking
kmax
Counter
Rscq(k) ( )2
Z-1
pn_lock
max{R2sci[k]+R2scq[k]}
Threshold
The index for which the peak of the complex magnitude squared sequence
is detected corresponds directly to the lag time between the received
sequence and the local copies of the codes in the receiver. Once PN-
synchronization lock has been achieved, kmax is used to initialize the read-
side address of the buffer between the down-converter and the Hadamard
Despreader.
Hadamard Despreader
Data from the demodulator filter pairs is buffered while the code offset is
detected by the Gold Code correlator. The data is written in pairs into the
buffer, with each memory location storing the 8-bit decimated I and Q
component samples concatenated as a 16-bit word. The buffer is arranged
as a quadruple circular one, which allows demodulated I-Q data storage
beyond the latency of the Gold Code correlation calculation. The result is
to allow the storage of 4,096 I-Q pairs (i.e., 4× correlator window length)
before results are overwritten by the newly calculated outputs from the
Gold Code correlator. Figure 19 shows the Hadamard Despreader
interface’s block diagram.
Figure 19. Hadamard Despreader Interface
R sci[k]
Complex Gold
Code Correlator Peak
Output Lags Rscq[k] Detector
k
pn_lock max
Write Read
Address Address
Generator Generator
Buffer
(i[n],q[n]) Aligned (i[n],q[n]) 8-Channel

De-Rotated I & Q
Hadamard
Components
Despreader
Once the Gold Code sequence point of alignment has been detected, the I-
Q data is read from the buffer starting with the data written to the location
in memory, corresponding to the offset index, kmax . The data is passed
into an eight-channel Hadamard Despreader that implements
despreading of up to eight spread-spectrum channels. In the DSSS
reference design, because only six channels are required, two of the
channels are idle. The redundancy provides for a simple interface
between the buffer and the despreader.
The Despreader is implemented as a multi-channel, signed accumulator,

which resets itself every data symbol interval, or equivalently, every 64-
oversampled-by-4 chips. Figure 20 shows a simplified diagram of the
Hadamard Despreader operation.
Figure 20. Simplified Hadamard Despreader Operation
i
Control Code Memory
m
c [m] DCH0
i
Sign Detect DCH1
sclr DCH2
8-Channel
Idle
i[n]
d[n] Signed DCH3
Accumulator DCH4
q[n]
PCH
Idle
The I-Q data is multiplexed into a single, 8-bit data stream d[n] with
successive samples taken from I and Q component arms every four clock
cycles. Each of the oversampled phases is signed according to the bit ci[m]
prior to being accumulated, see the following equation:
63
∑ d [ n ]ci [ m ] ,m = floor  --4-

n
RHi =
n=0
Where i is the channelization code index and m is the bit index within that
channelization code. The code selection index is updated every clock
cycle, while m is updated every 32 clock cycles because each oversampled
phase should be accumulated with the same indexed sign bit for each of
the eight channels. Every 64 samples, the accumulated value RHi[n] is
passed to a one-bit slicer to detect its sign, and the accumulated value for
that channel is cleared for processing of the next data symbol. The
despreader module is clocked at a rate of 122.88 MSPS to process the eight
15.36 MSPS oversampled channels.
Pilot Monitor
The pilot monitor compares the detected-demodulated pilot sequence
with a local copy and checks for errors. Every time a new pilot bit is output
by the Hadamard Despreader and is different to that expected by the pilot
monitor an error counter is incremented. When the error count exceeds
the specified error threshold, I-Q rotation due to shifted phase lock in the
Costas Loop is assumed and a separate 2-bit rotator index counter is
incremented and output to the I-Q derotator. Figure 21 shows a simplified
block diagram illustrating the functionality.
Figure 21. Pilot Monitor

Error Counter
Detected Pilot
Rotator
Sequence
Index
Counter Counter
Local Pilot Error Threshold
I-Q Derotation
The derived rotator index is fed back into an I-Q derotator, which
effectively implements shifts in the demodulated I-Q components by
n π /2 radians, n ∈ ( 0, 1, 2, 3 ) . The rotator is implemented as a look-up
table that, based on the index, switches and/or inverts the I- and
Q-component inputs to the Hadamard Despreader. Table 5 lists the
demodulator design files.
Table 5. Demodulator Design File Summary List (Part 1 of 2)

dsss_demodulator Top-level demodulator entity Instantiates all DSSS modulator sub-
entities
agc AGC top level Instantiates AGC sub-entities
agc_gain Multiplier AGC gain block
agc_cct AGC loop Calculates gain to be applied to
received signal
agc_sat Saturation Saturates input to AGC Loop if
required
agc_loop_IIR1.tdf First order IIR Filter Loop Filter Stage 1
agc_loop_IIR2.tdf Second order IIR Filter Loop Filter Stage 2
agc_deadbander Dead-banding circuit Generates direction and acceleration
factor for up/down counter
agc_updn_counter Counter Outputs gain to be applied to input
signal
nco_demod_str NCO Quadrature IF carrier generation with
frequecy modulation input.
costas Costas Loop circuitry Tracks phase/frequency offsets and
outputs
pll_loop_filter Second order IIR filter Filters detected phase offset
mult_d Stratix dedicated multiplier Demodulator mixer
fir_demod_str Demodulator filter Parallel RRC FIR filter
Table 5. Demodulator Design File Summary List (Part 2 of 2)

gold_corr 4X oversampling complex correlator Correlates demodulated sequences
against local copy of Gold Code
peak_detect Peak Detector Computes maximum index over
correlator lag output window
demod_2_hadamard Stratix MegaRam buffer Buffer demodulated streams to be
read out from deduced offset
hadamard_mux Multiplexer Multiplexes oversampled I-Q streams
to single 8-channel stream
hadamard_despreader_8ch_syn Hadamard Despreader 8-channel Hadamard Despreader
pilot monitor Pilot channel output monitor Checks for errors between despread
pilot channel and local copy
iq_derotator 90-degree phase shifter De-rotates demodulated I-Q channels
as required
System To observe the DSSS modem reference design operation under various
channel conditions, you can simulate the design using the ModelSim®
Simulation & simulation software. This section discusses DSSS modem reference design
simulation and analysis.
Analysis
DSSS Modem Simulation Testbench
The modem can be exercised via the top-level simulation DSSS modem
testbench, dsss_interface. Figure 22 shows the interface’s principle
functional units, which consist of a set of input data sources arranged
appropriately and stored as a ROM in the Stratix device’s internal
memory. The data is read from the ROM and input to the modem via the
corresponding data and pilot channel ports.
Figure 22. Excercising the DSSS Modem Reference Design in ModelSim
DSSS Channel Model
GND
β=1
Input DSSS β=0
Data Modulator
Source
Output Data
γ =0 DSSS
α=0 GND Demodulator
1
γ=1
α= 1
K
A
Clock
Generator
Noise
Generator NL
Control
Channel effects are accessible via the channel_alpha, channel_beta,

and channel_gamma DSSS modem interface signals, represented by
symbols α, β and γ respectively in Figure 22.
When channel_alpha is asserted (α = 1), the channel attenuates the

modulated input signal by a factor, KA, which is user-specified via the
ATTEN_FACTOR parameter in the channel model file (i.e.,
channel_model.vhd). When channel_beta is asserted (β = 1), the
input to the modem consists of noise only. Deassertion causes both signal
and noise components to be output from the channel. When
channel_gamma is asserted (γ = 1), a generated noise sequence is added
to the modulated signal. The noise variance, NL is adjustable via the
parameter NOISE_LEVEL in the interface.
To observe the various simulated channel effects during modem

operation, α, β, and γ can be preset to be asserted, or deasserted, at any
given time by adjusting the values of the following parameters:
■ <START/END>_ATTEN_TIME
■ <START/END>_SIGNAL_NULL_TIME
■ <START/END>_ADD_NOISE_TIME
The value of these parameters can be defined in the parameter section of

the dsss_interface.vhd located in the RTL_source subdirectory. Both the
attenuation factor KA and noise level added in the channel, NL are fixed
by the user at compile-time.
For analysis in tools such as MATLAB, data at various points in the

modem are output to text files. Table 6 gives the points in the design that
are output by default.
Table 6. Data Points Output to Text Files During Simulation
File Name Data Point Location of Text I/O Process

channel_sig.txt Channel output signal component channel_model.vhd
channel_noise.txt Channel output noise component channel_model.vhd
l_filt_demod.txt Demodulated I-channel dsss_demodulate.vhd
q_filt_demod.txt Demodulated Q-channel dsss_demodulate.vhd
costas_out.txt Costas loop output dsss_demodulate.vhd
gain_out.txt Gain applied by AGC loop dsss_demodulate.vhd
agc_out.txt Scaled received input to demodulator dsss_demodulate.vhd
Exercising the DSSS Modem Reference Design in ModelSim
To run the DSSS modem reference design in the ModelSim software,

perform the following steps:
1. Start the ModelSim software and browse to the directory <install

directory>\Stratix_DSP_Kit-v<version>\Reference_Designs\dsss\
Projects\Modelsim if you are using the Stratix EP1S25 DSP
development board or <install directory>\Stratix_DSP_pro_kit-
v<version> if you are using the Stratix EP1S80 DSP development
board.
2. Choose the top-level testbench, dsss_interface_sim.vhd, located in

the Testbench subdirectory.
3. If desired, edit the Channel Effects parameters. See “DSSS Modem

Simulation Testbench” on page 28.
4. Run the TCL script, dsss_interface.tcl, located in the modelsim\tcl

subdirectory. Running the TCL script creates your ModelSim project,
compiles all required libraries and design files, and exercises the
modem for 10 ms. The results are output to a waveform.
Additionally, various data points from the channel and demodulator
are output to text as described in Table 6.
DSSS Modem Analysis & Simulation Results

This section describes the DSSS modem reference design analysis and
simulation results.
DSSS Modulator Output Analysis
The transmitted signal is required to have a bandwidth of 5 MHz centered

on a 15.36 MHz carrier and that any out-of band content be below 78 dB.
Figure 23 shows the resulting signal spectrum when the modulated signal
is output to a text file during simulation. Superimposed in blue are the
specified modulator requirements.
Figure 23. DSSS Modulator Output Spectrum
Channel Parameterization
Table 7 lists the test simulation file’s channel parameter values:
Table 7. Channel Parameter Values
Parameter Value
ATTEN_FACTOR 18
NOISE_LEVEL 5
START_ATTEN_TIME 2000 µs
END_ATTEN_TIME 16000 µs
START_SIGNAL_NULL_TIME 6500 µs
END_SIGNAL_NULL_TIME 7500 µs
START_ADD_NOISE_TIME 1 µs
END_ADD_NOISE_TIME 16000 µs
The channel parameterization results in the flowing assertions for the

channel effect parameters α , β , and γ in Figure 23 during simulation of
the modem.
α =1 2000 < t <= 16000 µs
=0 otherwise
β =1 6500 < t <= 7500 µs
=0 otherwise
γ =1 1 < t <= 16000 µs
=0 otherwise
Demodulator Performance
Figure 24 shows the resulting channel output after channel degradations

are applied. The input to the receiver is attenuated by 18 dB after 2 ms, and
completely annihilated for an interval of 1 ms for 6,500 < t <= 7,500 µs.
Noise, of 16 dB variance, is consistently added to the signal as it passes
through the channel during the entire simulation.
Figure 24. DSSS Modem Reference Design Test Case Channel Output
Figure 25 shows a plot of the error metrices as computed by the testbench

over the duration of the simulation. The top plot in Figure 25 indicates the
errors detected in the output data of the 5 data channels (i.e., DCHi and
PCH), while the bottom plot indicates the accumulated error count. It
should be noted that the blocks of output errors detected directly
correspond to the deliberately imposed channel degradations. The
modem adjusts to the changing channel, and operates without errors
following an interval of compensation for the channel effects.
Figure 25. DSSS Modem Output Error Metrices Given Channel Degradations Previously Specified
After reset is set low, the DSSS demodulator performs its initial
acquisition of code and carrier synchronization as well as AGC gain level.
Figure 26 shows a plot of the phase offset between the modulator and
demodulator carriers against time. The Costas Loop deduces a phase
offset between the received signal and the demodulator carriers, and then
drives the demodulator output phase to lock to the received modulated
signal as shown in Figure 27. At this point, the Costas Loop continues to
track any phase and/or frequency offsets detected.
The plots in Figures 26 and 27 compare the phase offset between the
modulator and demodulator NCO sine output; thus, the plots do not
account for channel latency and the AGC loop in the modulator. Figure 25
shows that this action incurs errors in the demodulated sequence, which
is the result of the Costas Loop driving the oscillator to lock 90° out of
phase—with respect to the demodulator I-Q arms. Thus, the pilot
monitor’s error threshold is quickly exceeded, causing an I-Q rotation.
Following the I-Q rotation, full correct input data demodulation occurs
and the output of the error counter remains fixed, which implies zero new
errors. The AGC gain level applied can also be seen to settle to a deduced
optimum operation point during this interval.
Figure 26. Phase Offset Between the Modulator & Demodulator
Figure 27. Phase Offset Between Modulator & Demodulator Over Initial 1ms Interval
At t = 2000 µs, the signal input power level is reduced by 18 dB, causing
errors to occur in the demodulated output. The AGC loop immediately
begins to compensate, increasing the gain applied to the input signal up
to a normalized value of K = 7.84, at which time no further errors are
detected at the demodulator output. The attenuation of the signal in the
channel also causes a brief increase in phase offset detected by the Costas
Loop, the output of which is quickly driven again towards zero as the
AGC loop compensates for the attenuation.
Figure 28. AGC Analysis
To observe the ability of the DSSS modem to reacquire synchronization,

the signal component of the channel output is grounded after 6.5 ms.
Because only the noise component of the channel output is passed to the
demodulator (see Figure 25) over this time interval, an expected increase
in error count occurs. When the signal is reapplied 1 ms later (i.e., at t = 7.5
ms), the carrier recovery and AGC circuits work to return to their
optimum operation points (see Figures 26 through 28) while code
synchronization is reacquired.
Again, Figure 25 shows that following the re-application of a modulated

signal to the demodulator, synchronization between the demodulator and
receiver is obtained and errors are not observed in the demodulated
output sequences for the remainder of the simulation.
Hardware The DSSS modem reference design can be downloaded to the Stratix
EP1S25 or EP1S80 DSP development board for hardware verification
Verification on purposes.
the Stratix If you are using the Stratix EP1S25 DSP development board a
EP1S25 or synthesizable testbench is located in the file <install
directory>\Stratix_DSP_kit-v<version>\Reference_Designs\dsss\
EP1S80 DSP quartus\dsss_interface.vhd. If you are using the Stratix EP1S80 DSP
Development development kit a synthesizable testbench is located in the file <install
directory>\Stratix_DSP_pro_kit-v<version>\Reference_Designs\dsss\
Board quartus\dsss_interface.vhd.
The testbench includes an input data source and an instantiation of the

Stratix PLL for system clock generation and control circuitry, see
Figure 29. The testbench takes the 80 MHz output from the on-board
crystal oscillator and uses it as the reference clock input to the Stratix PLL.
A system-wide reset is connected to the push-button switch SW0 that acts
as an asynchronous reset to the Stratix PLL. The push-button switch SW0
is also used to generate a synchronous system reset via the control signal
generator in the testbench. The input data is stored in the device’s internal
memory as ROM initialized by the input_data_rom.hex file. The address
to the ROM is generated by an internal counter.
Channel degradation effects such as signal nulling, signal attenuation and

additive noise can be induced by the user via switches on the Stratix
EP1S25 or EP1S80 DSP development board. Push-button switch SW1
asserts the input signal channel_alpha, which causes the demodulator
input to be attenuated by a factor ATTEN_FACTOR. The assertion of push-
button switch SW2 raises the input signal channel_beta to a logic 1,
causing the signal component of the channel output to be grounded. The
addition of noise, with variance proportional to the parameter
NOISE_LEVEL, is controlled by the DIP switch SW3p1 on the Stratix
EP1S25 or EP1S80 DSP development board. Setting the DIP switch SW3p1
to the ON position asserts the input signal channel_gamma and adds
noise to the channel input. The DSSS channel model parameters
ATTEN_FACTOR and NOISE_LEVEL (represented by KA and NL,
respectively in Figure 29) can be set at compile time by modifying the
parameters in the testbench file dsss_interface.vhd.
To view the output data from the modem on the Stratix EP1S25 or EP1S80
DSP development board, the SignalTap® II Logic Analyzer is used.
When code synchronization has been lost and then reacquired, the signal
lock in the Gold Code correlator peak detector is driven from low to high.
The signal is therefore used to trigger the SignalTap II Logic Analyzer to
upload data to the Quartus II software where it is displayed in the
SignalTap II Waveform Viewer. The data is clocked into the memory of
the internal logic analyzer by the 3.84 MHz clock generated by the Stratix
PLL. The trigger position is set to Pre indicating that 12% of the 16K
samples saved will be from the period of time before code
synchronization is acquired (or required), while the remaining samples
are from the period of time after code synchronization. This allows the
adjustment of the receiver to the actions that have caused a loss in lock
(i.e., system reset, signal attenuation, or nulling) to be observed, with
output data matching expected output after this period of adjustment.
Figure 29. DSSS Modem Reference Design & Synthesizable Testbench

SW1 channel_alpha
SW2 channel_beta
SW3p1 channel_gamma
DSSS Channel Model
GND
Input channel_beta = 0 channel_beta = 1

DSSS
Data Modulator
Source
channel_gamma = 0 Output Data
channel_alpha = 0 DSSS
1
GND Demodulator
channel_alpha = 1 channel_gamma = 1
XTAL KA
Stratix PLL
Noise
Generator NL
Control
sysreset
SW0
Configuring the Stratix Device & Exercising the DSSS Modem on

the Stratix EP1S25 or EP1S80 DSP Development Board
To exercise the DSSS modem on the Stratix EP1S25 or EP1S80 DSP

development board, you need to:
■ Configure the Stratix device on the Stratix EP1S25 or EP1S80 DSP

development board with the generated SRAM object file
dsss_interface.sof from within the SignalTap II Logic Analyzer in the
Quartus II design software.
■ Run the SignalTap II Logic Analyzer to view the modem output and
expected output to verify correct operation of the modem in the
Stratix device.
To configure the Stratix device on the Stratix EP1S25 or EP1S80 DSP

development board with the software output file dsss_interface.sof,
perform the following steps:
1. Connect the power supply unit (provided) to the Stratix EP1S25 or

EP1S80 DSP development board.
2. Attach the ByteBlaster™ II cable to the LPT1 parallel port of your PC

and connect it to the Stratix EP1S25 or EP1S80 DSP development
board.
3. Open the Quartus II project file, dsss.quartus.
4. Open the SignalTap II User Interface if it is not already open.
5. Choose the SignalTap II Logic Analyzer (Tools menu). SignalTap II

will open the dsss.stp file.
6. Ensure that the hardware setup is appropriately set to use the

ByteBlaster II cable on the correct communications port.
7. To configure the device with the dsss_interface.sof output file,

select the Programmer/Configure icon . Figure 30 shows an
example using the Stratix EP1S25 development board.
Figure 30. Example SignalTap II Configuration Using Stratix EP1S25 Device
To run the SignalTap II Logic Analyzer to view the modem output and
expected output, perform the following steps:
1. Choose the Autorun icon .
2. Press the push-button switch SW0 on the Stratix EP1S25 or EP1S80

DSP development board to reset the design. Upon release of the
switch, the receiver works to acquire carrier and code
synchronization in addition to the correct AGC gain level. Once the
receiver has converged to the correct operation point, the lock signal
is driven high triggering the SignalTap II Logic Analyzer to upload
the modem output data and expected output data to the respective
signals, data_out[5..0], and expected_output[5..0] in the
SignalTap II Waveform Viewer.
3. Induce channel effects. While the modem runs on the Stratix device,
nulling the channel output signal component can be achieved by
asserting the push-button switch SW2 on the Stratix EP1S25 or
EP1S80 DSP development board. This has the effect of causing the
receiver to lose synchronization again because its input consists of
noise only. When the switch is released, the receiver reacquires
synchronization, causing the lock signal to go high, and triggering

the SignalTap II Logic Analyzer to upload the data points back to the
Quartus II software. Similarly, asserting the push-button switch SW1
causes an attenuation of the input data to the demodulator. When
the attenuation has been compensated for sufficiently, the lock signal
is again raised high triggering the logic analyzer to upload the data.
Figure 31 shows the region either side of the SignalTap II Logic Analyzer
trigger event, enlarged to illustrate the result of applying the system reset
during modem operation. Initially, both the output and the expected
output are grounded while the reset is held. Thereafter, a period of time
follows where the output data is not as expected, i.e., it contains errors.
This is the acquisition interval of the modem where the AGC level and
carrier and code synchronization are obtained. After the receiver has
compensated for these effects, the output data matches the expected data
and the demodulator correctly recovers the transmitted data from the
received IF signal.
Figure 31. SignalTap II Logic Analyzer Trigger Event
Resource Usage Summary
Table 8 lists the resource usage of the DSSS modem reference design’s
primary functional units.
Table 8. DSSS Modem Resource Usage
Design Entity Logic M512 RAM M4K RAM MegaRAM DSP Block PLL
Elements Elements
DSSS modulator 9943 1 8 0 12 0
DSSS channel model 73 0 0 0 0 0
DSSS demodulator 12196 60 8 1 60 0
DSSS control, (1) 160 0 96 0 0 1
Note:
(1) Includes resource usage for the system control signal generation, clock generation, testbench input data storage, and
SignalTap Logic Analyzer.
Power Usage Estimates
The following device power usage estimates were obtained from the
Quartus II software over 100 µs of timing simulation.
Table 9. DSSS Modem Power Usage Estimates
Power mW
Total internal power 506.50
Total standby internal power 75.00
Total logic element internal power 282.71
Total IO buffer internal power 0.11
Total M512 RAM internal power 0.27
Total M4K RAM internal power 14.15
Total Clocktree internal power 175.05
Total DSP internal power 23.13
Total PLL internal power 78.03
Total power 506.50
References Reference documents for AN 289 include:
■ Shannon, C.E., A Mathematical Theory of Communications, Bell

Syst., Tech. J vol. 27, 1948 pp. 379-423, 623-657.
■ Smith J. G., Spectrally Efficient Modulation, Proc IEEE Int. Conv.
Commun. (ICC ’77) , June 1977 pp 3.1-37-3.1-41
■ M. Schwartz, Information Transmission, Modulation, And Noise.
McGraw-Hill, 1990. 4th edition.
■ Papuolis, A., Probability, Random Variables and Stochastic
Processes, McGraw-Hill Book Company, New York, 1965
■ F. M. Gardner, Phaselock Techniques, Wiley, New York, 1979.
■ ] B.P. Lathi, Modern Digital and Analog Communications Systems
2nd Edition, Oxford University Press, New York, 1983.
■ Phase-Locked Loops: Applications to Coherent Receiver Design,
Wiley 1976. Reprinted 1992, Krieger
■ Lindsey, W.C. and Simon M.K., eds., Phase Lock Loops and Their
Applications, IEEE Press, New York, 1977.
■ H. Harashima and H. Miyakawa, Matched-Transmission Technique
for Channels with Inter-symbol Interference, IEEE Trans.
Commun.,vol. COM-20, pp.774-80, August 1972.
■ Geraniotis, E., and Pursely M.B., Error Probabilities for Direct
Sequence Spread Spectrum Multiple-Access Communications: Part II
Approximations, IEEE Trans. Commun., vol COM30, No. 5, May
1982, pp 996-1009.
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Direct Sequence Spread

Spectrum (DSSS) Modem

Introduction Much of the signal processing performed in modern wireless

The Altera Stratix™ device family—with its dedicated DSP blocks,

The DSSS reference design implements a DSSS digital modem that

The DSSS modem reference design requires the following software:

■ Quartus II software, version 2.2

Figure 1. DSSS Modem

The DSSS modem reference design provides the following features:

■ Five independent data channels spread to 3.84 Mcps

This application note discusses the implementation of the DSSS modem,

Figure 2. Installation File Directory Structure

The modulator consists of a channelization section achieved by

Figure 3. DSSS Modulator

Orthogonal Variable Spreading Factor (OVSF) Code

Table 1. Channel Codes

Gold Code Generation

In 3G wireless modems, synchronization of the user equipment (UE) to

Gold Codes have excellent auto-correlative properties, and thus provide a

Figure 4. Synchronization Channel Generator

Figure 5. Auto-Correlation Function of Gold Codes

Pulse-Shape Filtering and Interpolation

1 To show the constituent effect of each of the filters in the multi-

Figure 6. Frequency Response of FIR Filters

The second filter stage is an interpolation-by-four filter designed with a

Figure 6 (Convolved Transmit Spectral Mask) shows the overall transmit

An NCO is used to translate the base-band data up to an IF of 15.36 MHz.

Table 2. Required NCO Specifications

Figure 8. Modulator NCO Parameterization

Required resolution = log2 (fclk/fres) bits

■ An angular precision of 18 bits

Figure 9 shows a spectral plot of the NCO sine output.

Figure 9. Spectral Plot of NCO Sine Output

Mixer & Quadrature Combiner

To modulate the 122.88 MSPS pulse-shaped I and Q components onto the

Modulator Design File Summary List

Table 3. Modulator Design File List

Design Entity Description Function

The channel output spectral response can be represented by the following

Where, H ( j ω ) = α e – j ω r and N j ω is the frequency domain

Figure 10 shows the channel model.

Figure 10. Channel Model

x(n) z−r y(n)

The attenuation α is a user-specifiable attenuation factor and r represents

Table 4 lists the channel model design entities.

Table 4. Channel Model Design Entities

Design Entity Description Function

Figure 11. DSSS Demodulator

31-Tap FIR Filter

Automatic Gain Control (AGC)

To compensate for possible attenuation of the transmitted channel signal,

Figure 12. AGC Circuit

Demodulator Input x(n) 8 ( )2

Figure 13. Altera IIR Compiler

Figure 14. Overal AGC Loop Filter Response

The dead-bander outputs two control signals to the up/down counter:

■ Directional indicator, w[n]

The directional indicator control signal, w[n], indicates to the counter if

The loop gain accelerator control signal, g[n], is a non-linear function of

Figure 15. Gain Acceleration Vs. Estimated Signal Power Level

Demodulator NCO & Mixer Circuitry

The demodulator NCO—which was designed with the Altera NCO

Carrier Recovery Loop

Ψ d[n] = i[n]* sq[n] -q[n]* si[n]