Case 6:21-cv-00057-ADA Document 599 Filed 04/22/21 Page 1 of 25

IN THE UNITED STATES DISTRICT COURT

FOR THE WESTERN DISTRICT OF TEXAS
WACO DIVISION

VLSI TECHNOLOGY LLC,

Plaintiff,

Case No. 6:21-cv-00057-ADA

v.

INTEL CORPORATION,
Defendant.

DEFENDANT INTEL CORPORATION’S RULE 50(B) MOTION

FOR JUDGMENT AS A MATTER OF LAW1

1
Pursuant to Fed. R. Civ. P. 59, Intel is concurrently filing a motion for a new trial on
infringement, invalidity, and damages (“Rule 59 Motion”). Pursuant to Fed. R. Civ. P. 52, Intel
is also filing briefs on bench trial issues relating to the ’759 patent (“’759 Bench Trial Brief”)
and unclean hands (“Unclean Hands Bench Trial Brief”).
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TABLE OF CONTENTS

PRELIMINARY STATEMENT .....................................................................................................1

I. INTEL IS ENTITLED TO JMOL OF NO INFRINGEMENT FOR THE ’373
AND ’759 PATENTS. .........................................................................................................1
A. No Reasonable Jury Could Find Infringement Of The Asserted Claims Of
The ’373 Patent. 1
1. The accused products do not store the claimed “minimum
operating voltage” or a value representative thereof. ..................................2
2. The accused products do not provide or supply the first and second
regulated voltages to the memory “when” the claims require. ....................5
3. The functional circuit in the accused products is not provided with,
and does not use, the first regulated voltage “while” the second
regulated voltage is provided to the memory. ..............................................6
B. No Reasonable Jury Could Find Infringement Of The Asserted Claims Of
The ’759 Patent. 8
1. The accused products do not provide the claimed “request.” ......................8
2. The accused products do not output a clock frequency of the high-
speed clock “to control” both “a clock frequency of a second
master device” and a “clock frequency of the bus.” ..................................11
C. No Reasonable Jury Could Find That VLSI Has Met Its Burden To Prove
Indirect Infringement. 13
II. INTEL IS ENTITLED TO JMOL OF INVALIDITY FOR THE ASSERTED
CLAIMS OF THE ’759 PATENT. ....................................................................................14
III. INTEL IS ENTITLED TO JMOL OF NO DAMAGES. ...................................................16
IV. CONCLUSION ..................................................................................................................20

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TABLE OF AUTHORITIES

Page(s)

CASES

Agrofresh Inc. v. Essentiv LLC,

2020 WL 7024867 (D. Del. Nov. 30, 2020) ............................................................................10

Alcon Research Ltd. v. Barr Laboratories, Inc.,

745 F.3d 1180 (Fed. Cir. 2014)..............................................................................................2, 8

Branch-Hines v. Hebert,
939 F.2d 1311 (5th Cir. 1991) ...............................................................................................2, 8

Carson v. Polley,
689 F.2d 562 (5th Cir. 1982) ...................................................................................................19

Cobalt Boats, LLC v. Brunswick Corp.,

773 F. App’x 611 (Fed. Cir. 2019) ............................................................................................9

Energy Transportation Group, Inc. v. William Demant Holding A/S,

697 F.3d 1342 (Fed. Cir. 2012)..................................................................................................9

Jang v. Boston Scientific Corp.,

872 F.3d 1275 (Fed. Cir. 2017)................................................................................................10

Medtronic, Inc. v. Mirowski Family Ventures, LLC,

571 U.S. 191 (2014) .................................................................................................................13

Mirror Worlds, LLC v. Apple Inc.,

784 F. Supp. 2d 703 (E.D. Tex. 2011) .......................................................................................1

Mirror Worlds, LLC v. Apple Inc.,

692 F.3d 1351 (Fed. Cir. 2012)..................................................................................................1

MobileMedia Ideas LLC v. Apple Inc.,

780 F.3d 1159 (Fed. Cir. 2015)................................................................................................11

Paradox Security Systems, Ltd. v. ADT Security Services, Inc.,

388 F. App’x 976 (Fed. Cir. 2010) ..........................................................................................11

Power Integrations, Inc. v. Fairchild Semiconductor International, Inc.,

843 F.3d 1315 (Fed. Cir. 2016)................................................................................................10

Process Control Corp. v. HydReclaim Corp.,

190 F.3d 1350 (Fed. Cir. 1999)................................................................................................13

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Retractable Technologies, Inc. v. Becton Dickinson & Co.,

842 F.3d 883 (5th Cir. 2016) .....................................................................................................1

Synthes USA, LLC v. Spinal Kinetics, Inc.,

2012 WL 4483158 (N.D. Cal. Sept. 27, 2012) ........................................................................14

Wisconsin Alumni Research Foundation v. Apple Inc.,

905 F.3d 1341 (Fed. Cir. 2018)..................................................................................................5

X One, Inc. v. Uber Technologies, Inc.,

440 F. Supp. 3d 1019 (N.D. Cal. 2020) ...................................................................................13

STATUTES AND RULES

35 U.S.C. § 102(g) .........................................................................................................................14

Federal Rule of Civil Procedure 50(a) .............................................................................................1

Federal Rule of Civil Procedure 50(b) .............................................................................................1

EXHIBITS

The exhibits cited in this motion as “Ex. __” are attached to the Declaration of Jeffrey A.
Dennhardt, filed as an attachment to this motion.

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PRELIMINARY STATEMENT

Following a six-day trial, the jury found that Intel literally infringed claims 1, 5, 6, 9, and

11 of U.S. Patent No. 7,523,373 (“the ’373 patent”) and infringed claims 14, 17, 18, and 24 of

U.S. Patent No. 7,725,759 (“the ’759 patent”) under the doctrine of equivalents. (Dkt. 564 at 2-

3.) The jury also found that Intel had not met its burden to prove that claims 14, 17, 18, and 24

of the ’759 patent were invalid. (Id. at 5.) The jury awarded VLSI a total of $2.175 billion in

damages: a lump sum of $1.5 billion for the ’373 patent and a lump sum of $675 million for the

’759 patent. (Id. at 6-7.) As explained below, however, the jury’s verdicts on infringement and

validity, as well as the amount of damages it awarded, were contrary to law and not supported by

substantial evidence. Therefore, pursuant to Fed. R. Civ. P. 50(b), Intel requests that the Court

enter judgment as a matter of law (“JMOL”) of no infringement for the ’373 and ’759 patents,

JMOL of invalidity for the ’759 patent, and JMOL of no damages. See Mirror Worlds, LLC v.

Apple Inc., 784 F. Supp. 2d 703, 710 (E.D. Tex. 2011) (JMOL “appropriate when ‘a reasonable

jury would not have a legally sufficient evidentiary basis to find for the [non-moving] party on

that issue’” (quoting Fed. R. Civ. P. 50(a))), aff’d, 692 F.3d 1351 (Fed. Cir. 2012); Retractable

Techs., Inc. v. Becton Dickinson & Co., 842 F.3d 883, 891 (5th Cir. 2016).

I. INTEL IS ENTITLED TO JMOL OF NO INFRINGEMENT FOR THE ’373 AND

’759 PATENTS.

A. No Reasonable Jury Could Find Infringement Of The Asserted Claims Of

The ’373 Patent.

The jury found that the C6 SRAM power multiplexer in Intel’s Haswell and Broadwell

products literally infringes claims 1, 5, 6, 9, and 11 of the ’373 patent. (Dkt. 564 at 2.)2 JMOL

2
At trial, VLSI did not assert the doctrine of equivalents for the ’373 patent. (See 2/23 Tr.
[Conte] 451:14-20.)

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the asserted claims require—because it is not. (2/25 Tr. [Sylvester] 941:7-24, 944:12-945:4,

954:14-21; DDX-7.17.) Indeed, Dr. Conte never explained how any voltage values stored in the

RING_RETENTION_VOLTAGE fuse supposedly relate to any properties of the accused C6

SRAM memory—including the “minimum voltage” that the C6 SRAM must receive to reliably

retain information. Intel’s expert Dr. Sylvester, and Intel engineer Jonathan Douglas

all agreed that RING_RETENTION_VOLTAGE applies generally to the “ring domain,” which

contains multiple components beyond the C6 SRAM (e.g., CBO, ring, multiple memory

arrays). 2/25 Tr. [Sylvester] 938:14-21,

950:21-953:1, 954:22-955:4; id. [Douglas] at 842:3-845:7, 854:22-855:3, 859:11-17; DDX-5.4;

DDX-5.5.) Mr. Douglas further confirmed there is no relationship between

RING_RETENTION_VOLTAGE and the C6 SRAM specifically (as opposed to the entire ring

domain), and VLSI presented no evidence to the contrary. (2/25 Tr. [Douglas] 859:11-20.)

For the accused Haswell and Broadwell products, Dr. Conte identified only two Intel

documents (one for each family) in support of his contentions regarding

, but neither document states or otherwise indicates

And, in fact, Dr. Sylvester,

Mr. Douglas, and Intel engineer Dan Borkowski all confirmed that the C6 SRAM and other

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components in the ring domain: (1) operate below RING_RETENTION_VOLTAGE—at the

lower RING_VF_VOLTAGE_0 voltage level, and (2) are fully operational at the

RING_VF_VOLTAGE_0 level, which is actually used in the accused products. (2/25 Tr.

[Douglas] 860:15-24, 854:8-16, 861:14-20; id. [Sylvester] 948:9-17, 945:20-948:17, 949:12-

950:14, 1014:24-1015:11, 1016:8-1017:16; id. [Borkowski] at

105:3-7, 105:17-25, 106:6-108:7; D-1661; D-1107 (A-D); DDX-7.21.) This evidence establishes

that RING_RETENTION_VOLTAGE is not the “minimum retention voltage” (or any other

“minimum operating voltage”) for the C6 SRAM.4

In rebuttal, Dr. Conte pointed to an Intel document showing a “Vretention” below a “v/f

0” point (D-505 at 24) and offered conclusory arguments that this rebutted the testimony of Dr.

Sylvester and Intel’s engineers (3/1 Tr. [Conte] 1425:15-1426:20), but Dr. Conte agreed that it

was a draft document and “not a final description of the products” (id. at 1435:11-1436:11). Dr.

Conte also claimed that Dr. Sylvester had failed to account for “inverse temperature dependence”

(voltage adjustments based on processor temperature) in comparing the values of

RING_RETENTION_VOLTAGE and RING_VF_VOLTAGE_0 (id. at 1426:21-1431:22)—an

opinion Dr. Conte offered for the first time at trial and only during rebuttal—but Dr. Conte

provided no factual support for this claim. (See id. at 1429:21-25.) Moreover, Dr. Conte’s

conclusory opinion cannot be squared with Intel engineer testimony and other factual evidence in

the record, including pcode for the accused products showing that

4
On cross-examination, VLSI’s counsel asked Intel’s expert Dr. Sylvester about a document
with “Vmin” data for Haswell and Broadwell processors. (2/25 Tr. [Sylvester] 986:15-989:11;
PTX-3675.) But Dr. Sylvester explained on re-direct that “Vmin” refers to an active voltage “to
meet a performance specification”—not a retention voltage—and has no connection to
RING_RETENTION_VOLTAGE or any minimum operating voltage of the accused C6 SRAM
memory. (2/25 Tr. [Sylvester] 1013:6-1016:2.) Dr. Conte never testified about this “Vmin”
document at all, let alone that the “Vmin” figures have any relation to the accused
RING_RETENTION_VOLTAGE fuse.

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value of the minimum operating voltage,” and (2) “the second regulated voltage … when the first

regulated voltage is less than the value of the minimum operating voltage.” (PTX-4, claims 1, 5,

6.) Each asserted apparatus claim also requires “a power supply selector that supplies” as the

operating voltage of the memory (1) “the first regulated voltage ... when the first regulated

voltage is at least the minimum operating voltage” and (2) “the second regulated voltage ... when

the first regulated voltage is below the minimum operating voltage.” (Id., claims 9, 11.)

Even under VLSI’s theory that the RING_RETENTION_VOLTAGE fuse stores the

“minimum operating voltage” value of the C6 SRAM, VLSI introduced no evidence that the

RING_RETENTION_VOLTAGE fuse value is ever used to guide “when” VCCR (what VLSI

accuses as the “first regulated voltage”) and VCCIO (what VLSI accuses as the “second

regulated voltage”) are supplied.

Dr. Conte offered no contrary opinions. Therefore,

JMOL of no infringement should enter for this additional reason.

3. The functional circuit in the accused products is not provided with,

and does not use, the first regulated voltage “while” the second
regulated voltage is provided to the memory.

Each asserted method claim further requires that, “while the second regulated voltage is

provided as the operating voltage of the memory, the first regulated voltage is provided to the

functional circuit.” (PTX-4, claims 1, 5, 6.) Similarly, each asserted apparatus claim requires “a

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power supply selector” that “supplies the second regulated voltage” to the memory “while” “the

circuit [that provides a function] uses the first regulated voltage.” (Id., claims 9, 11.)

However,

Intel’s witnesses testified that during the Package C7 sleep state—the state in which VCCIO

(what VLSI accuses as the “second regulated voltage”) powers the C6 SRAM bitcells—the

VCCR voltage (what VLSI accuses as the “first regulated voltage”) is unregulated and the

components on the ring are inoperable. (2/25 Tr. [Douglas] 863:16-864:19; id. [Sylvester] at

938:24-940:2, 941:7-24, 958:16-959:16, 960:9-18, 961:7-963:15, 965:17-966:10; DDX-7.15;

DDX-7.17; DDX-7.33; DDX-7.34; PTX-1588-NAT.39-40; D-27 at 39-40.)

Nor did Dr. Conte offer

any evidence that the ramped voltage is “reliable” during the ramp—as his own definition of a

regulated voltage requires. (2/23 Tr. [Conte] 383:15-384:5.) On the contrary, Intel’s witnesses

confirmed that VCCR is not regulated or reliable, nor are the ring components operable, during

this “ramp.” (2/25 Tr. [Douglas] 864:20-865:18, 880:19-881:23; id. [Sylvester] at 963:16-

964:17.) And, again, Dr. Conte offered no contrary evidence in his rebuttal testimony; in fact, he

agreed with Mr. Douglas’s testimony that the components in the ring domain are shut off and not

functional during the Package C7 state. (DDX-19.7; 3/1 Tr. [Conte] 1437:18-23.)

Accordingly, JMOL is required because no reasonable jury could find that what VLSI

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feature satisfied the “request” limitations under the doctrine of equivalents.

As an initial matter, to overcome a prior art rejection during prosecution, the ’759

applicant amended its claims to require that the claimed “request” is (1) “sent from the master

device” (not from “at least one of the plurality of master devices,” as previously claimed), and

(2) “in response to a predefined change in performance of the master device” (not on a regular,

periodic basis unrelated to any change in performance of the master device, as also previously

claimed). (D-249 at 350; 2/23 Tr. [Conte] 460:8-461:25.) Yet Dr. Conte asserted at trial that the

“request” limitations were satisfied by data sent by a combination of components (the core and

pcode running on the PCU) based on information sent continuously and periodically (not in

response to a performance change). (2/23 Tr. [Conte] 468:11-18, 470:8-471:12.) In other words,

Dr. Conte’s equivalents theory improperly recaptured subject matter that the patentee had

surrendered to obtain the claims. Thus, as explained more fully in Intel’s ’759 Bench Trial Brief,

prosecution history estoppel bars VLSI from relying on the doctrine of equivalents. See, e.g.,

Energy Transp. Grp., Inc. v. William Demant Holding A/S, 697 F.3d 1342, 1360 (Fed. Cir. 2012)

(affirming JMOL of no equivalents due to prosecution history estoppel); Cobalt Boats, LLC v.

Brunswick Corp., 773 F. App’x 611, 617-19 (Fed. Cir. 2019) (nonprecedential) (same).

As also explained in Intel’s ’759 Bench Trial Brief, VLSI’s equivalents argument

improperly vitiated the claim requirement of sending the “request” from the first master device

“in response to a predefined change in performance of the first master device.” (PTX-5, claims

14, 18.) Dr. Conte conceded that sending C0 residency information occurs “periodically”

irrespective of any changes in performance of the core. (2/23 Tr. [Conte] 468:11-18, 470:8-

471:12.) To treat this regularly-sent information as equivalent to the claimed “request” would

thus eliminate the “in response to a predefined change in performance of the first master device”

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Ventures, LLC, 571 U.S. 191, 198-99 (2014); Synthes USA, LLC v. Spinal Kinetics, Inc., 2012

WL 4483158, at *12 (N.D. Cal. 2012). Regardless, for the reasons stated above, VLSI failed to

prove infringement of any claim, and thus no claim for indirect infringement can exist.

II. INTEL IS ENTITLED TO JMOL OF INVALIDITY FOR THE ASSERTED

CLAIMS OF THE ’759 PATENT.

A patent is invalid if, before the patented invention, “the invention was made in this

country by another inventor who had not abandoned, suppressed, or concealed it.” 35 U.S.C.

§ 102(g) (pre-AIA). The jury found that Intel did not prove by clear and convincing evidence

that claims 14, 17, 18, and 24 of the ’759 patent are invalid as anticipated by Intel’s Yonah

processor. (Dkt. 564 at 5.) But given the evidence presented at trial, a reasonable jury could

only conclude that each asserted claim of the ’759 patent is anticipated by Intel’s prior invention

of Yonah.

As an initial matter, it is undisputed that Yonah is prior art under § 102(g). (2/26 Tr.

1040:7-1041:17 (“Mr. Chu: … We’re not contesting that Yonah qualifies as prior art.”); id.

[Rotem] at 1049:20-1057:2, 1065:7-1068:18; id. [Grunwald] at 1170:24-1172:8; D-949; D-957;

D-960; D-961; D-26; D-294; DDX-10.54; DDX-10.56; DDX-10.63; 3/1 Tr. 1542:11-12; Dkt.

563 at 31.) Intel also presented conclusive evidence that Yonah included each limitation of the

asserted claims. At trial, VLSI’s assertion otherwise was based solely on its argument that

Yonah did not have a hardware-based “programmable clock controller.” (3/1 Tr. [Conte]

1410:12-20.) But as explained below, VLSI’s argument is foreclosed by the claim language and

the specification. See infra pp. 15-16.

For claim 14, the evidence conclusively demonstrates the following:

• Element 14[A]: As VLSI did not contest, Yonah included a bus capable of operating

at a variable frequency. (2/26 Tr. [Rotem] 1063:24-1064:16, 1124:15-24; id. [Grunwald] at

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1172:9-1173:25, 1221:23-1222:19; D-267; D-274; D-33 at 36; DDX-10.67; PDX5.7.)

• Elements 14[B], 14[C]: As VLSI did not contest, Yonah included two cores (a “first

master device” and a “second master device”), each of which was coupled to the bus—and the

first core (via the operating system running on it) tracked the workload of the core, and in

response to a predefined change in performance of the first core, issued requests to change the

clock frequency of a high-speed clock. (2/26 Tr. [Rotem] 1050:1-8, 1058:7-22, 1096:21-1097:1,

1101:2-10; id. [Grunwald] at 1172:9-1173:25, 1222:5-1224:9; D-32 at 22; D-33; D-31 at 6; D-

296; DDX-10.68-10.70; 3/1 Tr. [Conte] 1445:18-25; PDX5.7.)

• Elements 14[D], 14[E]: Yonah included “a programmable clock controller” that had

an “embedded computer program therein” configured to receive a “request” from the first core.

(2/26 Tr. [Rotem] 1063:24-1064:16, 1104:3-6, 1124:15-24; id. [Grunwald] at 1224:12-1225:7,

1226:1-1227:6; 3/1 Tr. [Grunwald] 1345:17-1346:14; D-31; D-267 at 8, 11; D-284; D-948-D-

950; D-955-D-964; DDX-10.71; DDX-10.72.) Dr. Conte’s opinion that Yonah does not

anticipate was based solely on his opinion that Yonah did not have a hardware-based

programmable clock controller (3/1 Tr. [Conte] 1410:12-1417:12; PDX5.7-5.10), but the claim

language and specification make clear that a hardware-based controller is not required and that

software may be used (e.g., PTX-5 at 2:51-57, claims 14, 18). Indeed, Dr. Conte agreed that the

claimed “programmable clock controller” has “an embedded computer program,” which is “a

software program.” (2/23 Tr. [Conte] 492:25-493:10.) He also acknowledged that the ’759

patent specification “refers specifically to firmware” and “also refers specifically to software.”

(3/1 Tr. [Conte] 1446:15-24; see PTX-5 at 2:51-57.) Dr. Conte then admitted that the Yonah

operating system “had ultimate control over frequency changes,” that “the operating system was

executed in the cores of Yonah,” and that “it was that operating system in Yonah” that “asked the

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hardware to change the frequencies.” (3/1 Tr. [Conte] 1446:1-13; see id. [Conte] at 1406:2-14.)

The evidence thus establishes that Yonah included the claimed “programmable clock controller”

under the plain meaning of the claim language, which does not require a hardware-based clock

controller.

• Elements 14[F], 14[G]: In response to receiving the request, Yonah’s programmable

clock controller outputted the same high-speed clock frequency to control both the second core

and the bus. (2/26 Tr. [Rotem] 1060:1-7, 1066:9-1067:18, 1069:16-21, 1086:11-18, 1124:15-24;

id. [Grunwald] at 1172:9-1173:25, 1227:7-1228:17; D-31; D-32; D-33 at 36; D-267; D-274 at 8;

DDX-10.73; DDX-10.74; 3/1 Tr. [Conte] 1446:25-1447:9.) Indeed, Dr. Conte admitted that

Yonah had a PLL that “provided common clock control to all of Yonah.” (3/1 Tr. [Conte]

1446:25-1447:9.)

As to the other asserted claims, Intel showed that Yonah satisfied elements 18[A], 18[B],

and 18[E]-[I] for the same reasons it satisfied the corresponding elements in claim 14. (2/26 Tr.

[Grunwald] 1229:4-10.) VLSI did not contest Intel’s proof that Yonah satisfied the added

“arbiter” requirements of claim 18—via a router coupled to the bus, the first master device, and

the clock controller, and that arbitrates between requests, thereby controlling the flow of data on

the bus. (Id. at 1229:11-1230:3; D-281; D-31.) Nor did VLSI challenge Intel’s proof that Yonah

included each additional limitation required by dependent claims 17 and 24. (2/26 Tr. [Rotem]

1063:4-1064:16; id. [Grunwald] at 1228:20-25, 1230:6-10; D-274; D-33; D-31; D-296.)

On this record, a reasonable jury could only find that Yonah included each limitation of

the asserted claims under the plain meaning of the claim language. The Court should therefore

enter JMOL of invalidity.

III. INTEL IS ENTITLED TO JMOL OF NO DAMAGES.

As described above, the jury awarded a lump sum of $1.5 billion for the ’373 patent and a

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record”).)14 And the $2.175 billion lump sum awarded by the jury differs from Dr. Sullivan’s

analysis in both amount and form. (See PDX7.64, PDX7.66 (Dr. Sullivan calculating $1.61

billion for the ’373 patent and $831 million for the ’759 patent, each representing a running

royalty rather than a lump sum).) In any event, based on the trial record, no reasonable jury

could have: (1) found that Intel and/or Freescale—the parties to the hypothetical negotiation

here—would have used or even considered Dr. Sullivan’s made-for-litigation methodology to

value either asserted patent (2/24 Tr. [Sullivan] 705:13-707:4, 708:19-712:22); (2) accepted the

results of the flawed tests performed by VLSI’s technical experts, on which Dr. Sullivan’s

damages calculations hinged (2/24 Tr. [Sullivan] 702:4-703:2, 703:17-704:17, 728:6-729:17; id.

[Annavaram] 538:7-11, 539:4-540:3, 554:23-555:13, 556:8-561:19, 562:10-566:5, 578:7-581:1,

582:6-582:17, 582:20-583:7; PDX8.12; PDX8.16; 2/25 Tr. [Douglas] 855:25-857:11, 865:24-

866:6; id. [Sylvester] at 969:17-981:4; PTX-983; 2/26 Tr. [Rotem] 1124:4-6; Sealed Tr. [Conte]

30:12-31:17, 71:19-72:19; PDX4.242; PTX-3638; 3/1 Tr. [Conte] 1441:6-22, 1458:17-25;

DDX19.15); (3) accepted Dr. Sullivan’s regression analysis, which improperly included the

value of non-accused products and non-accused features, yet did not include the accused

features he purported to assess (2/24 Tr. [Sullivan] 616:8-617:9, 617:14-618:24, 619:25-620:23,

713:7-714:10, 720:6-723:10); and (4) accepted that the parties to the hypothetical negotiation

would have agreed to give VLSI 100% of the profits attributable to the alleged use of the patents,

as Dr. Sullivan’s analysis improperly assumed (2/24 Tr. [Sullivan] 661:11-664:20). See Rule 59

14
Although VLSI never put the damages numbers derived from Dr. Sullivan’s calculations into
evidence, it appears the Court inadvertently sent them back to the jury room during deliberations.
(Ex. 2; Ex. 3 (list of exhibits made available to jury during deliberations that includes unadmitted
PTX-3909, PTX-3910, and PTX-3912).) As explained in Intel’s Rule 59 Motion, if this Court
does not grant Intel’s motion for JMOL, it should grant a new trial because the jury
“inadvertently considered inadmissible evidence” that was prejudicial to Intel. See Carson v.
Polley, 689 F.2d 562, 569-71 (5th Cir. 1982).

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Motion at 6-11. Because Dr. Sullivan’s damages testimony depended on each of these defective

methodologies, JMOL of no damages should enter. See Crystal Semiconductor Corp. v. TriTech

Microelecs. Int’l, Inc., 246 F.3d 1336, 1358 (Fed. Cir. 2001) (affirming JMOL due to unreliable

expert damages methodology).

Fourth, Dr. Sullivan improperly used all of Intel’s revenues from sales of the accused

products to justify VLSI’s damages claim—without any evidence that the asserted patents are the

supposed “basis” for customer demand for the accused products. (2/24 Tr. [Sullivan] 652:9-21,

653:3-20, 655:18-658:2; PTX-3903; PDX7.49; PDX7.53.) This violates the entire market value

rule and warrants JMOL of no damages. See Lucent Techs., 580 F.3d at 1337-40 (reversing

denial of JMOL on damages issues where damages expert relied on total price of product and

entire market value rule did not apply); see also Rule 59 Motion 11.

Finally, VLSI’s damages claim is legally deficient because, as set forth in Intel’s

Daubert motions concerning the opinions of Dr. Sullivan, Mr. Chandler, Dr. Conte, and Dr.

Annavaram (Dkts. 261, 262, 264, 265), VLSI’s damages-related experts should not have been

permitted to testify on certain issues. See Rule 59 Motion at 1-12. Because VLSI’s entire

damages case at trial rested on that unreliable evidence, there was no proper basis on which a

reasonable jury could award damages in any amount. VLSI thus “failed to present a damages

case that can support the jury’s verdict” and “waived the right to damages based on alternate

theories,” such that JMOL of no damages should enter. See Finjan, Inc. v. Blue Coat Sys., Inc.,

879 F.3d 1299, 1312 (Fed. Cir. 2018).

IV. CONCLUSION

For the foregoing reasons, Intel respectfully requests that the Court enter JMOL of no

infringement for the asserted claims of the ’373 and ’759 patents, invalidity for the asserted

claims of the ’759 patent, and no damages.

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Dated: April 9, 2021 Respectfully submitted,

/s/ J. Stephen Ravel

OF COUNSEL: J. Stephen Ravel
Texas State Bar No. 16584975
William F. Lee (Pro Hac Vice) Kelly Ransom
Louis W. Tompros (Pro Hac Vice) Texas State Bar No. 24109427
Kate Saxton (Pro Hac Vice) KELLY HART & HALLMAN LLP
WILMER CUTLER PICKERING HALE 303 Colorado, Suite 2000
& DORR LLP Austin, Texas 78701
60 State Street Tel: (512) 495-6429
Boston, Massachusetts 02109 Email: steve.ravel@kellyhart.com
Tel: (617) 526-6000 Email: kelly.ransom@kellyhart.com
Email: william.lee@wilmerhale.com
Email: louis.tompros@wilmerhale.com James E. Wren
Email: kate.saxton@wilmerhale.com Texas State Bar No. 22018200
1 Bear Place, Unit 97288
Gregory H. Lantier (Pro Hac Vice) Waco, Texas 76798
Amanda L. Major (Pro Hac Vice) Tel: (254) 710-7670
WILMER CUTLER PICKERING HALE Email: james.wren@baylor.edu
& DORR LLP
1875 Pennsylvania Avenue Harry L. Gillam, Jr.
Washington DC 20006 Texas State Bar No. 07921800
Tel: (202) 663-6000 GILLAM & SMITH, L.L.P.
Email: gregory.lantier@wilmerhale.com 303 South Washington Avenue
Email: amanda.major@wilmerhale.com Marshall, Texas 75670
Tel: (903) 934-8450
Email: gil@gillamsmithlaw.com

Attorneys for Intel Corporation

CERTIFICATE OF SERVICE

I hereby certify that all counsel of record who are deemed to have consented to electronic

service are being served with a copy of the foregoing document via electronic mail on April 9,

2021.

/s/ J. Stephen Ravel

J. Stephen Ravel

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