Digital & Integrated Electronics Design

(ELEC143)

Part 2: Integrated Electronics

Lecture 21
Simple Circuit - Inverter
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 In previous lecture…
▪ Discussed different mask layouts for use in photolithography in the
fabrication of n-channel MOSFET, expressed in terms of m with appropriate
a included between them

▪ Designers determine the value of W/L to meet the current requirements.

For layouts, L is defined by the width of the gate strip and W is defined by
the length at which the gate strip overlaps the active area/diffusion region

▪ Today, with the aid of Voltage Transfer Characteristics (VTC) we will discuss
basic operation of an inverter designed using different load configuration
such as:
a. Passive load
b. Saturated load
c. Unsaturated load
d. Depletion

▪ Also discuss possible layouts of two of the inverter configurations above

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Inverter
▪ The simplest logic gate is an inverter where the output is a complement of
its input i.e. ‘NOT’ gate shown below and discussed in Digital Electronics
lectures

Input voltage, Output voltage,

Vin Vout

Vin Vout logic 0 logic 1

(low voltage) (high voltage)
logic 1 logic 0
(high voltage) (low voltage)

▪ Truth table shows the basic operation of the NOT gate. Logic 1 is represented
by a high voltage e.g. supply voltage VDD connected to the circuit, and logic 0 is
represented by a low voltage e.g. 0.1 V (ideally 0 V) depending on the design.
This voltage needs to be less than the threshold voltage VT of a MOSFET

Lets consider the operation of such inverter or NOT gate using different
design configurations of the respective circuit

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i. Inverter with passive load
▪ Earliest digital inverter consisted of an n-MOSFET
VDD
(MD) connected in series with a passive load RL
(refer to passive load slides in lectures 15 and 16)
RL

▪ Here the transistor MD is known as a ‘driver’ and

passive load/resistor RL is the ‘load’
Vout

▪ The gate of the driver MD acts as the input to the G D

inverter such that VGS = Vin, and the Vout from the MD
inverter is measured at the drain side connected
Vin S
to resistor. VDD is the supply voltage (e.g. 5 V)

GND
▪ When Vin is logic 0, MD is off (need at least VT to
be on) and thus no current flows in the inverter.
Circuit configuration of the
However when Vin is logic 1 then MD is on and inverter with n-MOSFET
current flows in the inverter driver and resistor load

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Inverter with passive load
▪ The current flowing in the resistor IR is the same as
VDD
the current in the transistor ID

▪ When the transistor is on, the same drain current flows RL IR

through driver MD and load resistor RL such that,

Vout = VDS
VDD = I D RL + Vout

▪ This equation is known as the load-line equation MD ID

Vin
▪ The value of the output voltage Vout (for logic 0) will
depend on resistance RL and channel resistance of GND
the transistor or the aspect ratio
Circuit configuration of the
inverter with n-MOSFET
▪ We can analyse the performance of the inverter driver and resistor load
using the Voltage Transfer characteristics (VTC) as
in the next slides
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Inverter with passive load
▪ Note the current or resistance RDS of the transistor MD, depends on the
device constant  and/or aspect ratio W/L as shown in drain current
expressions in the last lecture and summarised below

WCo
ID   where =
L

▪ The resistance of the implanted or passive load RL depends on the sheet

resistance and its dimensions L and W (refer passive load lecture slides 16)
as given by the expression below

L
RL = Rsheet
W

▪ Note W and L of MD and RL are not the same as these are different devices
using different processing technology and have different resistance values

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Voltage Transfer Characteristics (VTC) of inverter
▪ The basic operation and performance of an inverter can be described by a
Voltage Transfer Characteristics (VTC), which describes the Vout as a
function of Vin under DC operation

▪ To obtain the VTC of an inverter, the load line is superimposed onto the
output characteristics of the driver transistor (i.e. variation of drain current
with drain voltage), for different gate voltages as discussed in last lecture)

▪ The load line is given by an expression below, i.e. when transistor is off, no
current flow in the inverter (i.e. ID = 0), thus Vout (or VDS) = VDD. However when
transistor is on, as the resistance of the load is greater than the resistance of
the transistor, most of voltage is across the load (resistor)

VDD = I D RL + Vout

▪ The point of intersection between Vout and Vin (particularly when the two are equal)
are obtained and used to plot the VTC as illustrated in the next slide

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 Voltage Transfer Characteristics (VTC) of inverter
Output characteristics (in red) of the driver
VTC of the inverter with a
transistor superimposed to the load line of
passive load
the passive load resistor (in blue)
Enhancement mode n-MOST with L = 3m W = 6m Vout (V)

500 VDD = I D RL + Vout Vin= 5 V VOH VDD

5
Cut off
Drain current, ID (A)

400 VDD/RL 4
Saturated
Vin= 4 V
300 3 dVout
slope =
dVin
200 2
Vin= 3 V Linear

100 1 VOL
Vin= 2 V
Vin= 1 V
0 Vin= 0 V
0
0 1 2 3 4 5
0 1 2 3 4 5 6
VT
Vout (V) VDD Vin (V)

▪ From the VTC, assuming VDD = 5 V, when Vin = 0 V (logic 0) then Vout = VOH = 5 V (logic 1).
Similarly, when Vin = 5 V then Vout = VOL = small voltage (not 0 V), whose value depends on
the value of RL wrt resistance of the driver as discussed further in next slide/s, considering
the different regions of the VTC
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VTC analysis: Region I
▪ When VGS < VT, that is Vin < VT, the transistor is off and very low current
flows then in this case,

VDD Region I
VVo
out
RL IR ~ 0
I
VDD
II
Vout ~ VDD

MD
III
Vin < VT
ViVin
GND VT
VTC analysis: Region II
▪ For VGS > VT, the transistor is on and current
flows. There will be a voltage drop across R, VVo Region II
out
and as such Vo falls
I
VDD
▪ Transistor is initially saturated such that VDS > II
VGS - VT, or Vo > Vi - VT. The drain current is
given as:
III

• The load line equation becomes: Vi

Vin
ID VT

Note: for a steep t.c., R

needs to be large
VTC analysis: Region III
• For VDS < VGS - VT, i.e. Vo < Vi – VT, the MOST
unsaturated and follow:
VVo
out

I
VDD
II
Region III

• Substitute the load line to produce the quadratic III

equation for Vo (Vin) as,
Vi
Vin
VT

• Solve to find Vo for given Vin which corresponds to the voltage Vo2
at logic level 0, and for simplicity can assume: →0
2

• For small Vo (for logic 0), the value of R needs to be large

Power dissipation of inverter with passive load
▪ A maximum current flows in the inverter, when the input is at logic 1, such
that the driver transistor is on and thus there is a direct current path between
VDD and GND. In this case, a maximum dissipated power dissipated through
the load resistor given as:

Pmax = I D VDD

Pmax
(V −V ) V
= DD out DD
Power is inversely proportional to
the load resistor and proportional
RL to the square of supply voltage

▪ From expression above, to obtain low Pmax, RL needs to be large, which is also
needed to achieve an ideal VTC characteristics as discussed in last slide

▪ However, large RL uses larger area on the silicon substrate, which is costly. In
addition the different technology for the driver and load results in more complex
processes which is also costly. And because of such reasons, passive load
was replaced with ‘active’ load (i.e. transistors) as discussed for the next
inverter configuration
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Design trade-offs on choice of R value
VDD
Parameter Value of R

Noise immunity Large for low logic 0 RL

Packing density Small for small area

Power dissipation Large Vout = VDS

Speed Small
MD
Vin
• Poor packing density (R takes up large area),
• High power consumption,
• Slow operation speed…..

…never made it into production

• Passive load was replaced with active load as in next design

ii. Inverter with saturated n-type load
▪ 2nd generation of inverters replaced the passive load VDD
with active load (i.e. transistors) as in the figure

ML
▪ Both driver MD and load ML transistors respectively,
consists of enhancement n-MOSFETs resulting in
compatible fabrication processes and thus lower costs
Vout

▪ For this configuration, the gate capacitance and

mobility of MD and ML can be assumed to be the same
MD
Vin
▪ Also, ML operates in saturation regime since its gate
is tied to the drain, and to the supply rail i.e. VDD = VGS
= VDS. Thus the current through ML follows the
Circuit configuration of an
equation below. Note, if VG is below VT then ML is off, inverter with enhancement nMOS
as will be observed in VTC driver and saturated nMOS load

where

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Inverter with a saturated n-type load
▪ The current through the driver transistor MD, when it is on VDD
will depend on Vin. Such that it operates either in linear or
saturation regime as:
ML
Linear regime

Vout

Saturated regime
MD
Vin

where

▪ Note the current flowing in the inverter is the same

▪ We can determine the VTC for this inverter by plotting the output characteristics
of the driver and superimposing the load line
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 VTC of inverter with saturated active load
Vout (V)

500 5
Non-linear load VDD - VT

400
Drain current (A)

4 MD cut off
ML saturated
300
3
MD saturated
200 ML saturated
2
MD linear
100
1 ML saturated

0
0 1 2 3 4 5 0
Vout (V) 0 1 2 3 4 5
VDD - VT VDD VT Vin (V)

▪ With Vin = 0 V (logic 0), MD is cut-off and thus Vout is at logic 1 however the voltage is equal
to (VDD – VT) rather than VDD. This is a disadvantage as some of the voltage is lost thus
reducing the voltage swing, which also has impact on operational speeds

▪ The gain of the inverter depends on the ratio of  of MD and ML. For same Co and , the
gain becomes dependent on the ratio of the respective aspect ratios i.e. (W/L) D/(W/L)L.
For higher gain (W/L)D >> (W/L)L. However very small (W/L)L also affects the transient
responses as the ML acts as a pull-up for the next stage
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VTC analysis: Region I
VDD Region I
VVo
out
I
VDD
VDD-V
-VTT
II

Vout = VDD - VT

III

Vin < VT Vi

V
Viin
VT

‒ Driver load MOST is off

‒ Output is clamped at VDD – VT
‒ Note that the load is always on - a conducting channel
‒ Always a voltage VT sustained between source and gate - major
disadvantage as noise immunity is reduced
VTC analysis: Region II
▪ In this region, load and driver transistors are
both saturated: same current in each device VVo
out
Region II
I
VDD
VDD-V
-VTT
II

Note the:
III
‒ Gate-source voltage of the load is VDD – Vo
‒ Device constant or aspect ratios (W/L) of Vi
the load and driver are not the same. V
Viin
VT

▪ Equate the currents and re-arrange the equation such that,

VTC analysis: Region II (design issues)
▪ If output voltage is,

Want a steep gradient!

gradient

▪ For steeper slope, load device needs to be designed to have high ‘on-
resistance’ or in other words make the load a weaker device compared
to the driver

▪ This can be achieved by design with L << D for a steep t.c. and a SMALL
voltage for logic 0 (noise immunity)

▪ This is achieved by having an aspect ratio (W/L)load < 1

VTC analysis: Region III
▪ In this region, the load is saturated and
the driver is unsaturated VVo
out

I
▪ Using the appropriate current equations, VVDD- -VVTT
DD
II
equate the currents in driver and load,
such that: Region III

III

Vi
Vin
Vi
▪ Re-arrange to obtain a quadratic equation from VT
which the logic 0 condition can be calculated
for an applied logic 1 (Vi = VDD – VT)

▪ Note and
iii. With unsaturated or linear active load
▪ With this configuration, once again, both driver MD VDD
and load ML are both enhancement n-MOSFET
ML
▪ However in this case, the gate of ML is not tied to
its drain but has a separate or additional power VGG
supply rail VGG. This voltage VGG is greater than
Vout
VDS by VT and thus ML would be on but operating
in linear regime
MD
Vin

▪ This reduces the logic 1 (VOH) problem found with

Circuit configuration of an inverter
the saturated active load with enhancement nMOS driver and
unsaturated nMOS load

▪ However the additional power rail compromises

on the packing density of the circuits on the wafer

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With unsaturated or linear active load
▪ Similar to the last configuration, the current through VDD
the driver transistor MD (when on) will depend on Vin
such that it can operate either in linear or saturation
regime following the respective equations ML

VGG
▪ For the load transistor ML if VGG is greater than VDS
by VT then ML is on operating in linear regime Vout

MD
Vin

▪ Or

▪ Note the current flowing in the inverter is the same

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 VTC of inverter with linear active load
Vout (V)
VDD
500 5
Non-linear load MD cut off
400 ML linear
Drain current (A)

300
3
MD saturated
200 ML linear
2
MD linear
100
1 ML linear

0
0 1 2 3 4 5 0
Vout (V) 0 1 2 3 4 5
VDD VT Vin (V)

▪ Observe the difference with the load line when current is zero. The VTC is similar to the one
with passive load i.e. the logic 1 output is equal to V DD. Overcomes the issue of reduction in
the voltage swing as observed with saturated active load

▪ The gain of the inverter depends on the ratio of  of MD and ML, similar to last configuration

▪ The main disadvantage of this configuration is the additional power supply, which results in
complication in designing (i.e. additional wiring) and overall costs for developing the circuit
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iv. With depletion active load
▪ This design is also known as the nMOS technology
VDD
and it led the way to LSI circuits, with the early
microprocessors developed using this technology D

G ML
▪ This inverter configuration consists of an enhancement
S
n-MOSFET driver MD and depletion n-MOSFET load ML
Vout
▪ For ML, a conducting channel already exists such that
when VGS = 0 V, a current flows between the contacts
when VDS is applied. The conductivity of the channel MD
can be increased by increasing VGS. And the transistor Vin
can be switched off by applying a negative gate voltage

Circuit configuration of an inverter

▪ It can be considered that the threshold voltage of ML with enhancement nMOS driver and
to be negative VTL < 0 whilst threshold voltage of MD is depletion nMOS load

positive VTD > 0

▪ The gate of ML is connected (shortened) to the source (i.e. VGS = 0 V) which

ensures that the transistor is always on
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 VTC of inverter with depletion load
Vout (V)
500
VDD
5
400
depletion mode
Drain current (A)

nMOST 4
300
VGS = 0 V Steeper
3 slope
200
2
100
1
0
0 1 2 3 4 5
VDD 0
Vout (V) 0 1 2 3 4 5
VT Vin (V)

▪ With this configuration, VOH = VDD and the gain is high

▪ Steeper slope is obtained when βL << βD and low output voltage for logic 0
condition

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DC power dissipation
VDD
▪ Note the current in the load transistor is,

VGS = 0V
ML
load ID (max)
I D max = VGS − VT 
2
2
Vout

▪ The maximum d.c. (stand-by) power (logic 0)

dissipation is, MD
Vin
(logic 1)

▪ As VGS(load) = 0 and the load is saturated for this condition

▪ This configuration has small power dissipation however better characteristics

are obtained with the CMOS design which will be discussed in next lecture
Evolution of ‘Ratio-ed’ logic families

Resistive load / Saturated MOST load / Un-Sat. MOST load / nMOS

‒ Need to ‘ratio’ driver and load to ensure a small value for logic 0: Vlogic 0 << VT

‒ Asymmetric switching: weak pull-up device, strong pull-down device

Comparison of load devices
▪ Considered several load configurations including resistor, saturated and
depletion mode devices

VDD
ID
Transient current, i

LOAD LOAD

Vo
M1 M2
VD
VDD - V T VDD (= V o)

0V

• Consider an inverter feeding anther inverter

• As M1 turns off and Vo rises, M2 is turning on
• M1's load device delivers the transient current to turn M2 on
• Depletion load is best as it delivers a constant current over most of switching
transition whilst the Saturated load is the worst in this respect
Problem sheet
An inverter consists of n-MOSFET enhancement VDD
driver with a saturated n-MOSFET load as in Fig. 1.
The supply voltage VDD = 5 V. The transistors have
threshold voltage VT = 0.8 V and o = 350 A/V2.
ML
Determine the:

a) ratio of D /L such that Vin is at logic 1, and thus

Vout is at logic 0, assuming this to be at 0.1 V and Vout
device constant of the load = 1.75  10-4 A/V

b) aspect ratio of the driver and load Vin MD

c) Sketch simple layouts for the inverter assuming

minimum feature size is 0.5µm with appropriate
alignment error (use suitable scaling)
Fig. 1

Note: W W
 = o = ( Co )
L L

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Solution
For this design, Vin (logic 1) is clamped VDD = 5V
at VDD - VT
D

IDL
If both devices are on, equate the currents: ML

𝐼𝐷𝐿 = 𝐼𝐷𝐷 S
Vout = 0.1V
(logic 0)
Load is saturated such that:
Vin = VDD – VT MD IDD

𝛽𝐿 (logic 1)
𝐼𝐷𝐿 = 𝑉𝐺𝑆 − 𝑉𝑇 2
2

𝛽𝐿
or: 𝐼𝐷𝐿 = 𝑉𝐷𝐷 − 𝑉𝑜𝑢𝑡 − 𝑉𝑇 2
(1)
2

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 Solution
What about the driver? Is it operating in linear or saturation?

VDS : VGS – VT 0.1 < 4.2 – 0.8

VDD = 5V

𝑉𝐷𝑆 2 D
𝐼𝐷𝐷 = 𝛽𝐷 𝑉𝐺𝑆 − 𝑉𝑇 𝑉𝐷𝑆 −
2 ML IDL

or: 𝑉𝑜𝑢𝑡 2 S
𝐼𝐷𝐷 = 𝛽𝐷 𝑉𝑖𝑛 − 𝑉𝑇 𝑉𝑜𝑢𝑡 − (2) Vout = 0.1V
2
D (logic 0)

Vin = VDD – VT MD IDD

Equate (1) and (2),
(logic 1)
S

𝛽𝐿 2
𝑉𝑜𝑢𝑡 2
𝑉 − 𝑉𝑜𝑢𝑡 − 𝑉𝑇 = 𝛽𝐷 𝑉𝑖𝑛 − 𝑉𝑇 𝑉𝑜𝑢𝑡 −
2 𝐷𝐷 2
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Solution
Substitute the values,

𝛽𝐿 2
0.12
5 − 0.1 − 0.8 = 𝛽𝐷 4.2 − 0.8 0.1 −
2 2
𝛽𝐿 8.4 = 𝛽𝐷 0.335

𝜷𝑫
≈ 𝟐𝟓
𝜷𝑳

𝛽𝑜 𝑊ൗ𝐿
𝐷
= 25
𝛽𝑜 𝑊ൗ𝐿
𝐿

𝑊ൗ = 25 𝑊ൗ𝐿
𝐿 𝐷 𝐿
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Solution
Such that if:
𝑊ൗ = 1 then 𝑊ൗ = 25
𝐿 𝐿 𝐿 𝐷

or 𝑊ൗ = 0.5 then 𝑊ൗ = 12
𝐿 𝐿 𝐿 𝐷

Etc…..

Need to select appropriate values such that we are utilising small area
and also allows us to include alignment error.

Lets assume the 2nd option, if m = 0.5 µm then we can select the
following respective values:

WL = 5  m LL = 10 m WD = 12 m LD = m

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 Designing layouts for the inverter
▪ Designing complete layouts for simples inverters or complex integrated circuits
can be overwhelming

▪ Stick diagrams are typically initially used to assist in planning the layout. They
are abstract diagrams between transistor schematic and respective layouts, and
are not necessarily presented to scale. Simply replace the rectangles of the
layouts with lines (color coded) with x representing contacts to be made

VDD VDD (blue)

X

VG (red) X

Vout Vout (blue)

X Blue – metal
Red – Polysilicon gate
Vin Vin (red) X
Green – n diffusion/active area
X
GND (blue)

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 Example of the sketch of the layout of an
inverter with active load
▪ With the aid of stick diagram, actual layouts can be drawn to scale using
appropriate m and a between layouts as discussed in last lecture. For the metal
lines connecting the devices, and to VDD or GND, the width and length of these
lines also need to be expressed in terms of m

▪ For the circuit in the example earlier,

a possible rough sketch of the layout
is shown in the diagram on right-hand X
side, where (W/L)D > (W/L)L
X

▪ Note this is a rough sketch as it is not X

to correct scaling and also does not
include all the alignment errors
X

▪ For the design coursework, you need X

to make sure all layouts are presented X
to scale and include all the necessary
alignment error, including spacing
between devices and metal lines

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Example of the sketch of the layout of an
inverter with passive load
▪ Also consider an inverter with a passive load (p-n junction), in order to draw
layouts for the inverter, the respective values for W and L for each device need
to be determined

VDD
For the passive load, the number of
squares depends on the value of
resistance required. Each square is
RL given by minimum feature size.
Note the serpentine uses less area
compared to linear layout
(refer to p-n junction notes)
Vout

Vin
RDS
Dimensions for W and L for the
driver transistor is not the same
as those for the passive load

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Next lecture

Lecture on

CMOS inverters

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