EE5143_Lab2_LabReport 29 January 2017

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Brandon Laserna
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EE 5143
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29 January 2017
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 EE5143_Lab2_LabReport 29 January 2017

I. Objective

The objective of this lab was to become familiar with the basics of Xilinx Vivado. To do so
we were proved the code for a 4-bit adder. We were then walked through the procedures for
implementing the program on the Basys3 board.

II. Introduction

The Basys3 is an FPGA with several I/O devices and supporting hardware to make the
use of the FPGA more convenient and robust. The board is meant to be programmed with the

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Xilinx Vivado software, which is an FPGA logic-synthesis and optimization tool. This lab was

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meant to be an introduction to Xilinx Vivado and to implementing VHDL code onto the Basys3

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board as a functional circuit. The lab procedure provided screenshots to walk through the steps of

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creating a project, adding a source file, synthesizing the design, adding I/O constraints,
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generating the bitstream, and finally programming the Basys3 board. Code was also provided to
describe a 4-bit adder and to constrain the I/O ports.
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III. Procedure
1. Create an RTL project compatible with the Basys3 board entitled “lab2”
2. Add a new VHDL source file to the newly created project entitled “adder”
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3. Copy and paste the provided code for a 4-bit adder

4. Synthesize the “adder” file and view the RTL schematics
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5. Add constraints file “pin_io” to “adder” file to define the I/O ports
6. Copy and paste the provided code for the I/O ports
7. Generate bitstream file
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8. Connect Basys3 board and detect board in Vivado

9. Program the Basys3 board with “adder” file
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10. Observe that Basys3 board works as 4 bit adder with specified I/O ports

IV. Problems
There were no problems encountered. Because this was an introductory lab with provided
screenshots and code, there was not much room for error.

V. Results

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 EE5143_Lab2_LabReport 29 January 2017

The results of this lab were as expected. After following the instructions and
programming board with a 4-bit adder, the board performed as a 4-bit adder. To confirm I was
able to perform 1+1=2, 1+2=3, and 5+10=15.

VI. Conclusion

This lab served well as an introduction to Vivado and the Basys3 board. After setting up
the project and program files, it was very easy to program the board with the provided code.
There were no issues or errors during the lab. The 4-bit adder worked as expected with the
proper I/O ports. It was very satisfying seeing the board work as intended. It was also interesting

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viewing the schematics of the circuit that the program was simulating. It made it much easier to

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picture what was actually happening on the board rather than just relying on the code. The basics

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of Vivado have certainly been established and I am confident in my ability to accomplish the
upcoming labs. rs e
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 EE5143_Lab2_LabReport 29 January 2017

Appendix

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Figure 1 – RTL Schematic

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Figure 2 – Netlist Schematic

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