Ex.

No: 6 Date: 22/04/2021

Design of Half Adder and Full Adder Circuits

Aim: To verify circuit and truth table of Half Adder and Full Adder
circuits using PSpice simulation.

Apparatus/Tool required:
ORCAD / PSpice simulator - > EVAL Library – 7408, 7432 & 7486
Source Library - Digclock
Simulation Settings: Analysis Type - Time Domain
Run to time: 4ms (for Half Adder)
Run to time: 8ms (for Full Adder)
Circuit Diagram:

Half – Adder Circuit

O F F T IM E = 2 m S D S T M 1 U 1A
O N T IM E = 2 m S C LK 1
D ELAY = 3 S = A B
S TA R TV A L = 0 2
O PPVAL = 1
7486
O F F T IM E = 1 m S D S T M 2
O N T IM E = 1 m S C LK
D ELAY =
S TA R TV A L = 0
O PPVAL = 1
U 2A
1
3 C = A . B
2

7408

Full – Adder Circuit

O F F TIM E = 4 m S D S T M 3 U 3A
O N T IM E = 4 m S C LK 1 U 4A
D ELAY = 3 1 S = A  B  C
S TAR TVAL = 0 2 3
O PPVAL = 1 2
7486
O F F TIM E = 2 m S D S T M 4 7486
O N T IM E = 2 m S C LK
D ELAY =
S TAR TVAL = 0
O PPVAL = 1 U 6A
1
O F F TIM E = 1 m S D S TM 5 3
O N T IM E = 1 m S CLK 2
U 7A
C = (A  B ) . C + A·B
D ELAY =
S TAR TVAL = 0 7408 1
O PPVAL = 1 3
U 5A 2
1
3 7432
2

7408
Theory:

Half Adder Circuit:

1. Circuit Diagram

2. Truth Table
S=A
A B C=A.B
B
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

Model Timing Diagram:

Half – Adder

1
Full Adder Circuit

1. Circuit Diagram

2. Truth Table
A B C S=ABB C= (AB).C+A.B

0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

Model Timing Diagram:

Full – Adder

2
3
Simulation Circuit and Output (Both Waveform and Truth
Table)
1. Half Adder
a) Circuit Diagram:

b) Waveform:

4
c) Truth Table:

S=A
A B C=A.B
B
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

2. Full Adder
a) Circuit Diagram:

5
b) Waveform:

c) Truth Table:

A B C S=ABB C= (AB).C+A.B

0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

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Procedure:

1. Open Pspice software & create a new project.

2. Take digital logic gates from the eval library and digclock from
source library.
3. Place all logic gates, as given in circuit diagram of Half Adder
and Full Adder respectively and connect the digclock.
4. Now create a simulation profile and name it in the transient mode
and keep time=2us for Half Adder.
5. Now enable voltage pins and run the program to get the graph.
6. Edit simulation profile and change time=4us for Full Adder.
7. Repeat step, by placing the voltage pins and run the program to
the graph.

Inference:

Truth table for Half Adder and Full Adder circuits are verified using
PSpice simulation.

Reg. No: 20MID0209 Name: SHARAN R B Date: 22/04/2021