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ELL 100 Introduction To Electrical Engineering: Ecture
ELL 100 Introduction To Electrical Engineering: Ecture
2
RECAP OF
VARIOUS
LOGIC GATES
3
LOGIC NETWORKS
Logic gates can be interconnected to give a wide variety of functions.
A (A C)
B F=(A C)+B
C (A+B)
A
F=(A+B) (B+C)
B
C (B+C)
4
BOOLEAN IDENTITIES
A F=1 F=0 A F=1
A+1=1 A 0 0A A+A 1
1 0 A
5
RULES OF COMBINATIONAL LOGIC
Laws of Boolean Algebra (‘+’ denotes ‘OR’, ‘AB’ denotes ‘A AND B’)
a) Commutative rules: A+B = B+A ; AB = BA
7
Laws of Boolean Algebra used for simplifying logical expressions
(Al = Ā denotes the complement/inverse/NOT of A)
A0 A ( Al )l A
A 1 A A AB A
A0 0 A A B A B
l
A 1 A A B B A
A A A A B B A
A A 1 l
A B A B
A A A A B A B
A A 0
l
( A B )( A C ) A BC 8
HALF ADDER CIRCUIT
Takes two binary digits A and B as inputs. A B
Gives out sum S and carry C bits as outputs.
1-bit
C
Half Adder
C AB
S A B AB A B
l l
S
9
HALF ADDER CIRCUIT
A
Bl
SS A B AB
l l A
C AB
C
B
Al
B
A
B
SS A B
C
C AB
10
FULL ADDER CIRCUIT
Half Adder accepts only 2 input bits. If two n-bit binary numbers are to be
added, there can be a carry bit in various places also.
Full Adder makes provision for a carry-in bit also i.e. total 3 input bits.
A B
(Carry-out) (Carry-in)
1-bit
Co Ci
Full Adder
(Sum)
S 11
FULL ADDER CIRCUIT (SUM)
A
B S
Ci
S A B Ci A B Ci A B Ci
l
12
FULL ADDER CIRCUIT (CARRY OUT)
B
Co
Ci
1-bit
Bo
Half Subtractor
Bo A Bl
D A B AB A B
l l
D 14
HALF SUBTRACTOR CIRCUIT
A
D A B AB A B
D l l
A
Boo Al B
B
B
15
FULL SUBTRACTOR CIRCUIT
Performs subtraction of two bits, taking into account borrow of the previous
adjacent lower bit also. Has three inputs A, B and Bi, denoting the minuend,
subtrahend, and previous borrow, respectively. The two outputs, D and Bo
represent the difference and output borrow.
A B
1-bit
Bo Bi
Full Subtractor
D 16
FULL SUBTRACTOR CIRCUIT (DIFFERENCE)
A
B D
Bi
D A B Bi A BB AB B ABBi
l l l
i
l l
i
l
D A B Bi 17
FULL SUBTRACTOR CIRCUIT (OUTPUT BORROW)
A
B
Bo
Bi
Bo A B Bi A BB A BBi ABBi
l l l
i
l l
Bo A ( B Bi BB ) BBi ( A A )
l l
i
l l
Bo A ( B Bi ) BBi
l
18
SOLVED EXAMPLES
Q. Using Boolean algebra techniques, simplify this expression:
F = AB + A(B + C) + B(B + C)
B B+AC
AB+A(B+C)+B(B+C)
B
C A
C
19
SOLVED EXAMPLES
Q. Minimize the following Boolean function using algebraic manipulation:
F=ABCllD
Dll+ABC l
+ABCl D+AB l ll
D+ABl CCD+ABCD+AB l l
D+ABCD+AB l l
CD+ABCD
CD+ABCD +AB l l l l
+ABCDCD
Soln: F ABCl (D+Dl )+ABl Cl D+ACD(B+Bl )+ACD l (B+Bl )
F ABCl ABl Cl D ACD ACD l
F ABCl ABl Cl D AC( D D l )
F ABCl ABl Cl D AC
F = A(C+BCl ) ABl Cl D
F A(C B ) ABl Cl D
F AC AB ABl Cl D
F AC A( B Bl Cl D)
F AC A( B Cl D) AC AB ACl D A(C Cl D) AB
F A(C D ) AB AC AD AB 20
SOLVED EXAMPLES
Q. Apply de Morgan's theorems to the following expressions:
(a) F A BC D ( E F ) (b) F AB C D EF
Soln:
(a) F A BC D( E F ) (b) F AB C D EF
F A BC D ( E F ) A BC D ( E F )
F AB C D EF
F A BC D E F F A B C D E F
F A B C D E F
21
SOLVED EXAMPLES
Q. Draw the circuit to implement the function F A B A C
Simplify this function and hence redraw the reduced circuit.
A A B
Soln: F A B AC
F A B AC
B
A B AC
F A B AC C
AC
F A B C
A
B
A B C
C
22
SUM OF PRODUCTS (SOP) FORM
Two or more “product” (AND-gated) terms are “summed” (OR-
gated) to form a Boolean expression.
a. A B C A B C
b. A A C ( A B )
27
Canonical Forms of Boolean Expressions
The various possible standard product (AND) terms are called “minterms”,
while the standard sum (OR) terms are called “maxterms”.
N input variables (bits) can be combined to form 2N minterms or 2N maxterms,
designated by their decimal equivalents (bits are assigned values such that each
minterm yields value 1 while each maxterm yields value 0)
X Y Z minterm designation maxterm designation
0 0 0 𝑋𝑌𝑍 𝑚𝑜 𝑋+𝑌+𝑍 𝑀𝑜
0 0 1 𝑋𝑌𝑍 𝑚1 𝑋+𝑌+𝑍 𝑀1
Note that each maxterm
0 1 0 𝑋𝑌𝑍 𝑚2 𝑋+𝑌+𝑍 𝑀2
is the complement
0 1 1 𝑋𝑌𝑍 𝑚3 𝑋+𝑌+𝑍 𝑀3
(inverse) of the
corresponding minterm
1 0 0 𝑋𝑌𝑍 𝑚4 𝑋+𝑌+𝑍 𝑀4
1 0 1 𝑋𝑌𝑍 𝑚5 𝑋+𝑌+𝑍 𝑀5 i.e. mi = Mi’
1 1 0 𝑋𝑌𝑍 𝑚6 𝑋+𝑌+𝑍 𝑀6 (from de Morgan’s laws)
1 1 1 𝑋𝑌𝑍 𝑚7 𝑋+𝑌+𝑍 𝑀7 28
Canonical Forms of Boolean Expressions
Example: We can write the expression for function F using the truth table below
X Y Z F
0 0 0 0
F X YZ X Y Z XYZ (SOP form using minterms:
collect all the terms which
0 0 1 1 F m1 m4 m7 give F = 1)
0 1 0 0
X Y Z X Y Z X Y Z
0 1 1 0
1 0 0 1 F X Y Z X Y Z
F M 0 M 2 M 3M 5M 6
1 0 1 0
1 1 0 0
1 1 1 1 (POS form using maxterms: collect all the terms which give F = 0)
F XY X Z
F XY X XY Z X X Y X X Z Y Z
F Y X X Z Y Z X X 1
F X Y Z Z X YY Z X X Y Z ( X X 0)
)
F X Y Z X Y Z X Y Z X Y Z X Y Z X Y Z X YY ( X Y )( X Y )
F X Y Z X Y Z X Y Z X Y Z ( XX X )
F M 4M 5M 0M 2
F ( X , Y , Z ) (0, 2, 4,5)
F ( X , Y , Z ) (1,3, 6, 7)
31
EXERCISES
32
KARNAUGH MAP (K-MAP)
Karnaugh maps are a powerful, widely used, tabular method of logic
simplification that are used to find the simplest SOP or POS form.
Each cell in the Karnaugh map corresponds to one line in the truth table.
33
KARNAUGH MAP (K-MAP)
Steps to simplify a logic expression using a Karnaugh map are:
1. Draw the empty Karnaugh map.
2. Fill in 1’s and 0’s into the corresponding cells. (using the original
logic expression or it’s truth table.)
3. Identify and draw loops on the Karnaugh map to group together
adjacent 1’s (for SOP form) or adjacent 0’s (for POS form).
4. Create the expression for each group and combine to give the
simplified logic expression. 34
KARNAUGH MAP (K-MAP)
1. Creating an empty Karnaugh map
The number of inputs N defines the number of cells (2N) in the
Karnaugh map to be drawn.
e.g. for two variables, A and B, there are four possible input states i.e.
00, 01, 11 and 10. Hence, the K-map will have 4 cells, each cell
corresponding to one particular input state.
The small numbers in the top left corner of each cell show the decimal
equivalent of the binary input code for that cell. Notice that the cells are
arranged such that only 1-bit changes when we go to an adjacent cell.
Each cell thus corresponds to one particular minterm mi or maxterm Mi,
where i is the decimal equivalent denoting the cell.
35
Two-variable K-map Three-variable K-map Four-variable K-map
F = f(A,B) F = f(A,B,C) F = f(A,B,C,D)
A
A CB 0 1 BA
DC 00 01 11 10
B 0 1 0 1
00 0 1 3 2
0 1 00
0 2 3
01 4 5 7 6
01
2 3 6 7
1 11 12 13 15 14
11
4 5
10 8 9 11 10
Truth table for two variables 10
BA
C 00 01 11 10
0 1 3 2
0
4 5 7 6
1
KARNAUGH MAP
2. Filling in the Karnaugh map
Each cell of the Karnaugh map is filled with either a 1 or a 0
signifying the output for the input corresponding to that cell.
AB 0 1
A A( B B )(C C ) AB AB C C ABC ABC ABC ABC
The second term is expand as, 00 1 1
AB AB (C C ) ABC ABC
01 1 1
The standard SOP expression is given as,
ABC ABC ABC ABC ABC ABC ABC 11 1
42
KARNAUGH MAP
3. Creating groups in Karnaugh maps
When all the output values are entered, all of the 1’s (or all of the 0’s,
depending on if SOP or POS form is finally required, respectively) must
be grouped together according to the following rules:
43
KARNAUGH MAP
3. Creating groups in Karnaugh maps
• Each cell with output 1 (or each cell with output 0; for SOP or POS) must
be included in at least one group.
• The groups may overlap, so one cell may be included in several groups,
but any group that has all its elements included in other groups can be
ignored.
• There may be several correct minimal forms for a given logic function,
dependent upon the particular groupings that are chosen.
• Once the groups have been assigned, a logic expression can be created.
For each group, write down the common inputs (AND/product terms if
using 1s; OR/sum terms if using 0s) that describe that specific group and
combine accordingly (SOP or POS). 44
SOLVED EXAMPLES
Q. Simplify F ABC ABC ABC
into simpler SOP form using K-map C C
C
AB 0 1
AB 00
AB 01 1 AB
F AB BC
BC 11 1 1
AB
AB 10
SOLVED EXAMPLES
Q. Simplify F m(1, 2,3, 6)
into simpler SOP form using K-map C C C
AB 0 1 Group
1
AB 00
Group 1 AC 1
Group 2 BC AB 01 1 1
Group 2 11 1
AB
F AC BC
AB 10
SOLVED EXAMPLES
Q. Simplify F m(2,3, 4,5, 7,8,10,13,15)
Group
into simpler SOP form using K-map CD CD CD CD
CD 3
AB 00 01 11 10
Group
AB 00
1 BD 1 1
2 ABC AB
01 1 1 1
Group 2
3 BC D Group
AB 11 1 1 1
4 ABD Group
AB 10 4
1 1
Group
F BD ABC BC D ABD Group 4
3
SOLVED EXAMPLES
Q. Simplify F m(0,5, 7,8,10,12,14,15)
Group
5
into simpler SOP form using K-map CD CD CD CD CD
AB 00 01 11 10
Group Group
AB 00
1 ABD 1
1
2 ABC AB 01
1 1
Group
3 AC D 2
4 AC D AB 11 1 1 1
Group 4
4 BC D AB 10 1 1
Group
F ABD ABC AC D AC D BC D 5
Group
3
SOLVED EXAMPLES
Q. Use a Karnaugh map to find the minimum SOP expression of the
function: f ( A, B, C , D) m(0, 2,5, 7,8,10,13,15)
Group
CD CD CD CD CD 2
AB 00 01 11 10
AB
00 1 1
Group
Group Group 2 AB 01
1
1 1
1 BD
AB 11 1 1 Group
2 BD 2
AB 10 1 1
2 BC A+B 01
0 0
A+B
11 0
Group 2
F A BC A+B 10
SOLVED EXAMPLES
Q. Use K-maps to convert the following standard POS expression into:
a) a minimum POS expression, b) a standard SOP expression, and
c) a minimum SOP expression.
F ( A B C D )( A B C D )( A B C D )( A B C D )( A B C D )( A B C D )
Group 3
a) CD C+D C+D C+D C+D
AB 00 01 11 10 Group
Group
1
1 A B C A+B 00 0 0 0
2 B C D A+B 01 0
3 B C D A+B 11 0
Group 2
B C D B C D
10 0
SOP: F A B C
Minimum POS: A+B
Group
3
b) The remaining cells are filled with 1s. CD CD CD CD CD
AB 00 01 11 10
Sum all the minterms corresponding to
these cells with output 1 to get the AB 00 1 0 0 0
standard SOP expression as:
AB 01 1
F = ∑(0000, 0101, 0111, 0110, 1101, 0 1 1
+ ABCD + ABCD
52
c)
Group
4
Group CD CD CD CD CD
1 BD AB 00 01 11 10
AB
2 BC 00 1 Group
Group 1 2
3 AC
AB 01
4 BC D 1 1 1
AB
11 1 1 1 Group
3
Minimum SOP: F BD BC AC BC D
AB 10 1 1 1
Group
4 53
KARNAUGH MAP
"Don't Care" Conditions
Sometimes a situation arises in which some input variable
combinations are not allowed. For example, in a particular coding
scheme with 4 input bits called “BCD”, there are six invalid
combinations: 1010, 1011, 1100, 1101, 1110, and 1111.
Since these unallowed states will never occur in for that particular
application, they can be treated as "don't care" terms with respect
to their effect on the output. That is, for these "don't care" terms
either a 1 or a 0 may be assigned to the output: it really does not
matter since they will never occur.
54
KARNAUGH MAP
"Don't Care" Conditions
Y ABC ABCD
0011 0 10 1 1 X X
0100 0
0101 0 1
0110 0 CD
0111 1 AB 00 01 11 10
1000 1 With "don't cares"
00
1 A
1001 1
1010 X 2
01 1
1011
1100
X
X
1 2 BCD
11 X X X X
1101 X
1110 X
Y A BCD
10 1 1 X X
1111 X
56
CD 2
"Don't Care" Conditions AB 00 01 11 10 Without "don't cares"
Example: POS form 00 0 0 0 0
1 A C
Inputs Output 3 2 A B
ABCD Y
0000 0
01 0 0 0 23 A C D
0001 0 1
11 X X
X X
0010 0
Y A C A B A C D
0011 0
10 X X
0100 0
0101 0
0110 0 CD 2
0111 1 AB 00 01 11 10 With "don't cares"
1000 1
00 0 0 0 0 1 A C
1001 1
1010 X 3 2 A B
01 0 0 0
1011 X
3C D
1100 X 1
11 X X X X
1101 X
1110
1111
X
X
10 X X
Y A C A B C D
57
EXERCISES
Q. Use Karnaugh maps to find the minimum SOP and POS expressions for the
function f ( x1 ,....x4 ) x1 x3 x4 x3 x4 x1 x2 x4 x1 x2 x3 x4 , assuming that there are
also don’t-cares defined as D (9,12,14)
Q. Using K-maps, determine the minimum SOP and POS expressions for the
function f ( x1 , x2 , x3 , x4 ) m(4, 6,8,10,11,12,15) D(3,5, 7,9)
58
EXERCISES
Q. Draw the Karnaugh map and determine the minimum-cost SOP and POS
expressions for the function f ( P, Q, R, S ) m(0, 2,5, 7,8,10,13,15)
Q. Draw the Karnaugh map and determine the minimum-cost SOP and POS
expressions for the function f ( A, B, C , D) (3,5, 7,8,10,11,12,13)
59
EXERCISES
Q. Write an SOP expression for this truth
table, and then draw a gate circuit diagram
corresponding to that SOP expression
60
EXERCISES
Q. Examine this truth table and then write
both the SOP and POS standard Boolean
expressions describing the output.
61
EXERCISES
62
EXERCISES
63
EXERCISES
64
References
E. Hughes, J. Hiley, K. Brown, and I. M. Smith,
“Electrical and Electronic Technology,” Pearson
Education Limited, England, 2008.
65