Chapter 4

Junction Field Effect Transistor

Theory and Applications
_____________________________________________
4.0 Introduction
Like bipolar junction transistor, junction field effect transistor JFET is also a
three-terminal device but it is a unipolar device, which shall mean that the
current is made of either electron or hole carrier.

The operation of JFET is controlled by electric field effect. Thus, JFET is a

voltage-controlled current source device, whereas BJT is a current-controlled
source device.

There are two types of JFET namely n-channel and p-channel. n-channel
type means the carrier type in the conducting channel is electron. Likewise, for
p-channel type, the carrier type in conducting channel is hole.

JFET has three terminals, which are gate G, drain D and source S. The gate
is used to control the flow of carrier from source to drain. Source is the terminal
that emits carrier and the drain is the terminal that receives carrier.

The structures of n-channel and p-channel JFET are shown in Fig. 4.1.

(a) n-channel JFET (b) p-channel JFET

Figure 4.1: The structures of n-channel and p-channel
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The symbols of n-channel and p-channel JFETs are shown in Fig. 4.2.

(a) n-channel JFET (b) p-channel JFET

Figure 4.2: Symbols of n-channel and p-channel JFET

4.1 Biasing the JFET

In normal operation, the gate of JFET is always reverse-biased. Thus, an n-
channel type, the gate is biased with negative voltage i.e. gate voltage is less
than zero volt VG < 0, whilst for p-channel type, the gate is biased with positive
voltage i.e. gate voltage is greater than zero voltage VG > 0.

The source and drain are biased according to the channel type or carrier
type. If it is an n-channel JFET (electron as carrier), the source is biased with
negative voltage while the drain is biased with positive voltage. Alternatively, it
can be biased such that the drain voltage VD is greater than the source voltage
VS. i.e. VD > VS.

If it is a p-channel JFET (hole as carrier), the source is biased with positive

voltage while the drain is biased with negative voltage. Alternatively, it can be
biased such that the drain voltage VD is less than the source voltage VS. i.e. VD
< VS.

Figure 4.3 shows the bias condition for an n-channel JFET.

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 4 Junction Field Effect Transistor Theory and Applications

Figure 4.3: Bias connection for n-channel JFET

4.2 JFET Characteristics and Parameters

Figure 4.4 shows the drain current characteristics of a JFET for gate-to-source
voltage equal to 0V. i.e. VGS = 0.

Figure 4.4: JFET drain characteristics curve for VGS = 0

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Between point A and B, it is the ohmic region of the JFET. It is the region
where the voltage and current relationship follows ohm's law. At point B, the
drain current is at maximum for VGS = 0 condition and is defined as IDSS. It is
the pinch-off point, where there is no increase of current as drain-to-source
voltage VDS is further increased. The VDS voltage at this point is called pinch-off
voltage VP. It is also the voltage point where drain-to-gate voltage VDG produces
enough depletion thickness to narrow the channel so that the resistance of the
channel will increase significantly. Since VGS = 0, VDS is also equal to VDG.
Thus, in general the pinch-off voltage Vp is

Vp = VDS(P) - VGS (4.1)

where VDS(P) is the pinch-off drain-to-source voltage for a VGS value. IDSS and VP
are constant values listed by the manufacturer for a given JFET type, which are
the drain current and pinch-off voltage at gate-to-source voltage VGS = 0.

At point C, the JFET begins to breakdown where the ID increases rapidly

and it is an irreversible breakdown.

Different value of VGS produces different drain characteristic curve. For n-

channel JFET, as VGS decreases, ID current and VDS(P) decreases. There is a VGS
value that no drain current ID is registered irrespective of the drain-source
voltage VDS. This gate-to-source voltage VGS is the cutoff gate-to-source voltage
VGS(off). Since there is no ID current, VDS must be zero. Thus, from equation (4.1)
VGS = -VP. Equation (4.1) can also now be written as VDS(P) = VGS – VGS(off).

Figure 4.5: Drain characteristics of n-channel JFET of different VGS

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 4 Junction Field Effect Transistor Theory and Applications

At ohmic region of the drain characteristic curve for n-channel type follows
equation (4.2a), which is

W
I D = AqN D µ n E X = 2bqN D µ n  VDS (4.2a)
L

where A is the effective cross sectional area of the channel for a given VGS
voltage and b is the effective channel width for a given gate-to-source voltage
and zero drain current. At gate-to-source voltage equals to zero volt i.e. VGS = 0
volt, the effective channel width b is equal to h. Thus, the channel on-resistance
1 L
is defined as rDS( on ) = ⋅ .
2 hqN D µ n W

The pinch-off curve follows equation (4.2b), which is

2
 V 
ID = IDSS 1 − DS( P )  (4.2b)
 VP 

Figure 4.6 shows the set-up for obtaining cut-off condition whereby the drain
current ID is equal to zero.

Figure 4.6: Condition for cutoff of an n-channel JFET

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4 Junction Field Effect Transistor Theory and Applications

Example 4.1
For the JFET circuit shown in the figure, VP = 8.0V and IDSS = 12.0mA. (a)
Determine the value of VDS when pinch-off begins. (b) If the gate is grounded,
what is the value of ID for VDD = 12.0V when VDS is above pinch-off?

Solution
From the circuit, VGS = -5V and apply equation (4.1),

VDS(P) = VP + VGS
= 8V + (-5V)
= 3V
The VDS voltage when pinch-off occurred is 3.0 V.

When the gate is grounded, VGS = 0V, the drain current ID is equal to IDSS =
12mA. For any value of drain-to-source voltage VDS above pinch-off voltage of
8V, the drain current ID remains as IDSS = 12.0mA. This is true as long as the
drain-to-source voltage VDS is below breakdown voltage.

4.2.1 Transfer Characteristics

The transfer characteristic of an n-channel JFET is shown in Fig. 4.7. At gate-

to-source voltage VGS = 0, the drain current ID is equal to IDSS and at gate-to-
source voltage VGS(off), drain current ID = 0.

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 4 Junction Field Effect Transistor Theory and Applications

Figure 4.7: Transfer characteristics curve of an n-channel JFET

The curve is a parabolic curve, which can be expressed mathematically as

2
 VGS 
I D = I DSS 1 −  (4.3)
 VGS( off ) 

4.2.2 Forward Transconductance

The forward transconductance gm of the JFET is defined as the change of drain
current for a given change in gate-source voltage VGS and it is expressed as

∆I D
gm = (4.4)
∆VGS

From the transfer characteristic curve, one will realize that the transconductance
of the device is at maximum when VGS is at zero voltage. The value of gm at VGS
= 0 is always given in the manufacturer data sheet of the device, which is
denoted as gm0. If gm0 is given, gm for a given VGS can be calculated from
equation (4.5).
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4 Junction Field Effect Transistor Theory and Applications

 VGS 
g m = g m0 1 −  (4.5)
 VGS( off ) 

Equation (4.5) can be derived from equation (4.4) by differentiating drain

current with respect to gate-to-source voltage i.e. dID/dVGS.

dI D 2I DSS  VGS 
gm = =− 1 −  (4.6)
dVGS VGS( Off )  VGS( off ) 

Comparing equation (4.5) and (4.6), gm0 shall be

2I DSS
g m0 = − (4.7)
VGS( off )

Thus, given the values of IDSS and VGS(off), the transconductance of the device at
VGS = 0 can be determined.

From equation (4.3) and (4.5), transconductance gm can be expressed as

g m = g m0 I D / I DSS (4.8)

Thus, the transconductance gm of JFET for a given drain current ID value, can be
obtained.

4.2.3 Input Impedance

Since the gate of JFET is reverse-biased, the input impedance is very high. This
is one advantage of JFET over bipolar junction transistor. In JFET data sheet,
the input impedance is given by gate reverse current IGSS for a given gate-source
voltage VGS. Thus, input impedance can be expressed as

VGS
R IN ( gate ) = (4.9)
I GSS

4.3 dc Biasing JFET

The purpose of biasing the device is to select the right dc gate-to-source voltage
for the JFET in order to establish a desired value of drain current. Listed here
are some standard methods.
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4.3.1 Self-Biasing of JFET

The self-biasing circuits for n-channel and p-channel JFET are shown in Fig.
4.8. The gate of the JFET is connected to the ground via a gate resistor RG.

(a) n-channel JFET (b) p-channel JFET

Figure 4.8: Self-biasing of JFET

The gate voltage VG is closed to zero since the voltage dropped across RG by
IGSS can be ignored. Thus,

VGS = VG - VS (4.10)

From Fig. 4.8(a), VS = IDRS and VG = 0

VGS = 0V - IDRS

and

VGS = + IDRS for p-channel JFET

The drain-source voltage VDS is

VDS = VD -VS
= VDD - IDRD -IDRS
= VDD - ID(RD + RS) (4.11)
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4 Junction Field Effect Transistor Theory and Applications

As mentioned earlier, the purpose of biasing is to select the right dc gate-source

voltage for the JFET to establish a desired value of drain current. Once it is
established. The source resistance RS can be calculated using equation (4.12).

VGS
RS = (4.12)
ID

Example 4.2
Determine the value of RS required to self-bias an n-channel JFET with IDSS =
25mA, VGS(off) = -10V, VGS = -5V and its transconductance gm.

Solution
Drain current ID at gate-to-source VGS = -5V is
2
 VGS   − 5V 
2

ID = IDSS 1 −  = 25mA 1 − = 6.25mA

 VGS( off )   − 10V 

The source resistance RS is

VGS 5V
RS = = = 800Ω
ID 6.25mA

2I DSS 2 x25mA
Transconductance gm at VGS = 0, g m0 = − =− = 5mA / V
VGS( off ) − 10V

Thus, the transconductance gm at ID = 6.25mA is,

g m = g m0 I D / I DSS = 5mA / V 6.25mA 25mA = 2.5mA / V

4.3.2 Mid-point Bias

The purpose of midpoint bias is to allow maximum drain current ID swing. From
the drain transfer characteristic curve, the midpoint bias occurred at drain
current ID corresponds to IDSS/2 and at approximately gate-to-source voltage VGS
equals to VGS(off)/4. Indeed when drain current equals to ID = IDSS/2, gate-to-
source voltage is VGS = 0.29 time of gate-to-source cutoff voltage VGS(off). The
illustration is shown in Fig. 4.9.

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 4 Junction Field Effect Transistor Theory and Applications

Figure 4.9: The transfer characteristic curve showing midpoint-bias values for JFET

4.3.3 Voltage Divider Bias

An n-channel JFET with voltage-divider bias is shown in Fig. 4.10. The voltage
at the source of the JFET must be more positive than the voltage at the gate in
order to keep the gate-source junction reverse-biased.

The source voltage VS is

VS = IDRS (4.13)

The gate voltage VG is set by resistors R1 and R2 and is expressed by the

following equation using voltage-divider concept.

 R2 
VG =  V (4.14)
 R 1 + R 2  DD

The gate-to-source voltage VGS is VGS = VG - VS

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4 Junction Field Effect Transistor Theory and Applications

Thus,

 R2 
VGS =   V - IDRS (4.15)
 R 1 + R 2  DD

VDS = VDD - ID(RD +RS) (4.16)

and

VG − VGS
ID = (4.17)
RS

Figure 4.10: An n-channel JFET voltage-divider bias circuit

Example 4. 3
Determine the dc Q-point of the amplifier shown in figure and draw its dc load
line. Given the IDSS and VGS(off) of JFET are 20mA and - 4.0V respectively.

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 4 Junction Field Effect Transistor Theory and Applications

Solution
Since RIN(gate) is extremely large, it does not cause any significant effect to gate
resistor RG.

Using equation (4.3)

 − 15
2
. V
I D = 20mA  1 −  = 7.8mA
 − 4V 

Voltage drop across drain-source

VDS = VDD - ID x 1kΩ = 20V - 1kΩ x 7.8mA

= 12.2V

Maximum ID = IDSS = 20mA and VDS at cutoff, VDS(cutoff) = 20V.

From the results above, the Q (quiescent)-point and dc load line are drawn
and shown in Fig. 4.11.

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4 Junction Field Effect Transistor Theory and Applications

Figure 4.11: The graph shows the dc load line and Q-point of the amplifier shown in Fig.
4.10

Example 4.4
Determine the approximate Q-point for the JFET biased with a voltage divider
circuit as shown in the figure, given that the particular device has transfer
characteristic curve as shown.

Solution
From equation (4.13), for drain current ID = 0A, the gate-to-source voltage VGS
is

 R2   2.2 MΩ 
VGS = VG =   VDD =   8V = 4.0V
 2.2 MΩ + 2.2 MΩ 
 R1 + R 2 

From Equation (4.15), for VGS = 0V, the drain current is

VG
ID = = 4V/3.3kΩ = 1.2mA
RS

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 4 Junction Field Effect Transistor Theory and Applications

From graphic plot, ID for Q-point is 1.8mA. Thus, from equation (4.14)

VDS = VDD - ID(RD +RS)

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4 Junction Field Effect Transistor Theory and Applications

= 8V - 1.8mA(680Ω + 3.3kΩ)
= 0.83V

4.4 Small Signal Amplifier

In this Section, the JFET is configured such that it works as a small-signal
amplifier. Various methods of biasing configuration such common-drain,
common-gate, and common-source configurations will be studied including its
merit and demerit points.

The amplification can be achieved from n-channel JFET transfer

characteristic and drain curves as they are shown in Fig. 4.12 and Fig. 4.13
respectively. Similarly, amplification can be achieved for p-channel JFET
device.

As shown in Fig. 4.12, a small change of gate-to-source voltage VGS can

result a large change of drain current ID.

Figure 4.12: Transfer characteristic curve of n-channel JFET showing signal amplification

Similarly, once can see that the above-mentioned change would also show in the
change of drain-to-source voltage VDS as shown in Fig. 4.13.
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 4 Junction Field Effect Transistor Theory and Applications

Like in the case of bipolar junction transistor, the Q-point of the amplifier
should be designed to set at the linear region of the transfer characteristic curve
to avoid non-linearity distortion.

Figure 4.13: Drain curve of n-channel JFET showing signal amplification

∆I D
Equation (4.4) defines dc transconductance as gm = . Thus, ac
∆VGS
Id
transconductance is defined as g m = . By rearranging the equation, ac drain
Vgs
current is Id = gmVgs.

4.4.1 Equivalent Circuits of FET

The hybrid π-model equivalent circuits of JFET are shown in Fig. 4.14. These
circuits are applicable for JFET and MOSFET. The drain current Id is equal to
gmVgs gate-source resistance rgs and output impedance = ro are introduced as
shown in Fig. 4.14(a). If gate-to-source resistance rgs is assumed to be infinitely
large and rO is large enough to be neglected, then the simplified equivalent
circuit shall be Fig. 4.14(b). Output impedance ro of the JFET can be determined

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4 Junction Field Effect Transistor Theory and Applications

from the Early voltage VM and drain current ID using equation

VM + VDS VM
r0 = ≅ .
ID ID

(a) (b)
Figure 4.14: π-model of JFET/MOSFET ac equivalent circuit

The T-model of the JFET device, which is also the model for the MOSFET
device, is shown in Fig. 4.15. The model is derived based on the fact the ac
source resistance Rin(source) of the JFET/MOSFET is equal to Rin(source)
Vgs Vgs 1
= = = .
IS g m Vgs gm

Figure 4.15: T-model of JFET/MOSFET ac equivalent circuit

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 4 Junction Field Effect Transistor Theory and Applications

4.4.2 Voltage Gain

The voltage gain AV of the JFET with an external ac source as input is defined
as AV = Vout/Vin. For a self bias JFET amplifier, its ac equivalent circuit is
shown in Fig. 4.16.

Figure 4.16: ac equivalent circuit

From the circuit, the output voltage Vout is Vout = -Vds = -IdRD and the input
voltage Vin is Vin = Vgs = Id/gm. Thus, the voltage gain is equal to AV = Vout/Vin
is

Id R D
AV = − = −g m R D (4.18)
Id / gm

4.4.3 Effect of ro and RS

If output impedance ro of JFET is taken into consideration, the voltage gain AV
will be reduced to

R D rO
A V = −g m (4.19)
R D + rO

If there is a source resistance RS, where the ac equivalent circuit is shown in

Fig. 4.17, voltage gain AV is reduced further because input voltage Vin is not just
equal to gate-to-source voltage Vgs. The input voltage Vin is Vin =Vgs + VgsgmRS
R D rO
= Vgs(1 + gmRS). Since output voltage Vout is Vout = -gmVgs . Therefore,
R D + rO
the ac voltage gain AV is
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4 Junction Field Effect Transistor Theory and Applications

gm  R D rO 
AV = -   (4.20)
(1 + g m R S )  R D + rO 

Figure 4.17: ac equivalent circuit with external source resistance Rs

4.4.4 Common-Source Amplifier

Figure 4.18 shows a common-source amplifier and its corresponding ac

equivalent circuit is shown in Fig. 4.19.

Figure 4.18: A common source JFET amplifier

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Figure 4.19: ac equivalent circuit of the common source JFET amplifier

If the dc circuit is biased at midpoint, then ID = IDSS/2. Otherwise, ID needs to be

known. Since it is self-bias then VGS = - IDRS. Substitute VGS into equation
2
 I R 
(4.3), it yields the drain current as I D = I DSS 1 + D S  . Expanding the square
 VGS( off ) 
 I R I2 R 2 
term of the equation, it yields drain current ID = IDSS 1 + 2 D S + D2 S  .
 VGS( off ) VGS( off ) 
Rearrange this quadratic equation in the forms of ax 2 + bx + c = 0 , it becomes
 2I DSS R S  I DSS R S2 2 I DSS R S2
I DSS +  
−1 ID + 2 I D = 0 , whereby the coefficients are a = 2 , b
 V  VGS( off ) VGS( Off )
 GS( off ) 
 2I R 
=  DSS S −1 , and c = IDSS respectively. Thus, drain-current ID is obtained from
 VGS( off ) 
− b ± b 2 − 4ac
ID = . It yields two values for drain current ID. One needs to
2a
consider the value of IDSS before the right value of ID to be chosen. The drain
current shall not be greater than IDSS current.

The drain-to-source voltage VDS is obtained from equation (4.21).

VDS = VDD - IDRD - IDRS (4.21)

The input impedance of the gate is extremely high so it can be neglected.

However, if IGSS and VGS are given then it can be calculated using equation
(4.9).

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4.4.5 Common-Drain Amplifier

Figure 4.20 shows a common-drain amplifier. It is also called source-follower.
Unlike the bipolar junction transistor common-collector amplifier, it is called
emitter-follower. The ac equivalent circuit of the amplifier is shown in Fig.
4.21.

Figure 4.20: A common-drain amplifier

Figure 4.21: The ac equivalent circuit of the common-drain amplifier

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 4 Junction Field Effect Transistor Theory and Applications

As usual voltage gain AV is Av = Vout/Vin. The input voltage Vin is Vin = Vgs +
IdRS. The output voltage Vout is Vout = IdRS. The voltage gain AV shall then be
equal to AV = IdRS/(Vgs + IdRS).

Recall that transconductance gm is gm = Id/Vgs. Substituting drain current Id

equals to Id = gmVgs, the voltage gain AV shall be

gmRS
AV = (4.22)
1+ gmRS

Thus, one can see that the gain is always less than one. If gmRs >> 1 then Av ≅ 1.

The input impedance of the gate RIN(gate) is very high and it can be
calculated from the gate reverse current IGSS value for a specified VGS value
from data sheet of the JFET using equation (4.9). If these data are given for a
specified JFET then the input impedance RIN for the amplifier shall be RIN(gate)
parallel with gate resistance RG.

4.4.6 Common-Gate Amplifier

The common-gate amplifier is shown in Fig. 4.22 and its corresponding ac
equivalent circuit is shown in Fig. 4.23.

Figure 4.22: A common-gate amplifier

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Figure 4.23: The equivalent circuit of the common-gate amplifier

The voltage gain AV is AV = -Vout/Vin and taking equation (4.4) for the drain
current Id, which is equal to gmVgs. The voltage gain shall be

Av = - Vout/Vgs = -IdRD/Vgs = gmVgsIdRD/Vgs

= - gmRd (4.23)

The input impedance Rin(source) = Vin/Iin. Since the input voltage Vin is Vin = Vgs
and Iin = Id = gmVgs. The ac source resistance Rin(source) shall be

Rin(source) = 1/gm (4.24)

From equation (4.24), it tells us that the input impedance Rin(source) is small,
which true because the source should have low impedance.

Example 4.5
From the circuit of common source JFET amplifier shown in the figure, its has
VGS(off) = -2.0V, IDSS = 1.4mA. If you need this amplifier to be biased with ID =
0.7mA, VDD = 20V, and voltage gain of 20dB, what is the value of RS, and RD?

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 4 Junction Field Effect Transistor Theory and Applications

Solution
Using equation (4.3), the drain current ID is
2
 VGS   VGS 
2

I D = I DSS 1 −  = 0.7mA = 1.4mA 1 −  . Solving this equation for gate-to-

 VGS( off )   2V 
source voltage VGS is yield equal to - 0.59V.

From equation (4.7), the transconductance at gate-to-source voltage equal

2I DSS 2 x1.4mA
to zero volt. i.e. VGS = 0 V is g m 0 = − =− = 1.4mA / V .
VGS( off ) − 2 .0 V

From equation (4.8), the transconductance gm for drain current ID = 0.7mA

is g m = g m 0 I D / I DSS = 1.4mA / V 0.7mA 1.4mA = 0.99mA / V .

From equation (4.12), the source resistance is RS = |VGS/ID| =

|0.59V/0.7mA| = 842.8Ω.

Voltage gain AV of 20dB corresponds to absolute voltage gain AV equal to

10.
From equation (4.13), voltage gain AV is AV = gmRD, then drain resistance
RD is RD = AV/gm=10/0.99mA/V = 10.1kΩ.

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4.5 Multistage Amplifier

The two-stage n-channel JFET amplifier is shown in Fig. 4.24. Recall the
multiple stage bipolar junction transistor amplifiers; the voltage gain of the first
stage is decreased by the load effect created by the input impedance of the
following stage.

However, the input impedance of each stage of multistage JFET amplifier

is very high that it has little effect on the preceding stage and it can be
neglected.

Figure 4.24: A two-stage JFET amplifier

The drain current is found to be 3.36mA. The transconductance shall then be

2.9mS. Thus, the overall gain of this two-stage amplifier is AV = AV1AV2 which
is equal to (2833µS)(1.5kΩ)(2833µS)(1.5kΩ) = 18.9.

In decibel it is AV (dB) = 20log(18.9) = 25.5dB.

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Tutorials
4.1. Describe and draw the diagrams to illustrate, how the n-channel and p-
channel JFET should be biased for normal operation.

4.2. The data sheet for certain type of JFET indicates that IDSS = 25mA,
VGS(off) = -10V, and gm0 = 5000µS.

Determine
(i) The type of JFET
(ii) Drain current ID at VGS = 0
(iii) Drain current ID and transconductance gm at VGS = - 4V.
2
 V  ∆I  V 
4.3. Given that I D = I DSS 1 − GS  , g m = D , and g m = g m 0 1 − GS  ,
 VGS( off )  ∆VGS  VGS( off ) 
2I
prove that g m 0 = − DSS and g m = g m 0 I D / I DSS .
VGS( off )

4.4. An n-channel JFET has a pinch-off voltage VP of – 4.5V and IDSS =

9.0mA. At what value of VGS in the pinch-off region will ID equal to
3.0mA and what is the value of VDS(P) when ID = 3.0mA?

4.5. From the circuit of common source JFET amplifier shown in figure, its
has VGS(off) = -2.0V, IDSS = 1.4mA. If you need this amplifier to be biased
with ID = 0.7mA, VDD = 20V, and voltage gain of 20dB, what is the
value of RS, and RD?

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4 Junction Field Effect Transistor Theory and Applications

4.6. Given a common drain JFET amplifier has VGS(off) = -8.0V, gm0 =
6000µS, R1 = R2 = 500kΩ, VDD = 20V, and C1 = C2 = 0.1µF.

(i) Calculate the values of output impedance and input impedance of the
amplifier when gate-to-source voltage VGS are -1.0V and -0.5V?
(ii) Calculate the drain-to-source current IDS when VGS is -1.5V?
(iii) What is the ac voltage gain AV of this amplifier when a load RL of
15.0kΩ is connected at VGS = -1.5V?

References
1. Thomas L. Floyd, "Electronic Devices", Prentice Hall International,
Inc.,1999.
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