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    EECS240 - Spring 2008 Comparator Gain-Bandwidth: Lecture 20: Comparators

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    nadeemjutt
    This document summarizes key aspects of comparators: 1. It provides an example comparator specification of a 4Gb/s link with a minimum detectable voltage difference of 1mV and a supply voltage of 1V, requiring the comparator to have a gain over 1000 in less than 250ps. 2. It discusses comparator performance metrics like clock rate, offset, resolution, hysteresis, and input capacitance. It also discusses comparator design challenges like power dissipation, common-mode rejection, kickback noise, and bandwidth. 3. It briefly describes common comparator circuit topologies like the flash converter, cascaded open-loop amplifiers, regenerative latch, current-mode latch, and techniques to address

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    EECS240 - Spring 2008 Comparator Gain-Bandwidth: Lecture 20: Comparators

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    This document summarizes key aspects of comparators: 1. It provides an example comparator specification of a 4Gb/s link with a minimum detectable voltage difference of 1mV and a supply voltage of 1V, requiring the comparator to have a gain over 1000 in less than 250ps. 2. It discusses comparator performance metrics like clock rate, offset, resolution, hysteresis, and input capacitance. It also discusses comparator design challenges like power dissipation, common-mode rejection, kickback noise, and bandwidth. 3. It briefly describes common comparator circuit topologies like the flash converter, cascaded open-loop amplifiers, regenerative latch, current-mode latch, and techniques to address

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    This document summarizes key aspects of comparators: 1. It provides an example comparator specification of a 4Gb/s link with a minimum detectable voltage difference of 1mV and a supply voltage of 1V, requiring the comparator to have a gain over 1000 in less than 250ps. 2. It discusses comparator performance metrics like clock rate, offset, resolution, hysteresis, and input capacitance. It also discusses comparator design challenges like power dissipation, common-mode rejection, kickback noise, and bandwidth. 3. It briefly describes common comparator circuit topologies like the flash converter, cascaded open-loop amplifiers, regenerative latch, current-mode latch, and techniques to address

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    7 views4 pages

    EECS240 - Spring 2008 Comparator Gain-Bandwidth: Lecture 20: Comparators

    Uploaded by

    nadeemjutt
    This document summarizes key aspects of comparators: 1. It provides an example comparator specification of a 4Gb/s link with a minimum detectable voltage difference of 1mV and a supply voltage of 1V, requiring the comparator to have a gain over 1000 in less than 250ps. 2. It discusses comparator performance metrics like clock rate, offset, resolution, hysteresis, and input capacitance. It also discusses comparator design challenges like power dissipation, common-mode rejection, kickback noise, and bandwidth. 3. It briefly describes common comparator circuit topologies like the flash converter, cascaded open-loop amplifiers, regenerative latch, current-mode latch, and techniques to address

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    Comparator Gain-Bandwidth

    EECS240 – Spring 2008 Example:

    • 4Gb/s link
    Lecture 20: Comparators • Minimum ∆V: 1mV
    • Vdd = 1V

    Æ Av > 1V / 1mV = 1000 in < 250ps!

    Elad Alon
    Dept. of EECS

    EECS240 Lecture 20 4

    Comparator Operational Amplifier?

    +
    - fu 2 1
    f −3dB = =
    clk Avo 3 Tbit

    • Specs and issues:


    2 Avo
    fu =
    • Clock rate fs • Power dissipation 3Tbit
    • Offset • CM rejection 1000
    = = 1.33THz
    • Resolution • Kickback noise 3 × 250ps
    • Hysteresis • …
    • Input cap

    EECS240 Lecture 20 2 EECS240 Lecture 20 5

    Flash Converter Open-Loop Amplifier Cascade


    VREF VIN

    • Fast: one clock cycle R/2

    per conversion R

    • High complexity:
    R

    Digital
    2B-1 comparators Encoder
    Output

    • High input R
    capacitance
    R/2

    EECS240 Lecture 20 3 EECS240 Lecture 20 6


    Cascaded Amplifier Power Consumption
    • Simplified bandwidth analysis:
    • Open-circuit time constants
    • (Not most accurate, but leads to nearly the right
    answer for design optimization)

    EECS240 Lecture 20 7 EECS240 Lecture 20 10

    Bandwidth/Gain Optimization Regenerative Latch

    EECS240 Lecture 20 8 EECS240 Lecture 20 11

    Bandwidth/Gain Optimization CML Comparator (Latch)

    EECS240 Lecture 20 9 EECS240 Lecture 20 12


    StrongArm Latch Overdrive Recovery

    EECS240 Lecture 20 13 EECS240 Lecture 20 16

    Another CMOS Comparator Kickback

    EECS240 Lecture 20 14 EECS240 Lecture 20 17

    Hysteresis Kickback cont’d

    EECS240 Lecture 20 15 EECS240 Lecture 20 18


    Kickback cont’d

    EECS240 Lecture 20 19

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