750 MHz to 1150 MHz Quadrature

Demodulator with Fractional-N PLL and VCO

Data Sheet ADRF6801
FEATURES GENERAL DESCRIPTION
IQ demodulator with integrated fractional-N PLL The ADRF6801 is a high dynamic range IQ demodulator with
LO frequency range: 750 MHz to 1150 MHz integrated PLL and VCO. The fractional-N PLL/synthesizer
Input P1dB: 12.5 dBm generates a frequency in the range of 3.0 GHz to 4.6 GHz. A
Input IP3: 25 dBm divide-by-4 quadrature divider divides the output frequency of
Noise figure (DSB): 14.3 dB the VCO down to the required local oscillator (LO) frequency
Voltage conversion gain: 5.1 dB to drive the mixers in quadrature. Additionally, an output buffer
Quadrature demodulation accuracy can be enabled that generates an fVCO/2 signal for external use.
Phase accuracy: 0.3°
The PLL reference input is supported from 10 MHz to 160 MHz.
Amplitude accuracy: 0.05 dB
The phase detector output controls a charge pump whose output
Baseband demodulation: 275 MHz, 3 dB bandwidth
is integrated in an off-chip loop filter. The loop filter output is
SPI serial interface for PLL programming
then applied to an integrated VCO.
40-lead, 6 mm × 6 mm LFCSP
The IQ demodulator mixes the differential RF input with the
complex LO derived from the quadrature divider. The differential
APPLICATIONS I and Q output paths have excellent quadrature accuracy and
QAM/QPSK RF/IF demodulators can handle baseband signaling or complex IF up to 120 MHz.
Cellular W-CDMA/CDMA/CDMA2000 The ADRF6801 is fabricated using an advanced silicon-germanium
Microwave point-to-(multi)point radios
BiCMOS process. It is available in a 40-lead, exposed-paddle,
Broadband wireless and WiMAX
RoHS-compliant, 6 mm × 6 mm LFCSP package. Performance is
specified over the −40°C to +85°C temperature range.

FUNCTIONAL BLOCK DIAGRAM

GND VCCLO VCCLO LOSEL IBBP IBBN GND
35 34 17 36 33 32 31
BUFFER
CTRL ADRF6801 30 GND
LON 37 29 VCCBB
BUFFER
28 GND
LOP 38
27 VCCRF

BUFFER DIVIDER
FRACTION MODULUS INTEGER ÷1
GND 11 REG REG MUX
OR
DATA 12 ÷2
SPI THIRD-ORDER QUAD
CLK 13 INTERFACE 26 RFIN
FRACTIONAL ÷2
LE 14 INTERPOLATOR
GND 15 PRESCALER VCO
N COUNTER ÷2 CORE 25 GNDRF
×2
24 GND
REFIN 6 – PHASE
MUX TEMP + FREQUENCY CHARGE PUMP 23 GND
÷2
GND 7 SENSOR DETECTOR 250µA,
500µA (DEFAULT), 22 VCCBB
÷4
3.3V LDO 750µA, 2.5V LDO VCO LDO
MUXOUT 8 1000µA 21 GND
09576-001

1 2 10 16 3 4 5 9 39 40 18 19 20
VCC1 DECL3 VCC2 GND CPOUT GND RSET DECL2 VTUNE DECL1 QBBP QBBN GND

Figure 1.

Rev. A Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2011–2018 Analog Devices, Inc. All rights reserved.
Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
ADRF6801
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings ............................................................ 6
Pin Configuration and Function Descriptions ............................. 7
Typical Performance Characteristics ............................................. 9
Synthesizer/PLL .......................................................................... 12
Complementary Cumulative Distribution Functions (CCDF)
....................................................................................................... 13
Circuit Description ......................................................................... 14
LO Quadrature Drive ................................................................. 14
V-to-I Converter ......................................................................... 14
Mixers........................................................................................... 14
Emitter Follower Buffers ........................................................... 14
Bias Circuitry .............................................................................. 14
REVISION HISTORY
6/2018—Rev. 0 to Rev. A
Change to Register Structure Section .......................................... 14
Changes to Register Programming Section ................................ 22
1/2011—Revision 0: Initial Version
Rev. A | Page 2 of 34
Data Sheet
Register Structure ....................................................................... 14
Applications Information .............................................................. 21
Basic Connections ...................................................................... 21
Supply Connections ................................................................... 21
Synthesizer Connections ........................................................... 21
I/Q Output Connections ........................................................... 22
RF Input Connections ............................................................... 22
Charge Pump/VTUNE Connections ...................................... 22
LO Select Interface ..................................................................... 22
External LO Interface ................................................................ 22
Setting the Frequency of the PLL ............................................. 22
Register Programming ............................................................... 22
EVM Measurements .................................................................. 23
Evaluation Board Layout and Thermal Grounding ................... 24
ADRF6801 Software .................................................................. 28
Characterization Setups ................................................................. 30
Outline Dimensions ....................................................................... 34
Ordering Guide .......................................................................... 34
Data Sheet ADRF6801

SPECIFICATIONS
VS = 5 V; ambient temperature (TA) = 25°C; fREF = 26 MHz, fLO = 900 MHz, fBB = 4.5 MHz, RLOAD = 450 Ω differential, all register and PLL
settings use the recommended values shown in the Register Structure section, unless otherwise noted.

Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
RF INPUT AT 900 MHz RFIN pins
Internal LO Frequency Range With VCO amplitude = 63 (R6 [DB15 to DB10]) 750 1125 MHz
With VCO amplitude = 24 (R6 [DB15 to DB10]) 750 1150 MHz
Input Return Loss Measured at 900 MHz <−20 dB
Input P1dB 12.5 dBm
Second-Order Input Intercept (IIP2) −5 dBm each tone >65 dBm
Third-Order Input Intercept (IIP3) −5 dBm each tone 25 dBm
Noise Figure Double sideband from RF to either I or Q output 14.3 dB
With a −10 dBm interferer 5 MHz away 18.9 dB
LO-to-RF Leakage At 1×LO frequency, 50 Ω termination at the RF port −75 dBm
I/Q BASEBAND OUTPUTS IBBP, IBBN, QBBP, QBBN pins
Voltage Conversion Gain 450 Ω differential load across IBBP, IBBN (or QBBP, QBBN) 5.1 dB
Demodulation Bandwidth 1 V p-p signal 3 dB bandwidth 275 MHz
Quadrature Phase Error 0.3 Degrees
I/Q Amplitude Imbalance 0.05 dB
Output DC Offset (Differential) ±5 mV
Output Common-Mode Voltage VPOS − 2.4 V
Gain Flatness Any 5 MHz (<100 MHz) 0.2 dB p-p
Maximum Output Swing Differential 450 Ω load 4 V p-p
Differential 200 Ω load 2.4 V p-p
Maximum Output Current Each pin 12 mA p-p
LO INPUT/OUTPUT LOP, LON
Output Level Into a differential 50 Ω load, LO buffer enabled (LO −2.5 dBm
frequency = 900 MHz, output frequency = 1800 MHz)
Input Level Externally applied 2×LO, PLL disabled 0 dBm
Input Impedance Externally applied 2×LO, PLL disabled 50 Ω
VCO Operating Frequency With VCO amplitude = 63 (R6 [DB15 to DB10]) 3000 4500 MHz
With VCO amplitude = 24 (R6 [DB15 to DB10]) 3000 4600 MHz
SYNTHESIZER SPECIFICATIONS All synthesizer specifications measured with
recommended settings provided in Figure 33 through
Figure 39
Channel Spacing fPFD = 26 MHz; modulus = 2047 25 kHz
PLL Bandwidth Can be adjusted with off-chip loop filter component 130 kHz
values and RSET
SPURS fLO = 900 MHz, fREF = 26 MHz, fPFD = 26 MHz, measured
at BB outputs with fBB = 50 MHz
Reference Spurs fREF = 26 MHz, fPFD = 26 MHz −91.6 dBc
fPFD/2 −107.8 dBc
fPFD × 2 −89.1 dBc
fPFD × 3 −94.2 dBc

Rev. A | Page 3 of 34
ADRF6801 Data Sheet
Parameter Test Conditions/Comments Min Typ Max Unit
PHASE NOISE (USING 130 kHz LOOP FILTER) fLO = 900 MHz, fREF = 26 MHz, fPFD = 26 MHz, measured
at BB outputs with fBB = 50 MHz
1 kHz offset −99.5 dBc/Hz
10 kHz offset −107.8 dBc/Hz
100 kHz offset −106.6 dBc/Hz
500 kHz offset −126.7 dBc/Hz
1 MHz offset −131.7 dBc/Hz
5 MHz offset −143.5 dBc/Hz
10 MHz offset −150.5 dBc/Hz
Integrated Phase Noise 1 kHz to 10 MHz integration bandwidth 0.16 °rms
PHASE NOISE (USING 2.5 kHz LOOP FILTER) fLO = 900 MHz, fREF = 26 MHz, fPFD = 26 MHz, measured
at BB outputs with fBB = 50 MHz
1 kHz offset −71.3 dBc/Hz
10 kHz offset −88.3 dBc/Hz
100 kHz offset −114.1 dBc/Hz
500 kHz offset −129.5 dBc/Hz
1 MHz offset −138.6 dBc/Hz
5 MHz offset −150.2 dBc/Hz
10 MHz offset −150.3 dBc/Hz
PLL FIGURE OF MERIT (FOM) Measured with fREF = 26 MHz, fPFD = 26 MHz −215.4 dBc/Hz/Hz
Measured with fREF = 104 MHz, fPFD = 26 MHz −220.9 dBc/Hz/Hz
Phase Detector Frequency 20 26 40 MHz
REFERENCE CHARACTERISTICS REFIN, MUXOUT pins
REFIN Input Frequency Usable range 10 160 MHz
REFIN Input Capacitance 4 pF
MUXOUT Output Level VOL (lock detect output selected) 0.25 V
VOH (lock detect output selected) 2.7 V
REFOUT Duty Cycle 50 %
CHARGE PUMP
Pump Current 500 µA
Output Compliance Range 1 2.8 V
LOGIC INPUTS CLK, DATA, LE pins
Input High Voltage, VINH 1.4 3.3 V
Input Low Voltage, VINL 0 0.7 V
Input Current, IINH/IINL 0.1 µA
Input Capacitance, CIN 5 pF
POWER SUPPLIES VCC1, VCC2, VCCLO, VCCBB, VCCRF pins
Voltage Range (5 V) 4.75 5 5.25 V
Supply Current (5 V) Normal Rx mode, internal LO 262 mA
Rx mode, internal LO with LO buffer enabled 288 mA
Rx mode, using external LO input (internal VCO, PLL shut 157 mA
down)
Supply Current (5 V) Power-down mode 20 mA

Rev. A | Page 4 of 34
Data Sheet ADRF6801
TIMING CHARACTERISTICS
VS = 5 V, unless otherwise noted.

Table 2.
Parameter Limit at TMIN to TMAX (B Version) Unit Test Conditions/Comments
t1 20 ns min LE setup time
t2 10 ns min DATA to CLK setup time
t3 10 ns min DATA to CLK hold time
t4 25 ns min CLK high duration
t5 25 ns min CLK low duration
t6 10 ns min CLK to LE setup time
t7 20 ns min LE pulse width

Timing Diagram
t4 t5

CLOCK

t2 t3

DB1 DB0 (LSB)

DATA DB23 (MSB) DB22 DB2 (CONTROL BIT C2) (CONTROL BIT C1)

t7

LE

t1 t6

09576-002
LE

Figure 2. Timing Diagram

Rev. A | Page 5 of 34
ADRF6801 Data Sheet

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION
Table 3.
Parameter Rating
Supply Voltage, VCC1, VCC2, VCCLO, −0.5 V to +5.5 V
VCCBB, and VCCRF (VS1)
Digital I/O, CLK, DATA, and LE −0.3 V to +3.6 V
RFIN 16 dBm
θJA (Exposed Paddle Soldered Down) 30°C/W
Maximum Junction Temperature 150°C
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.

Rev. A | Page 6 of 34
Data Sheet ADRF6801

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

34 VCCLO
39 VTUNE

36 LOSEL
40 DECL1

32 IBBN
33 IBBP
35 GND

31 GND
37 LON
38 LOP
VCO BUFFER
LDO CTRL

VCC1 1 30 GND

DECL3 2 29 VCCBB
SCALE
PHASE DETECTOR
CPOUT 3 AND 28 GND
CHARGE PUMP
BLEED

GND 4 DIV 27 VCCRF

CTRL

RSET 5 26 RFIN
VCO VCO DIV
×2 BAND 6 3000MHz MUX ÷1 QUADRATURE
TO OR ÷2
REFIN 6 CURRENT ÷2 25 GNDRF
CAL/SET 6 4600MHz
MUX
÷2

GND 7 24 GND
PROGRAMABLE PRESCALER
÷4 DIVIDER ÷2
ENABLE

MUXOUT 8 23 GND

DECL2 9 22 VCCBB
2.5V THIRD-ORDER
LDO SDM
VCC2 10 21 GND

FRACTION MODULUS INTEGER

SERIAL PORT
LE 14
DATA 12

CLK 13

VCCLO 17
GND 11

GND 15

GND 16

QBBP 18

GND 20
QBBN 19

08817-003

Figure 3. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description
1 VCC1 The 5 V Power Supply Pin for VCO and PLL (VCC1).
2 DECL3 Decoupling Node for the 3.3 V LDO. Connect a 0.1 µF capacitor between this pin and ground.
3 CPOUT Charge Pump Output Pin. Connect this pin to VTUNE through the loop filter.
4, 7, 11, 15, 16, 20, 21, GND Connect these pins to a low impedance ground plane.
23, 24, 28, 30, 31, 35

Rev. A | Page 7 of 34
ADRF6801 Data Sheet
Pin No. Mnemonic Description
5 RSET Charge Pump Current. The nominal charge pump current can be set to 250 µA, 500 µA, 750 µA, or 1
mA using DB10 and DB11 of Register 4 and by setting DB18 to 0 (internal reference current). In this
mode, no external RSET is required. If DB18 is set to 1, the four nominal charge pump currents
(INOMINAL) can be externally tweaked according to the following equation where the resulting value is in
units of ohms.
 217.4 × ICP 
RSET =   − 37.8
 I NOMINAL 
6 REFIN Reference Input. Nominal input level is 1 V p-p. Input range is 10 MHz to 160 MHz.
8 MUXOUT Multiplexer Output. This output can be programmed to provide the reference output signal or
the lock detect signal. The output is selected by programming the appropriate register.
9 DECL2 Decoupling Node for 2.5 V LDO. Connect a 0.1 µF capacitor between this pin and ground.
10 VCC2 The 5 V power supply pin for the 2.5 V LDO.
12 DATA Serial Data Input. The serial data is loaded MSB first with the three LSBs being the control bits.
13 CLK Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is
latched into the 24-bit shift register on the CLK rising edge. Maximum clock frequency is 20 MHz.
14 LE Load Enable. When the LE input pin goes high, the data stored in the shift registers is loaded into
one of the six registers, the relevant latch being selected by the first three control bits of the 24-bit
word.
17, 34 VCCLO The 5 V Power Supply for the LO Path Blocks.
18, 19 QBBP, QBBN Demodulator Q-Channel Differential Baseband Outputs; Differential Output Impedance of 24 Ω.
22, 29 VCCBB The 5 V Power Supply for the Baseband Output Section of the Demodulator Blocks.
25 GNDRF Ground Return for RF Input Balun.
26 RFIN Single-Ended, Ground Referenced 50 Ω, RF Input.
27 VCCRF The 5 V Power Supply for the RF Input Section of the Demodulator Blocks.
32, 33 IBBN, IBBP Demodulator I-Channel Differential Baseband Outputs; Differential Output Impedance of 24 Ω.
36 LOSEL LO Select. Connect this pin to ground for the simplest operation and to completely control the LO
path and input/output direction from the register SPI programming.
For additional control without register reprogramming, this input pin can determine whether the
LOP and LON pins operate as inputs or outputs. LOP and LON become inputs if the LOSEL pin is
set low, the LDRV bit of Register 5 is set low, and the LXL bit of Register 5 is set high. The
externally applied LO drive must be at 2×LO frequency (and the LDIV bit of Register 5 (DB5) set
low). LON and LOP become outputs when LOSEL is high or if the LDRV bit of Register 5 (DB3) is set
high and the LXL bit of Register 5 (DB4) is set low. The output frequency is 2×LO frequency (and
the LDIV bit of Register 5 (DB5) must be set high). This pin should not be left floating.
37, 38 LON, LOP Local Oscillator Input/Output. When these pins are used as output pins, a differential frequency
divided version of the internal VCO is available on these pins. When the internal LO generation is
disabled, an external M×LO frequency signal can be applied to these pins (where M corresponds
to the LO path divider setting). (Differential Input/Output Impedance of 50 Ω)
39 VTUNE VCO Control Voltage Input. This pin is driven by the output of the loop filter. The nominal input
voltage range on this pin is 1.0 V to 2.8 V.
40 DECL1 Connect a 10 µF capacitor between this pin and ground as close to the device as possible
because this pin serves as the VCO supply and loop filter reference.
EP Exposed Paddle. The exposed paddle should be soldered to a low impedance ground plane.

Rev. A | Page 8 of 34
Data Sheet ADRF6801

TYPICAL PERFORMANCE CHARACTERISTICS

VS = 5 V, TA = 25°C, unless otherwise noted. LO = 750 MHz to 1150 MHz.
16 80
CONVERSION GAIN (dB) AND INPUT P1dB (dBm)

14 IP1dB 75

12

TA = +85°C 70

INPUT IP2 (dBm)

10 TA = +25°C
TA = –40°C
TA = +85°C
8 65 TA = +25°C
TA = –40°C
6 GAIN
60 I CHANNEL
Q CHANNEL
4
55
2

0 50

09576-007
09576-004
750 800 850 900 950 1000 1050 1100 1150 750 800 850 900 950 1000 1050 1100 1150
LO FREQUENCY (MHz) LO FREQUENCY (MHz)

Figure 4. Conversion Gain and Input P1dB vs. LO Frequency Figure 7. Input IP2 vs. LO Frequency

35 20

33 19
TA = +85°C
31 TA = +25°C 18
TA = –40°C TA = +85°C
29 17 TA = +25°C
NOISE FIGURE (dB)

TA = –40°C
INPUT IP3 (dBm)

27 16

25 15

23 14

21 13

19 12

17 11

15 10
09576-005

09576-008
750 800 850 900 950 1000 1050 1100 1150 750 800 850 900 950 1000 1050 1100 1150
LO FREQUENCY (MHz) LO FREQUENCY (MHz)

Figure 5. Input IP3 vs. LO Frequency Figure 8. Noise Figure vs. LO Frequency

1.0 5
IQ QUADRATURE PHASE ERROR (Degrees)

0.8 4
TA = +85°C
0.6 TA = +85°C 3 TA = +25°C
TA = +25°C TA = –40°C
IQ GAIN MISMATCH (dB)

0.4 TA = –40°C 2

0.2 1

0 0

–0.2 –1

–0.4 –2

–0.6 –3

–0.8 –4

–1.0 –5
09576-006

09576-009

750 800 850 900 950 1000 1050 1100 1150 750 800 850 900 950 1000 1050 1100 1150
LO FREQUENCY (MHz) LO FREQUENCY (MHz)

Figure 6. IQ Gain Mismatch vs. LO Frequency Figure 9. IQ Quadrature Phase Error vs. LO Frequency

Rev. A | Page 9 of 34
ADRF6801 Data Sheet
–50 1

–55 0
LO-TO-RF FEEDTHROUGH (dBm)

FREQUENCY RESPONSE (dB)

–60 –1

NORMALIZED BASEBAND
–65 –2

–70 –3

–75 –4

–80 –5

–85 –6

–90 –7

09576-013
09576-010
750 800 850 900 950 1000 1050 1100 1150 1 10 100
LO FREQUENCY (MHz) BASEBAND FREQUENCY (MHz)

Figure 10. LO-to-RF Feedthrough vs. LO Frequency, LO Output Turned Off Figure 13. Normalized Baseband Frequency Response vs. Baseband
Frequency
–35 80
IIP2
–40 70
LO-TO-BB FEEDTHROUGH (dBV rms)

INPUT P1dB (dBm), INPUT IP2 (dBm),

–45 60

AND INPUT IP3 (dBm)

TA = +85°C
–50 50 TA = +25°C
TA = –40°C

–55 40 I CHANNEL
Q CHANNEL
–60 30 IIP3

–65 20
IP1dB

–70 10

–75 0
09576-011

09576-014
750 800 850 900 950 1000 1050 1100 1150 5 10 15 20 25 30 35 40 45 50
LO FREQUENCY (MHz) BASEBAND FREQUENCY (MHz)

Figure 11. LO-to-BB Feedthrough vs. LO Frequency, LO Output Turned Off Figure 14. Input P1dB, Input IP2, and Input IP3 vs. Baseband Frequency

–30 34
32
–35
30
RF-TO-BB FEEDTHROUGH (dBc)

–40 28
NOISE FIGURE (dB)

26
–45
24
–50 22
20
–55
18
–60
16

–65 14
12
–70
10
09576-012

09576-015

750 800 850 900 950 1000 1050 1100 1150 –35 –30 –25 –20 –15 –10 –5 0 5
RF FREQUENCY (MHz) INPUT BLOCKER POWER (dBm)

Figure 12. RF-to-BB Feedthrough vs. RF Frequency Figure 15. Noise Figure vs. Input Blocker Level,
fLO = 900 MHz (RF Blocker 5 MHz Offset)

Rev. A | Page 10 of 34
Data Sheet ADRF6801
0 2.0

–5 1.9
RF INPUT RETURN LOSS (dB)

–10 1.8

VPTAT VOLTAGE (V)

–15 1.7

–20 1.6

–25 1.5

–30 1.4

–35 1.3

–40 1.2

09576-016

09576-019
750 800 850 900 950 1000 1050 1100 1150 –40 –15 10 35 60 85
RF FREQUENCY (MHz) TEMPERATURE (°C)

Figure 16. RF Input Return Loss vs. RF Frequency Figure 19. VPTAT vs. Temperature

0 3.5

–2 TA = +85°C
3.0 TA = +25°C
OUTPUT RETURN LOSS (dB)

TA = –40°C
–4
LOP, LON DIFFERENTIAL

VTUNE VOLTAGE (V)

2.5
–6

–8 2.0

–10
1.5
12

1.0
–14

–16 0.5
09576-017

09576-020
1500 1600 1700 1800 1900 2000 2100 2200 2300 750 800 850 900 950 1000 1050 1100 1150
LOP, LON OUTPUT FREQUENCY (MHz) LO FREQUENCY (MHz)

Figure 17. LO Output Return Loss vs. LO Output Frequency, LO Output Figure 20. VTUNE vs. LO Frequency
Enabled (1500 MHz to 2300 MHz), Measured through TC1-1-13 Balun
400

380

360
TA = +85°C
340 TA = +25°C
TA = –40°C
CURRENT (mA)

320

300

280

260

240

220

200
09576-018

750 800 850 900 950 1000 1050 1100 1150

LO FREQUENCY (MHz)

Figure 18. 5 V Supply Currents vs. LO Frequency,

LO Output Enabled

Rev. A | Page 11 of 34
ADRF6801 Data Sheet
SYNTHESIZER/PLL
VS = 5 V. See the Register Structure section for recommended settings used. External loop filter bandwidths of ~130 kHz and 2.5 kHz
used (see plots within this section for annotations), fREF = fPFD = 26 MHz, measured at BB output, fBB = 50 MHz, unless otherwise noted.
–40 1.0

TA = +85°C 0.9 TA = +85°C

–60 TA = +25°C TA = +25°C

INTEGRATED PHASE NOISE (°rms)

TA = –40°C 0.8 TA = –40°C
PHASE NOISE (dBc/Hz)

0.7
–80
0.6
130kHz LOOP FILTER
BANDWIDTH
–100 0.5

0.4
–120
0.3
2.5kHz LOOP FILTER
BANDWIDTH 0.2
–140
0.1

–160 0
09576-021

09576-024
1k 10k 100k 1M 10M 750 800 850 900 950 1000 1050 1100 1150
OFFSET FREQUENCY (Hz) LO FREQUENCY (MHz)
Figure 21. Phase Noise vs. Offset Frequency, fLO = 900 MHz, Shown for Loop Figure 24. Integrated Phase Noise vs. LO Frequency (Spurs Omitted), Using
Filter Bandwidths of 2.5 kHz and 130 kHz Loop Filter Bandwidth of 130 kHz
–70 –50
TA = +85°C 1 × PFD FREQUENCY 1kHz
TA = +25°C 3 × PFD FREQUENCY OFFSET
–75
TA = –40°C 0.5 × PFD FREQUENCY –70
PLL REFERENCE SPURS (dBc)

10kHz
–80 OFFSET
PHASE NOISE (dBc/Hz)

–90 1kHz OFFSET

–85

–90 –110
130kHz LOOP FILTER BANDWIDTH
10kHz 2.5kHz LOOP FILTER BANDWIDTH
–95 OFFSET TA = +85°C
–130 TA = +25°C
5MHz
OFFSET TA = –40°C
–100

–150
–105
5MHz
OFFSET
–110 –170

09576-025
09576-022

750 800 850 900 950 1000 1050 1100 1150 750 800 850 900 950 1000 1050 1100 1150
LO FREQUENCY (MHz) LO FREQUENCY (MHz)

Figure 22. PLL Reference Spurs vs. LO Frequency, Using Loop Filter Figure 25. Phase Noise vs. LO Frequency (1 kHz, 10 kHz, and 5 MHz Offsets),
Bandwidth of 130 kHz Shown for Loop Filter Bandwidths of 2.5 kHz and 130 kHz
–70 –90
TA = +85°C 2 × PFD FREQUENCY
–75 TA = +25°C 4 × PFD FREQUENCY –100 100kHz OFFSET
TA = –40°C
PLL REFERENCE SPURS (dBc)

–80
PHASE NOISE (dBc/Hz)

–110

–85
–120 100kHz OFFSET
–90 1MHz OFFSET

–130
–95

–140
–100
1MHz OFFSET TA = +85°C
–150 TA = +25°C
–105
130kHz LOOP FILTER BANDWIDTH TA = –40°C
2.5kHz LOOP FILTER BANDWIDTH
–110 –160
09576-026
09576-023

750 800 850 900 950 1000 1050 1100 1150 750 800 850 900 950 1000 1050 1100 1150
LO FREQUENCY (MHz) LO FREQUENCY (MHz)

Figure 23. PLL Reference Spurs vs. LO Frequency, Using Loop Filter Figure 26. Phase Noise vs. LO Frequency (100 kHz and 1 MHz Offsets), Shown
Bandwidth of 130 kHz for Loop Filter Bandwidths of 2.5 kHz and 130 kHz

Rev. A | Page 12 of 34
Data Sheet ADRF6801
COMPLEMENTARY CUMULATIVE DISTRIBUTION FUNCTIONS (CCDF)
VS = 5 V, fLO = 900 MHz, fBB = 4.5 MHz.
100 100
CUMULATIVE DISTRIBUTION PERCENTAGE (%)

CUMULATIVE DISTRIBUTION PERCENTAGE (%)

90 90

80 GAIN 80 TA = +85°C
TA = +85°C TA = +25°C
70 TA = +25°C 70 TA = –40°C
TA = –40°C
60 I CHANNEL
60
Q CHANNEL
50 IP1dB 50

40 40

30 30

20 20

10 10

0 0

09576-027

09576-030
0 2 4 6 8 10 12 14 16 18 60 62 64 66 68 70 72 74 76 78 80
GAIN (dB) AND INPUT P1dB (dBm) INPUT IP2 (dBm)

Figure 27. Gain and Input P1dB Figure 30. Input IP2

100 100
CUMULATIVE DISTRIBUTION PERCENTAGE (%)

CUMULATIVE DISTRIBUTION PERCENTAGE (%)

90 90

80 TA = +85°C
80
TA = +25°C
TA = –40°C
70 70
I CHANNEL
60 60 TA = +85°C
Q CHANNEL
TA = +25°C
50 50 TA = –40°C

40 40

30 30

20 20

10 10

0 0
09576-028

09576-131
15 17 19 21 23 25 27 29 31 33 35 4 6 8 10 12 14 16 18 20 22 24
INPUT IP3 (dBm) NOISE FIGURE (dB)

Figure 28. Input IP3 Figure 31. Noise Figure

100 100
CUMULATIVE DISTRIBUTION PERCENTAGE (%)

CUMULATIVE DISTRIBUTION PERCENTAGE (%)

90 90

80 TA = +85°C
80
TA = +25°C
TA = –40°C
70 70

60 60

50 50 TA = +85°C
TA = +25°C
40 40 TA = –40°C

30 30

20 20

10 10

0 0
09576-029

09576-132

–0.5 –0.4 –0.3 –0.2 –0.1 0 0.1 0.2 0.3 0.4 0.5 –5 –4 –3 –2 –1 0 1 2 3 4 5
IQ GAIN MISMATCH (dB) IQ QUADRATURE PHASE ERROR (Degrees)

Figure 29. IQ Gain Mismatch Figure 32. IQ Quadrature Phase Error

Rev. A | Page 13 of 34
ADRF6801
CIRCUIT DESCRIPTION
The ADRF6801 integrates a high performance IQ demodulator
with a state-of-the-art fractional-N PLL. The PLL also integrates
a low noise VCO. The SPI port allows the user to control the
fractional-N PLL functions, the demodulator LO divider functions,
and optimization functions, as well as allowing for an externally
applied LO.
The ADRF6801 uses a high performance mixer core that results
in an exceptional input IP3 and input P1dB, with a very low output
noise floor for excellent dynamic range.
LO QUADRATURE DRIVE
A signal at 2× the desired mixer LO frequency is delivered to
a divide-by-2 quadrature phase splitter followed by limiting
amplifiers which then drive the I and Q mixers, respectively.
V-TO-I CONVERTER
The RF input signal is applied to an on-chip balun which then
provides both a ground referenced, 50 Ω single-ended input
impedance and a differential voltage output to a V-to-I converter
that converts the differential voltages to differential output currents.
These currents are then applied to the emitters of the Gilbert
cell mixers.
MIXERS
The ADRF6801 has two double-balanced mixers: one for the
in-phase channel (I channel) and one for the quadrature channel
(Q channel). These mixers are based on the Gilbert cell design
of four cross-connected transistors. The output currents from
the two mixers are summed together in the resistive loads that
then feed into the subsequent emitter follower buffers.
EMITTER FOLLOWER BUFFERS
The output emitter followers drive the differential I and Q signals
off chip. The output impedance is set by on-chip 12 Ω series
resistors that yield a 24 Ω differential output impedance for each
baseband port. The fixed output impedance forms a voltage divider
with the load impedance that reduces the effective gain. For example,
a 500 Ω differential load has ~0.5 dB lower effective gain than
with a high (10 kΩ) differential load impedance.
The common-mode dc output levels of the emitter followers are set
from VCCBB via the voltage drop across the mixer load resistors,
the VBE of the output emitter follower, and the voltage drop
across the 12 Ω series resistor.
Rev. A | Page 14 of 34
Data Sheet
BIAS CIRCUITRY
There are several band gap reference circuits and three low
dropout regulators (LDOs) in the ADRF6801 that generate the
reference currents and voltages used by different sections. The
first of the LDOs is the 2.5 V LDO, which is always active and
provides the 2.5 V supply rail used by the internal digital logic
blocks. The 2.5 V LDO output is connected to DECL2 (Pin 9)
for the user to provide external decoupling.
The second LDO is the VCO LDO, which acts as the positive
supply rail for the internal VCO. The VCO LDO output is
connected to DECL2 (Pin 40) for the user to provide external
decoupling. The VCO LDO can be powered down by setting
Register 6, DB18 = 0, which allows the user to save power when
not using the VCO.
The third LDO is the 3.3 V LDO, which acts as the 3.3 V
positive supply rail for the reference input, phase frequency
detector, and charge pump circuitry. The 3.3 V LDO output is
connected to DECL3 (Pin 2) for the user to provide external
decoupling. The 3.3 V LDO can be powered down by setting
Register 6, DB19 = 0, which allows the user to save power when
not using the VCO. The demodulator also has a bias circuit that
supplies bias current for the mixer V-to-I stage, which then sets
the bias for the mixer core. The demodulator bias cell can also
be shut down by setting Register 5, DB7 = 0.
REGISTER STRUCTURE
The ADRF6801 provides access to its many programmable
features through a 3-wire SPI control interface that is used to
program the seven internal registers. The minimum delay and
hold times are shown in the timing diagram (see Figure 2). The
SPI provides digital control of the internal PLL/VCO as well as
several other features related to the demodulator core, on-chip
referencing, and available system monitoring functions. The
MUXOUT pin provides a convenient, single-pin monitor output
signal that can be used to deliver a PLL lock-detect signal or an
internal voltage proportional to the local junction temperature.
Note that internal calibration for the PLL must run when the
ADRF6801 is initialized at a given frequency. This calibration is run
automatically whenever Register 0, Register 1, or Register 2 is
programmed. Because the other registers affect PLL performance,
Register 0, Register 1, and Register 2 must always be programmed
last. For ease of use, starting the initial programming with
Register 6 and then programming the registers in descending
order, ending with Register 0, is recommended. Once the PLL
and other settings are programmed, the user can change the
PLL frequency simply by programming Register 0, Register 1,
or Register 2 as necessary.
Data Sheet ADRF6801
DIVIDE
MODE INTEGER DIVIDE RATIO CONTROL BITS

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 0 0 0 0 0 0 0 0 DM ID6 ID5 ID4 ID3 ID2 ID1 ID0 C3(0) C2(0) C1(0)

DM DIVIDE MODE
0 FRACTIONAL (DEFAULT)
1 INTEGER

ID6 ID5 ID4 ID3 ID2 ID1 ID0 DIVIDE RATIO

0 0 1 0 1 0 1 21 (INTEGER MODE ONLY)

0 0 1 0 1 1 0 22 (INTEGER MODE ONLY)
0 0 1 0 1 1 1 23 (INTEGER MODE ONLY)
0 0 1 1 0 0 0 24
... ... ... ... ... ... ... ...
... ... ... ... ... ... ... ...
0 1 1 1 0 0 0 56 (DEFAULT)
... ... ... ... ... ... ... ...
... ... ... ... ... ... ... ...
1 1 1 0 1 1 1 119
1 1 1 1 0 0 0 120 (INTEGER MODE ONLY)
1 1 1 1 0 0 1 121 (INTEGER MODE ONLY)
1 1 1 1 0 1 0 122 (INTEGER MODE ONLY)

09576-031
1 1 1 1 0 1 1 123 (INTEGER MODE ONLY)

Figure 33. Integer Divide Control Register (R0)

Register 0—Integer Divide Control The integer divide ratio sets the INT value in Equation 1. The
With R0[2:0] set to 000, the on-chip integer divide control register INT, FRAC, and MOD values make it possible to generate output
is programmed as shown in Figure 33. The internal VCO frequencies that are spaced by fractions of the PFD frequency.
frequency (fVCO) equation is Note that the demodulator LO frequency is given by fLO = fVCO/4.
fVCO = fPFD × (INT + (FRAC/MOD)) × 2 (1) Divide Mode
where: Divide mode determines whether fractional mode or integer mode
fVCO is the output frequency of the internal VCO. is used. In integer mode, the VCO output frequency, fVCO, is
INT is the preset integer divide ratio value (21 to 123 for integer calculated by
mode, 24 to 119 for fractional mode).
fVCO = fPFD × (INT) × 2 (2)
MOD is the preset fractional modulus (1 to 2047).
FRAC is the preset fractional divider ratio value (0 to MOD − 1).

Rev. A | Page 15 of 34
ADRF6801 Data Sheet
Register 1—Modulus Divide Control
With R1[2:0] set to 001, the on-chip modulus divide control register is programmed as shown in Figure 34. The MOD value is the preset
fractional modulus ranging from 1 to 2047.

MODULUS DIVIDE RATIO CONTROL BITS

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 0 0 0 0 0 MD10 MD9 MD8 MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0 C3(0) C2(0) C1(1)

MD10 MD9 MD8 MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0 MODULUS VALUE
0 0 0 0 0 0 0 0 0 0 1 1
0 0 0 0 0 0 0 0 0 1 0 2
... ... ... ... ... ... ... ... ... ... ... ...
... ... ... ... ... ... ... ... ... ... ... ...
1 1 0 0 0 0 0 0 0 0 0 1536 (DEFAULT)
... ... ... ... ... ... ... ... ... ... ... ...

09576-032
... ... ... ... ... ... ... ... ... ... ... ...
1 1 1 1 1 1 1 1 1 1 1 2047

Figure 34. Modulus Divide Control Register (R1)

Register 2—Fractional Divide Control
With R2[2:0] set to 010, the on-chip fractional divide control register is programmed as shown in Figure 35. The FRAC value is the preset
fractional modulus ranging from 0 to MOD − 1.

FRACTIONAL DIVIDE RATIO CONTROL BITS

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 0 0 0 0 0 FD10 FD9 FD8 FD7 FD6 FD5 FD4 FD3 FD2 FD1 FD0 C3(0) C2(1) C1(0)

FD10 FD9 FD8 FD7 FD6 FD5 FD4 FD3 FD2 FD1 FD0 FRACTIONAL VALUE
0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 1 1
... ... ... ... ... ... ... ... ... ... ... ...
... ... ... ... ... ... ... ... ... ... ... ...
0 1 1 0 0 0 0 0 0 0 0 768 (DEFAULT)
... ... ... ... ... ... ... ... ... ... ... ...

09576-033
... ... ... ... ... ... ... ... ... ... ... ...
FRACTIONAL VALUE MUST BE LESS THAN MODULUS <MOD

Figure 35. Fractional Divide Control Register (R2)

Register 3—Σ-Δ Modulator Dither Control

With R3[2:0] set to 011, the on-chip Σ-Δ modulator dither control register is programmed as shown in Figure 36. The dither restart value
can be programmed from 0 to 217 to 1, though a value of 1 is typically recommended.
DITHER DITHER
MAGNITUDE ENABLE DITHER RESTART VALUE CONTROL BITS
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 DITH1 DITH0 DEN DV16 DV15 DV14 DV13 DV12 DV11 DV10 DV9 DV8 DV7 DV6 DV5 DV4 DV3 DV2 DV1 DV0 C3(0) C2(1) C1(1)

DEN DITHER ENABLE

0 DISABLE
1 ENABLE (DEFAULT, RECOMMENDED)

DITH1 DITH0 DITHER MAGNITUDE

0 0 15 (DEFAULT)
0 1 7
1 0 3
1 1 1 (RECOMMENDED)

DITHER RESTART
DV16 DV15 DV14 DV13 DV12 DV11 DV10 DV9 DV8 DV7 DV6 DV5 DV4 DV3 DV2 DV1 DV0 VALUE
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0x00001 (DEFAULT)
... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ...
09576-034

... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ...
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0x1FFFF

Figure 36. Σ-Δ Modulator Dither Control Register (R3)

Rev. A | Page 16 of 34
Data Sheet ADRF6801
Register 4—Charge Pump, PFD, and Reference Path and the divided-down VCO signal. This phase offset is used to
Control linearize the PFD-CP transfer function and can improve
fractional spurs. The magnitude of the phase offset is
With R4[2:0] set to 100, the on-chip charge pump, PFD, and
determined by
reference path control register is programmed as shown in
Figure 37. θ PFD , OFS
ΔΦ [deg] = 22.5
The charge pump current is controlled by the base charge I CP , MULT
pump current (ICP, BASE) and the value of the charge pump
Finally, the phase offset can be either positive or negative
current multiplier (ICP, MULT).
depending on the value of the DB17 bit in Register 4.
The base charge pump current can be set using an internal or
The reference frequency applied to the PFD can be manipulated
external resistor (according to Bit DB18 of Register 4). When
using the internal reference path source. The external reference
using an external resistor, the value of ICP, BASE can be varied
frequency applied can be internally scaled in frequency by 2×,
according to
1×, 0.5×, or 0.25×. This allows a broader range of reference
 217.4 × I CP , BASE  frequency selections while keeping the reference frequency
RSET [Ω] =   − 37.8
 250  applied to the PFD within an acceptable range.
The actual charge pump current can be programmed to be a The ADRF6801 also provides a MUXOUT pin that can be
multiple (1, 2, 3, or 4) of the charge pump base current. The programmed to output a selection of several internal signals. The
multiplying value (ICP, MULT) is equal to 1 plus the value of the default mode provides a lock-detect output that allows users to
DB11 and DB10 bits in Register 4. verify when the PLL has locked to the target frequency. In addition,
several other internal signals can be routed to the MUXOUT pin as
The PFD phase offset multiplier (θPFD, OFS), which is set by Bit
described in Figure 37.
DB16 to Bit DB12 of Register 4, causes the PLL to lock with a
nominally fixed phase offset between the PFD reference signal

Rev. A | Page 17 of 34
ADRF6801 Data Sheet
PDF CHARGE
INPUT REF CHARGE PHASE CP CHARGE PFD ANTI-
OUPUT MUX PFD PHASE OFFSET PUMP PFD EDGE
PATH PUMP OFFSET CURRENT CNTL PUMP BACKLASH CONTROL BITS
SOURCE MULTIPLIER VALUE SENSITIVITY
SOURCE REF POLARITY MULTIPLIER SRC CONTROL DELAY

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
RMS2 RMS1 RMS0 RS1 RS0 CPM CPBD CPB4 CPB3 CPB2 CPB1 CPB0 CPP1 CPP0 CPS CPC1 CPC0 PE1 PE0 PAB1 PAB0 C3(1) C2(0) C1(0)

PAB1 PAB0 PFD ANTIBACKLASH

DELAY
0 0 0ns (DEFAULT,
RECOMMENDED)
0 1 0.5ns
1 0 0.75ns
1 1 0.9ns

REFERENCE PATH EDGE

PE0 SENSITIVITY
0 FALLING EDGE (RECOMMENDED)
1 RISING EDGE (DEFAULT)

DIVIDER PATH EDGE

PE1 SENSITIVITY
0 FALLING EDGE (RECOMMENDED)
1 RISING EDGE (DEFAULT)

CHARGE PUMP
CPC1 CPC0 CONTROL
0 0 BOTH ON
0 1 PUMP DOWN
1 0 PUMP UP
1 1 TRISTATE (DEFAULT)

CPS CHARGE PUMP CONTROL SOURCE

0 CONTROL BASED ON STATE OF DB7/DB8 (CP CONTROL)

1 CONTROL FROM PFD (DEFAULT)

CHARGE PUMP
CPP1 CPP0 CURRENT MULTIPLIER

0 0 1
0 1 2 (DEFAULT, RECOMMENDED)
1 0 3
1 1 4

CPB4 CPB3 CPB2 CPB1 CPB0 PFD PHASE OFFSET MULTIPLIER

0 0 0 0 0 0 × 22.5°/ICP, MULT
0 0 0 0 1 1 × 22.5°/ICP, MULT
... ... ... ... ... ...
0 0 1 1 0 6 × 22.5°/ICP, MULT (RECOMMENDED)
... ... ... ... ... ...
0 1 0 1 0 10 × 22.5°/ICP, MULT (DEFAULT)
... ... ... ... ... ...
1 1 1 1 1 31 × 22.5°/ICP, MULT

CPBD PFD PHASE OFFSET POLARITY

0 NEGATIVE
1 POSITIVE (DEFAULT, RECOMMENDED)

CPM CHARGE PUMP CURRENT

REFERENCE SOURCE
0 INTERNAL (DEFAULT)
1 EXTERNAL

INPUT REFERENCE
RS1 RS0 PATH SOURCE
0 0 2 × REFERENCE INPUT
0 1 REFERENCE INPUT (DEFAULT)
1 0 0.5 × REFERENCE INPUT
1 1 0.25 × REFERENCE INPUT

RMS2 RMS1 RMS0 OUTPUT MUX SOURCE

0 0 0 LOCK DETECT (DEFAULT)

0 0 1 VPTAT
0 1 0 BUFFERED VERSION OF REFERENCE INPUT
0 1 1 BUFFERED VERSION OF 0.5 × REFERENCE INPUT
1 0 0 BUFFERED VERSION OF 2 × REFERENCE INPUT
1 0 1 TRISTATE
09576-035

1 1 0 BUFFERED VERSION OF 0.25 × FREF

1 1 1 RESERVED (DO NOT USE)

Figure 37. Charge Pump, PFD, and Reference Path Control Register (R4)

Rev. A | Page 18 of 34
Data Sheet ADRF6801
Register 5—LO Path and Demodulator Control
Register 5 controls whether the LOIP and LOIN pins act as an input or output, whether the divider before the polyphase divider is in
divide-by-1 or divide-by-2, and whether the demodulator bias circuitry is enabled as detailed in Figure 38.

LO
DEMOD LO LO OUTPUT
BIAS FIRST IN/OUT DRIVER CONTROL BITS
ENABLE DIVIDER CTRL ENABLE
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMBE 0 LDIV LXL LDRV C3(1) C2(0) C1(1)

LO OUTPUT DRIVER
LDRV ENABLE

0 DRIVER OFF (DEFAULT)

1 DRIVER ON

LXL LO IN/OUT CONTROL

0 LO OUTPUT (DEFAULT)
1 LO INPUT

LDIV DIVIDE RATIO

0 ÷1
1 ÷ 2 (DEFAULT,
NECESSARY FOR VCO USE)

DMBE DEMOD BIAS ENABLE

09576-036
0 DISABLE
1 ENABLE (DEFAULT)

Figure 38. LO Path and Demodulator Control Register (R5)

Rev. A | Page 19 of 34
ADRF6801 Data Sheet
Register 6—VCO Control and Enables The VCO amplitude can be controlled through Register 6. The
With R6[2:0] set to 110, the VCO control and enables register is VCO amplitude setting can be controlled between 0 and 31
programmed as shown in Figure 39. decimal, with a default value of 24.

VCO band selection is normally selected based on BANDCAL
calibration; however, the VCO band can be selected directly using
Register 6. The VCO BS SRC determines whether the BANDCAL
calibration determines the optimum VCO tuning band or if the
external SPI interface is used to select the VCO tuning band
based on the value of the VCO band select.
The internal VCO can be disabled using Register 6. The internal
VCO LDO can be disabled if an external clean 3.0 V supply is
available.
The internal charge pump can be disabled through Register 6.
Normally, the charge pump is enabled.

CHARGE 3.3V VCO

PUMP LDO VCO LDO VCO VCO
VCO AMPLITUDE BS VCO BAND SELECT CONTROL BITS
ENABLE ENABLE ENABLE ENABLE SWITCH CSR
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 CPEN L3EN LVEN VCO EN VCO SW VC5 VC4 VC3 VC2 VC1 VC0 VBSRC VBS5 VBS4 VBS3 VBS2 VBS1 VBS0 C3(1) C2(1) C1(0)

VBS5 VBS4 VBS3 VBS2 VBS1 VBS0 VCO BAND SELECT

FROM SPI
0 0 0 0 0 0 0
... ... ... ... ... ... ...
1 0 0 0 0 0 32 (DEFAULT)
... ... ... ... ... ...
...
1 1 1 1 1 1 63

VBSRC VCO BAND CAL AND SW SOURCE CONTROL

0 BAND CAL (DEFAULT)
1 SPI

VC5 VC4 VC3 VC2 VC1 VC0 VCO AMPLITUDE

0 0 0 0 0 0 0
... ... ... ... ... ... ...
0 0 1 0 0 0 8 (DEFAULT)
... ... ... ... ... ... ...
1 0 1 1 1 1 47
... ... ... ... ... ... ...
1 1 1 1 1 1 63 (RECOMMENDED)

VCO SW VCO SWITCH CONTROL FROM SPI

0 REGULAR (DEFAULT)
1 BAND CAL

VCO EN VCO ENABLE

0 DISABLE
1 ENABLE (DEFAULT)

LVEN VCO LDO ENABLE

0 DISABLE
1 ENABLE (DEFAULT)

L3EN 3.3V LDO ENABLE

0 DISABLE
1 ENABLE (DEFAULT)

CPEN CHARGE PUMP ENABLE

09576-037

0 DISABLE
1 ENABLE (DEFAULT)

Figure 39. VCO Control and Enables (R6)

Rev. A | Page 20 of 34
Data Sheet ADRF6801

APPLICATIONS INFORMATION
BASIC CONNECTIONS
The basic circuit connections for a typical ADRF6801 application
are shown in Figure 40.
SUPPLY CONNECTIONS
The ADRF6801 has several supply connections and on-board
regulated reference voltages that should be bypassed to ground
using low inductance bypass capacitors located in close proximity
to the supply and reference pins of the ADRF6801. Specifically
Pin 1, Pin 2, Pin 9, Pin 10, Pin 17, Pin 22, Pin 27, Pin 29, Pin 34,
and Pin 40 should be bypassed to ground using individual bypass
capacitors. Pin 40 is the decoupling pin for the on-board VCO
LDO, and for best phase noise performance, several bypass
capacitors ranging from 100 pF to 10 µF may help to improve
phase noise performance. For additional details on bypassing the
supply nodes, see the evaluation board schematic in Figure 42.
SYNTHESIZER CONNECTIONS
The ADRF6801 includes an on-board VCO and PLL for LO
synthesis. An external reference must be applied for the PLL to
operate. A 1 V p-p nominal external reference must be applied
to Pin 6 through an ac coupling capacitor. The reference is
compared to an internally divided version of the VCO output
frequency to create a charge pump error current to control and
lock the VCO. The charge pump output current is filtered and
converted to a control voltage through the external loop filter
that is then applied to the VTUNE pin (Pin 39). ADIsimPLL™
can be a helpful tool when designing the external charge pump
loop filter. The typical Kv of the VCO, the charge pump output
current magnitude, and PFD frequency should all be considered
when designing the loop filter. The charge pump current magnitude
can be set internally or with an external RSET resistor connected to
Pin 5 and ground, along with the internal digital settings applied to
the PLL (see the Register 4—Charge Pump, PFD, and Reference
Path Control section for more details).
+5V

CHARGE PUMP
LOOP FILTER

IF I-OUTPUT
BALUN IF I-OUTPUT

40 39 38 37 36 35 34 33 32 31
LOSEL

VCCLO

IBBN
DECL1

IBBP
VTUNE

GND
LOP

GND
LON

+5V
+5V 1 VCC1 GND 30

2 DECL3 VCCBB 29

3 CPOUT GND 28

4 GND VCCRF 27 +5V

OPEN
5 RSET RFIN 26 RF INPUT
R2 ADRF6801
EXTERNAL 6 GNDRF 25
REFIN
REFERENCE

7 GND GND 24

MONITOR 8 MUXOUT GND 23

OUTPUT
9 DECL2 VCCBB 22 +5V

10 VCC2 GND 21
VCCLO

QBBP

QBBN
DATA

GND
GND

GND

GND
CLK

LE

+5V
11 12 13 14 15 16 17 18 19 20

SPI CONTROL IF Q-OUTPUT IF Q-OUTPUT

BALUN

+5V
09576-041

Figure 40. Basic Connections

Rev. A | Page 21 of 34
ADRF6801
I/Q OUTPUT CONNECTIONS
The ADRF6801 has I and Q baseband outputs. Each output
stage consists of emitter follower output transistors with a low
differential impedance of 24 Ω and can source up to 12 mA p-p
differentially. A Mini-Circuits TCM9-1+ balun is used to trans-
form a single-ended 50 Ω load impedance into a nominal 450 Ω
differential impedance.
RF INPUT CONNECTIONS
The ADRF6801 is to be driven single-ended and can be either dc
coupled or ac coupled. There is an on-chip ground referenced
balun that converts the applied single-ended signal to a differential
signal that is then input to the RF V-to-I converter.
CHARGE PUMP/VTUNE CONNECTIONS
The ADRF6801 uses a loop filter to create the VTUNE voltage
for the internal VCO. The loop filter in its simplest form is an
integrating capacitor. It converts the current mode error signal
coming out of the CPOUT pin into a voltage to control the VCO
via the VTUNE voltage. The stock filter on the evaluation
board has a bandwidth of 130 kHz. The loop filter contains
seven components, four capacitors, and three resistors. Changing
the values of these components changes the bandwidth of the loop
filter. Note that to obtain the approximately 2.5 kHz loop band-
width, the user can change the values of the following components
on the evaluation board to as follows: C14 = 0.1 µF, R10 = 68 Ω,
C15 = 4.7 µF, R9 = 270 Ω, C13 = 47 nF, R60 = 0 Ω, C4 = open.
LO SELECT INTERFACE
The ADRF6801 has the option of either monitoring a scaled
version of the internally generated LO (LOSEL pin driven high
at 3.3 V) or providing an external LO source (LOSEL pin driven
low to ground, the LDRV bit in Register 5 set low, and the LXL bit
in Register 5 set high). See the Pin Configuration and Function
Descriptions section for full operation details.
EXTERNAL LO INTERFACE
The ADRF6801 provides the option to use an external signal
source for the LO into the IQ demodulating mixer core. It is
important to note that the applied LO signal is divided down
by either 2 or 4 depending on the LO path divider bit, LDIV, in
Register 5, prior to the actual IQ demodulating mixer core. The
divider is determined by the register settings in the LO path
and mixer control register (see the Register 5—LO Path and
Demodulator Control section). The LO input pins (Pin 37 and
Pin 38) present a broadband differential 50 Ω input impedance.
The LOP and LON input pins must be ac-coupled. This is achieved
on the evaluation board via a Mini-Circuits TC1-1-13+ balun with
a 1:1 impedance ratio. When not in use, the LOP and LON pins
can be left unconnected.
Rev. A | Page 22 of 34
Data Sheet
SETTING THE FREQUENCY OF THE PLL
The frequency of the VCO/PLL, once locked, is governed by the
values programmed into the PLL registers, as follows:
fPLL = fPFD × 2 × (INT + FRAC/MOD)
where:
fPLL is the frequency at the VCO when the loop is locked.
fPFD is the frequency at the input of the phase frequency detector.
INT is the integer divide ratio programmed into Register 0.
MOD is the modulus divide ratio programmed into Register 1.
FRAC is the fractional value programmed into Register 2.
The practical lower limit of the reference input frequency is
determined by the combination of the desired fPLL and the maximum
programmable integer divide ratio of 119 and reference input
frequency multiplier of 2. For a maximum fPLL of 4600 MHz,
fREF > ~fPLL/(119 × 2 × 2), or 9.7 MHz.
A lock detect signal is available as one of the selectable outputs
through the MUXOUT pin, with logic high signifying that the
loop is locked.
When the internal VCO is used, the actual LO frequency is
fLO = fPLL/4
REGISTER PROGRAMMING
Because Register 6 controls the powering of the VCO and
charge pump, it must be programmed once before programming
the PLL frequency (Register 0, Register 1, and Register 2).
The registers should be programmed starting with the highest
register first and then sequentially down to Register 0 last. When
Register 0, Register 1, or Register 2 is programmed, an internal
VCO calibration is initiated that must execute when the other
registers are set. Therefore, the order must be Register 6, Register 5,
Register 4, Register 3, Register 2, Register 1, and then Register 0.
Whenever Register 0, Register 1, or Register 2 is written to, it
initializes the VCO calibration (even if the value
in these registers does not change). After the device has been
powered up and the registers configured for the desired mode of
operation, only Register 0, Register 1, or Register 2 must be
programmed to change the LO frequency.
If none of the register values is changing from their defaults,
there is no need to program them.
Data Sheet
EVM MEASUREMENTS
EVM is a measure used to quantify the performance of a digital
radio transmitter or receiver. A signal received by a receiver has
all constellation points at their ideal locations; however, various
imperfections in the implementation (such as magnitude imbalance,
noise floor, and phase imbalance) cause the actual constellation
points to deviate from their ideal locations.
ADRF6801
The ADRF6801 shows excellent EVM performance for 16 QAM.
Figure 41 shows the EVM of the ADRF6801 being better than
−40 dB over a RF input range of about +35 dB for the 16 QAM
modulated signal at a 10 MHz symbol rate. The pulse shaping
filter’s roll-off (alpha) was set to 0.35.
0

In general, a demodulator exhibits three distinct EVM limitations –5

vs. received input signal power. As signal power increases, the
–10
distortion components increase. At large enough signal levels,
where the distortion components due to the harmonic non- –15
linearities in the device are falling in-band, EVM degrades

EVM (dB)
–20
as signal levels increase. At medium signal levels, where the
demodulator behaves in a linear manner and the signal is well –25
above any notable noise contributions, the EVM has a tendency to
–30
reach an optimal level determined dominantly by either quadrature
accuracy and I/Q gain match of the demodulator or the precision –35
of the test equipment. As signal levels decrease, such that the
–40
noise is the major contribution, the EVM performance vs. the
signal level exhibits a decibel-for-decibel degradation with –45

09576-042
–65 –55 –45 –35 –25 –15 –5 5 15
decreasing signal level. At lower signal levels, where noise proves
INPUT POWER (dBm)
to be the dominant limitation, the decibel EVM proves to be
directly proportional to the SNR. Figure 41. EVM vs. Input Power, EVM Measurements at fRF = 900 MHz;
fIF = 0 MHz (that is, Direct Down Conversion); 16 QAM; Symbol Rate = 10 MHz
The basic test setup to test EVM for the ADRF6801 consisted
of an Agilent E4438C, which was used as a signal source. The
900 MHz modulated signal was driven single ended into the
RFIN SMA connector of the ADRF6801 evaluation board. The
IQ baseband outputs were taken differentially into two AD8130
difference amplifiers to convert the differential signals into single-
ended signals. A Hewlett Packard 89410A VSA was used to sample
and calculate the EVM of the signal. The ADRF6801 IQ base-
band output pins were presented with a 450 Ω differential load
impedance.

Rev. A | Page 23 of 34
ADRF6801 Data Sheet

EVALUATION BOARD LAYOUT AND THERMAL GROUNDING

An evaluation board is available for testing the ADRF6801. The the component values and suggestions for modifying the
evaluation board schematic is shown in Figure 42. Table 5 provides component values for the various modes of operation.

1 2
VCC VCC_RF VCC_BB VCC_LO VCC4
3 4
VCC_SENSE R55 S1
VCC R29 R32 R31 R13
0Ω 0Ω 0Ω 0Ω
OSC_3P3V
5 J1 6 10kΩ
3P3V_SENSE
R56 VCC_SENSE
7 8 R33 VCC_LO C28
OUTPUT_EN 2P5V_LDO 10kΩ VCC
LO_EXTERN 10µF
9 10 0Ω R6
LO_EXTERN VTUNE
VCO_LDO 0Ω VCC
LO VCC_LO
R59 OPEN
C8 C7 IBBP
OPEN 100pF 0.1µF
R3
R4
R38 R9 R60 R45 0Ω
CP T2 R40
0Ω 10kΩ 10kΩ 0Ω 3 4
R10 IOUT_SE
4 5 2 OPEN R41 P2 2 0Ω
C14 3kΩ C13 R46
6.8pF C4 T1
22pF C15 22pF 1 5
R37 2.7nF 3 1 0Ω R5
0Ω 0Ω
OPEN
R11 R12 IBBN
OPEN R1 0Ω 1nF
VCO_LDO 0Ω 1nF R39
3P3V1 C6 C5 C30
R15 C2 C1 0.1µF
0Ω 10µF 100pF
R27
R49 0Ω
3P3V_SENSE OPEN VCC_BB
40 39 38 37 36 35 34 33 32 31
VCC4 VCO_LDO C26 C27
DECL1

VTUNE

VCCLO

IBBN
LOP

LOSEL

IBBP
GND

GND
LON

100pF 0.1µF
R7 VCC_RF
VCC4 1 VCC1 GND 30
0Ω
R8 R26 VCC_RF
C9 C10
2 DECL3 VCCBB 29
0.1µF 100pF
C11 0Ω C12 0Ω
0.1µF 100pF 3 CPOUT GND 28 C24 C25
100pF 0.1µF

4 GND VCCRF 27
OPEN R28
5 RSET RFIN 26 RFIN
C31 R2 ADRF6801 0Ω
REFIN 6 REFIN GNDRF 25
R14 1nF
49.9Ω 7 GND GND 24
VCC_BB1
8 MUXOUT GND 23
R16 R25
REFOUT 9 DECL2 VCCBB 22 VCC_BB
0Ω 0Ω C23
C22
10 VCC2 GND 21
VCCLO

100pF 0.1µF
QBBN
QBBP
DATA

GND
GND

GND

GND
CLK

OPEN
LE

2P5V_LDO R18 QBBP

2P5V 11 12 13 14 15 16 17 18 19 20 R23
0Ω
C3 C17 C16 R21
10µF 0.1µF 100pF DATA R47 0Ω
T3 R43
LE 3 4
0Ω QOUT_SE
R58
R44 P3
2 0Ω
VCC R17 C34 R52 OPEN
OPEN C33 R51 R48
VCC2 OPEN OPEN 1 5
OPEN OPEN
0Ω 0Ω
R22
C19 C18 0Ω
CLK
0.1µF 100pF R57 OPEN
R30
0Ω 0Ω QBBN
C29 R42
C32 R50
OPEN OPEN 0.1µF
S2
R20
R35 R54
0Ω 0Ω VCC
R53
R19 0Ω 10kΩ
OPEN OPEN

R34
OUTPUT_EN
GND OPEN
LEGEND
R24 VCC_LO
NET NAME GND1 1 2 3 4 5
P1 C21 0Ω VCC_LO1
TEST POINT 6 7 8 9 C20
GND2 100pF
0.1µF 09576-044
SMA INPUT/OUTPUT

VTUNE DIG_GND

R36
0Ω

Figure 42. Evaluation Board Schematic

Rev. A | Page 24 of 34
Data Sheet ADRF6801
The package for the ADRF6801 features an exposed paddle on
the underside that should be well soldered to an exposed
opening in the solder mask on the evaluation board. Figure 43
illustrates the dimensions used in the layout of the ADRF6801
footprint on the ADRF6801 evaluation board (1 mil. = 0.0254 mm).
Note the use of nine via holes on the exposed paddle. These
ground vias should be connected to all other ground layers on
the evaluation board to maximize heat dissipation from the device
package. Under these conditions, the thermal impedance of the
ADRF6801 was measured to be approximately 30°C/W in still air.
0.012

0.050 0.035

09576-046
0.168
Figure 44. ADRF6801 Evaluation Board Top Layer

0.025

0.020
09576-043

0.177
0.232

Figure 43. Evaluation Board Layout Dimensions for the ADRF6801 Package

Figure 45. ADRF6801 Evaluation Board Bottom Layer 09576-047

Table 5. Evaluation Board Configuration Options

Component
VCC, VCC2, VCC4, VCO_LDO, VCC_LO,
VCC_LO1, VCC_RF, VCC_BB1, 3P3V1,
2P5V, CLK, DATA, LE, CP, DIG_GND,
GND, GND1, GND2
R1, R6, R7, R8, R13, R15, R17, R18,
R24, R25, R26, R27, R29, R31, R32,
R36, R49
Function Default Condition
Power supply, ground and other test points. VCC, VCC2, VCC4, VCC_LO, VCC_RF, VCC_BB1,
Connect a 5 V supply to VCC. VCC_LO1, VCO_LDO, 3P3V1, 2P5V =
Components Corporation TP-104-01-02,
CP, LE, CLK, DATA =
Components Corporation TP-104-01-06,
GND, GND1, GND2, DIG_GND =
Components Corporation TP-104-01-00
Power supply decoupling. Shorts or power supply R1, R6, R7, R8 = 0 Ω (0402),
decoupling resistors. R13, R15, R17 = 0 Ω (0402),
R18, R24, R25, R26, R27 = 0 Ω (0402),
R29, R31, R32 = 0 Ω (0402),
R36 = 0 Ω (0402),
Rev. A | Page 25 of 34
ADRF6801
Component
C1, C2, C3, C7, C8, C9, C10, C11, C12,
C16, C17, C18, C19, C20, C21, C22,
C23, C24, C25, C26, C27, C28
T1, C5, C6
R16, R14, R58, C31
R2, R9, R10, R11, R12, R37, R38, R59,
R60, C4, C14, C15, C13
R3, R4, R5, R21, R22, R23, R39, R40,
R41, R42, R43, R44, R45, R46, R47,
R48, C29, C30, T2, T3, P2, P3
R28
R30, R35, R50, R51, R52, R57, C32,
C33, C34, P1
R33, R55, R56, S1
Data Sheet
Function Default Condition
The capacitors provide the required decoupling of C1, C8, C10, C12 = 100 pF (0402),
the supply-related pins. C16, C18, C21, C22 = 100 pF (0402),
C24, C26 = 100 pF (0402),
C7, C9, C11 = 0.1 µF (0402),
C17, C19, C20, C23 = 0.1 µF (0402),
C25, C27 = 0.1 µF (0402),
C3, C2 = 10 µF (0603), C28 = 10 µF (3216)
External LO path. The T1 transformer provides C5, C6 = 1 nF (0603),
single-ended-to-differential conversion. C5 and C6 T1 = TC1-1-13+ Mini-Circuits
provide the necessary ac coupling.
REFIN input path. R14 provides a broadband 50 Ω R14 = 49.9 Ω (0402),
termination followed by C31, which provides the R16 = 0 Ω (0402),
ac coupling into REFIN. R16 provides an external R58 = open (0402),
connectivity to the MUXOUT feature described in C31 = 1 nF (0603)
Register 4. R58 provides option for connectivity to
the P1-6 line of a 9-pin D-sub connector for dc
measurements.
Loop filter component options. A variety of loop filter R12, R37, R38 = 0 Ω (0402),
topologies is supported using component R59 = open (0402),
placements C4, C13, C14, C15, R9, R10, and R60. R38 R9, R60 = 10 kΩ (0402),
and R59 provide connectivity options to numerous R10 = 3 kΩ (0402),
test points for engineering evaluation purposes. R2 R2, R11 = open (0402),
provides resistor programmability of the charge C13 = 6.8 pF (0402),
pump current (see Register 4 description). R37 C4, C14 = 22 pF (0402),
connects the charge pump output to the loop filter. C15 = 2.7 nF (1206)
R12 references the loop filter to the VCO_LDO. Default
values on board provide a loop filter bandwidth of
roughly 130 kHz using a 26 MHz PFD frequency.
IF I/Q output paths. The T2 and T3 baluns provide a R4, R5, R21, R22, = 0 Ω (0402),
9:1 impedance transformation; therefore, with a 50 Ω R40, R43, R45, R46 = 0 Ω (0402),
load on the single-ended IOUT/QOUT side, the center R47, R48 = 0 Ω (0402),
tap side of the balun presents a differential 450 Ω R3, R23, R39, R41, R42, R44 = open (0402),
to the ADRF6806. The center taps of the baluns are C29, C30, = 0.1 µF (0402),
ac grounded through C29 and C30. The baluns create T2, T3 = TCM9-1+ Mini-Circuits,
a differential-to-single-ended conversion for ease P2, P3 = Samtec SSW-102-01-G-S
of testing and use, but an option to have straight
differential outputs is achieved via populating R3,
R39, R23, and R42 with 0 Ω resistors and removing
R4, R5, R21, and R22. P2 and P3 are differential
measurement test points (not to be used as jumpers).
RF input interface. R28 provides the single-ended R28 = 0 Ω (0402)
RF input path to the on-chip RF input balun.
Serial port interface. A 9-pin D-sub connector (P1) R30, R35, R57 = 0 Ω (0402),
is provided for connecting to a host PC or control R50, R51, R52 = open (0402),
hardware. Optional RC filters can be installed on C32, C33, C34 = open (0402),
the CLK, DATA, and LE lines to filter the PC signals P1 = Tyco Electronics 5747840-3
through R50 to R52 and C32 to C34. CLK, DATA, and
LE signals can be observed via test points for debug
purposes. R58 provides a connection to the MUXOUT
for sensing lock detect through the P1 connector.
LO select interface. The LOSEL pin, in combination R33 = 0 Ω (0402),
with the LDRV and LXL bits in Register 5, controls R55, R56 = 10 kΩ (0402),
whether the LOP and LON pins operate as inputs or S1 = Samtec TSW-103-08-G-S
outputs. A detailed description of how the LOSEL pin,
LDRV bit, and the LXL bit work together to control
the LOP and LON pins is found in Table 4 under the
LOSEL pin description. Using the S1 switch, the
user can pull LOSEL to a logic high (VCC/2) or a logic
low (ground). Resistors R55 and R56 form a resistor
divider to provide a logic high of VCC/2. LO select
can also be controlled through Pin 9 of J1. The 0 Ω
jumper, R33, must be installed to control LOSEL via J1.
Rev. A | Page 26 of 34
Data Sheet ADRF6801
Component Function Default Condition
J1 Engineering test points and external control. J1 is a J1 = Molex Connector Corp. 10-89-7102
10-pin connector connected to various important
points on the evaluation board that the user can
measure or force voltages upon.
R19, R20, R34, R53, R54, S2 Provides ground connection for Pin 16. R20, R53 = 0 Ω (0402),
R34, R54 = open (0402),
R19 = open, S2 = open

Rev. A | Page 27 of 34
ADRF6801
ADRF6801 SOFTWARE
The ADRF6801 evaluation board can be controlled from PCs
using a USB adapter board, which is also available from Analog
Devices, Inc. The USB adapter evaluation documentation and
ordering information can be found on the EVAL-ADF4XXXZ-USB
product page. The basic user interfaces are shown in Figure 46 and
Figure 47.
The software allows the user to configure the ADRF6801 for
various modes of operation. The internal synthesizer is controlled
by clicking on any of the numeric values listed in RF Section.
Data Sheet
Attempting to program Ref Input Frequency, PFD Frequency,
VCO Frequency (2×LO), LO Frequency, or other values in RF
Section launches the Synth Form window shown in Figure 47.
Using Synth Form, the user can specify values for Local Oscillator
Frequency (MHz) and External Reference Frequency (MHz).
The user can also enable the LO output buffer and divider options
from this menu. After setting the desired values, it is important
to click Upload all registers for the new setting to take effect.

09576-048

Figure 46. Evaluation Board Software Main Window

Rev. A | Page 28 of 34
Data Sheet ADRF6801

09576-049
Figure 47. Evaluation Board Software Synth Form Window

Rev. A | Page 29 of 34
ADRF6801 Data Sheet

CHARACTERIZATION SETUPS
Figure 48 to Figure 50 show the general characterization bench To do phase noise and reference spur measurements, the setup
setups used extensively for the ADRF6801. The setup shown in shown in Figure 50 was used. Phase noise was measured at the
Figure 48 was used to do the bulk of the testing. An automated baseband output (I or Q) at a baseband carrier frequency of
Agilent VEE program was used to control the equipment over the 50 MHz. The baseband carrier of 50 MHz was chosen to allow
IEEE bus. This setup was used to measure gain, input P1dB, output phase noise measurements to be taken at frequencies of up to
P1dB, input IP2, input IP3, IQ gain mismatch, IQ quadrature 20 MHz offset from the carrier. The noise figure was measured
accuracy, and supply current. The evaluation board was used to using the setup shown in Figure 49 at a baseband frequency
perform the characterization with a Mini-Circuits TCM9-1+ balun of 10 MHz.
on each of the I and Q outputs. When using the TCM9-1+ balun
below 5 MHz (the specified 1 dB low frequency corner of the
balun), distortion performance degrades; however, this is not
the ADRF6801 degrading, merely the low frequency corner of
the balun introducing distortion effects. Through this balun,
the 9-to-1 impedance transformation effectively presented a 450 Ω
differential load at each of the I and Q channels. The losses of the
output baluns were de-embedded from all measurements.

Rev. A | Page 30 of 34
Data Sheet ADRF6801
IEEE

R&S SMA100
SIGNAL GENERATOR

IEEE
RF1 3dB

R&S SMT03 SIGNAL GENERATOR MINI-CIRCUITS

AGILENT 11636A ZHL-42W AMPLIFIER
POWER DIVIDER 3dB REF
(SUPPLIED WITH +15V dc
(USED AS COMBINER) FOR OPERATION)

IEEE RF2 3dB

3dB

R&S SMT03 SIGNAL GENERATOR RF

IEEE
CH A

CH B RF SWITCH MATRIX

HP 8508A
IEEE VECTOR
VOLTMETER

I CH RF Q CH
AGILENT MXA
SPECTRUM ANALYZER

6dB 3dB 6dB

IEEE IEEE

AGILENT 34980A
MULTIFUNCTION ADRF6801
AGILENT DMM SWITCH EVALUATION BOARD
(FOR ISUPPLY MEAS.) (WITH 34950 AND 2× 10-PIN
IEEE CONNECTION
34921 MODULES)
(+5V VPOS,
DC MEASURE)
AGILENT E3631A 6dB
POWER SUPPLY

9-PIN D-SUB CONNECTION

(VCO AND PLL PROGRAMMING) REF
IEEE
IEEE

IEEE

IEEE
09576-050

Figure 48. General Characterization Setup

Rev. A | Page 31 of 34
ADRF6801 Data Sheet

IEEE

AGILENT 8665B
LOW NOISE SYN
SIGNAL GENERATOR

REF

RF1

AGILENT 346B
NOISE SOURCE 3dB

RF

RF SWITCH MATRIX
IEEE 10MHz
LOW-PASS FILTER

AGILENT N8974A
NOISE FIGURE ANALYZER I CH RF Q CH

AGILENT DMM
(FOR ISUPPLY MEAS.)
6dB 3dB 6dB
E IEEE

AGILENT 34980A
MULTIFUNCTION ADRF6801
SWITCH EVALUATION BOARD
(WITH 34950 AND 2× 10-PIN
IEEE CONNECTION
34921 MODULES)
(+5V VPOS1,
DC MEASURE)
AGILENT E3631A 6dB
POWER SUPPLY

9-PIN D-SUB CONNECTION

IEEE

(VCO AND PLL PROGRAMMING)

REF

IEEE

IEEE
09576-051

Figure 49. Noise Figure Characterization Setup

Rev. A | Page 32 of 34
Data Sheet ADRF6801

IEEE

R&S SMA100
SIGNAL GENERATOR

IEEE REF
RF1

R&S SMA100
SIGNAL GENERATOR

IEEE 100MHz
LOW-PASS FILTER

3dB
AGILENT E5052 SIGNAL SOURCE
ANALYZER
RF

RF SWITCH MATRIX
IEEE

AGILENT MXA
SPECTRUM ANALYZER I CH RF Q CH
AGILENT DMM
(FOR ISUPPLY MEAS.)
6dB 3dB 6dB
E IEEE

AGILENT 34980A
MULTIFUNCTION ADRF6801
SWITCH EVALUATION BOARD
(WITH 34950 AND 2× 10-PIN
IEEE CONNECTION
34921 MODULES)
(+5V VPOS1,
DC MEASURE)
AGILENT E3631A 6dB
POWER SUPPLY
IEEE

I E IEEE 9-PIN D-SUB CONNECTION

(VCO AND PLL PROGRAMMING) REF
IEEE

IEEE

IEEE
09576-052

Figure 50. Phase Noise Characterization Setup

Rev. A | Page 33 of 34
ADRF6801 Data Sheet

OUTLINE DIMENSIONS
6.10 0.60 MAX
6.00 SQ
5.90 0.60 MAX
PIN 1
INDICATOR
31 40 1
30

PIN 1 5.85 0.50 EXPOSED 4.25

INDICATOR 5.75 SQ BSC PAD 4.10 SQ
(BOTTOM VIEW)
5.65 3.95
21 10
20 11
0.50 0.20 MIN
TOP VIEW 0.40
4.50 REF
0.30
12° MAX 0.80 MAX FOR PROPER CONNECTION OF
1.00 0.65 TYP THE EXPOSED PAD, REFER TO
0.85 THE PIN CONFIGURATION AND
0.05 MAX
0.80 FUNCTION DESCRIPTIONS
0.02 NOM SECTION OF THIS DATA SHEET.
0.30 COPLANARITY
SEATING 0.08
PLANE 0.23 0.20 REF

06-01-2012-D
0.18

COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2

Figure 51. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

6 mm × 6 mm Body, Very Thin Quad
(CP-40-1)
Dimensions shown in millimeters

ORDERING GUIDE
Ordering
Model1 Temperature Range Package Description Package Option Quantity
ADRF6801ACPZ-R7 −40°C to +85°C 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-40-1 750
ADRF6801-EVALZ Evaluation Board
1
Z = RoHS Compliant Part.

©2011–2018 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D09576-0-6/18(A)

Rev. A | Page 34 of 34