6.

Multiple Interrupts and the 8259A Priority Interrupt Controller

PIC
6.1 Introduction
Previous sections show how interrupts can be used for a variety of applications. In a small system,
for example, we might read ASCII characters in from a keyboard on an interrupt basis; and detect
several emergency or job-done conditions on an interrupt basis. Each of these interrupt applications
requires a separate interrupt input. If we are working with an 8086, we have a problem here because
the 8086 has only two interrupt inputs, NMI and INTR. If we save NMI for a power failure
interrupt, this leaves only one interrupt input for all the other applications. For applications where
we have interrupts from multiple sources such as this we use an external device called a priority
interrupt controller (PlC) to "funnel" the interrupt signals into an interrupt input on the processor. In
this section we show how a common PlC, the Intel 8259A, is connected in an 8086 system, how it
is initialized, and how it is used to handle interrupts from multiple sources.

6.2 Overview and System Connections

To show you how an 8259A functions in an 8086 system we first need to review how the 8086
INTR input works. Remember from a discussion earlier that if the 8086 interrupt flag is set and the
INTR input receives a high signal, the 8086 will:

1. Push the flags on the stack.

2. Clear the IF and TF.

3. Push the return address on the stack.

4. Put the data bus in the input mode.

5. Send out two interrupt acknowledge pulses on its INTA pin. The INTA pulses tell some
external hardware device such as an 8259A to send the desired interrupt type to the 8086.

6. When the 8086 receives the interrupt type from the external device, it will multiply that
interrupt type by 4 to produce an address in the interrupt pointer table.

7. From that address and the three following addresses the 8086 gets the IP and CS values for
the start of the interrupt service procedure. Once these values are loaded into CS and IP, the
8086 will then execute the interrupt service procedure.

Now if you look at the internal block diagram of the 8259A in Figure 6.1, I think you will be able to
start seeing how it fits into the INTR operation.

Data Bus Buffer The 8-bit data bus buffer and the data bus allow the 8086 to send control words
to the 8259A and read a status word from the 8259A and allows the 8259A to send interrupt types
to the 8086.

Read/Write Logic This is a typical Read/Write control logic. When the address line A0 is at logic
0, the controller is selected to write a command or read a status. The Chip Select logic and A0
determine the port address of the controller.

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Figure (6.1): 8259A Block Diagram

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Control Logic This block has two pins: INT (Interrupt) as an output, and INTA (Interrupt
Acknowledge) as an input. The INT is connected to the interrupt pin of the processor. Whenever a
valid interrupt is asserted, this signal goes high. The INTA is the Interrupt Acknowledge signal
from the processor.

Interrupt Registers and Priority Resolver The interrupt mask register (IMR) is used to disable
(mask) enable (unmask) individual interrupt inputs. Each IR in this register corresponds to the
interrupt input of the same number. You unmask an interrupt input by sending a command word
with a 0 in the bit position that corresponds to that input.

The interrupt request register (IRR) keeps track of which interrupt inputs are asking for service. If
an interrupt input is unmasked, and has an interrupt signal on it, then the corresponding bit in the
interrupt request register will be set.

The in-service register (ISR) keeps track of which interrupt inputs are currently being serviced. For
each input that is currently being serviced, the corresponding bit will be set in the in-service
register.

The Priority Resolver (PR) examines these three registers and determines whether INT should be
sent to the microprocessor.

Cascade Buffer/Comparator This block is used to expand the number of interrupt levels by
cascading two or more8259As.

6.3 Interrupt Operation

To implement interrupts, the Interrupt Enable flip-flop in the microprocessor should be enabled by
writing the STI instruction, and the 8259A should be initialized by writing control words in the
control register. The 8259A requires two types of control words:

Initialization Command Words (ICWs) and Operational Command Words (OCWs). The ICWs are
used to set up the proper conditions and specify interrupts types. The OCWs are used to perform
functions such as masking interrupts, setting up status-read operations. etc. After the 8259A is
initialized, the following sequence of events occurs when one or more interrupt request lines go
high:

1. The IRR stores the requests.

2. The priority resolver checks three registers: the IRR for interrupt requests, the IMR for
masking bits, and the ISR for the interrupt request being served. It resolves the priority and
sets the INT high when appropriate.

3. The 8086 microprocessor acknowledges the interrupt by sending two INTA signal.

4. On receiving first INTA the appropriate priority bit in the ISR is set to indicate which
interrupt level is being served, and the corresponding bit in the IRR is reset to indicate that
the request is accepted. On receiving the second INTA, the 8259A sends -through the data
bus to the microprocessor- the interrupt type corresponding to the IR input that received the
interrupt request. The 8086 will use the received type number to find and execute the
interrupt service procedure.

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 5. By the end of second INTA pulse, and if the 8259A was initialized with "Automatic End of
Interrupt" mode, then the corresponding bit in the ISR is reset. If the 8259A was not
initialized in that mode, then the corresponding bit in the ISR would stay set until the 8259A
receives a command word (EOI End Of Interrupt) at the end of the interrupt service routine
which resets that bit.

The point here is that the 8259A ‘funnels” interrupt signals from up to eight different sources into
8086 INTR input, and it sends the 8086 a specified interrupt type for each one of the eight interrupt
inputs.

6.4 Suppose that 1R2 and 1R4 are unmasked

Suppose that 1R2 and 1R4 are unmasked, and the 8259A is not initialized in the automatic-end-of-
interrupt, and that an interrupt signal comes in on the lR4 input. Since lR4 is unmasked, bit 4 of the
interrupt request register will be set. The priority resolver will detect that this bit is set and see if
any action needs to be taken. To do this it checks the bits in the in-service register (ISP) to see if a
higher priority input is being serviced. If a higher priority input is being serviced, as indicated by a
bit being set for that input in the ISR, then the priority resolver will take no action. If no higher
priority interrupt is being serviced, then the priority resolver will activate the circuitry which sends
an interrupt signal to the 8086. When the 8086 responds with INTA pulses, the 8259A will send the
interrupt type that we specified for the IR4 input when we initialized the device. The 8086 will use
the type number it receives to find and execute the interrupt service procedure we wrote for the 1R4
interrupt. Now, suppose that while the 8086 is executing the IR4 service procedure an interrupt
signal arrives at the IR2 input of the 8259A. Since we assumed for this example that 1R2 was
unmasked, bit 2 of the interrupt request register will be set. The priority resolver will detect that this
bit in the IRR is set and make a decision whether to send another interrupt signal to the 8086. To
make the decision, the priority resolver looks at the in-service register. If a higher priority bit in the
ISR is set, then a higher priority interrupt is being serviced. The priority resolver will wait until the
higher priority bit in the ISR is reset before sending an interrupt signal to the 8086 for the new
interrupt input. If the priority resolver finds that the new interrupt has a higher priority than the
highest priority interrupt currently being serviced, it will set the appropriate bit in the ISR and
activate the circuitry which sends a new INT signal to the 8086. For our example here, IR2 has a
higher priority than IR4 so the priority resolver will set bit 2 of the ISR and activate the circuitry,
which sends a new INT signal to the 8086. If the 8086 INTR input was reenabled with an STI
instruction at the start of the IR4 service procedure, as shown in Figure 8-28a, then this new INT
signal will interrupt the 8086 again. When the 8086 sends out a second INTA pulse in response to
this interrupt, the 8259A will send it the type number for the 1R2 service procedure. The 8086 will
use the received type number to find and execute the 1R2 service procedure.

At the end of the IR2 procedure we send the 8259A a command word that resets bit 2 of the in-
service register so that lower priority interrupts can be serviced. After that, an IRET instruction at
the end of the 1R2 procedure sends execution back to the interrupted 1R4 procedure. At the end of
the 1R4 procedure we send the 8259A a command word which resets bit 4 of the in-service register
so that lower priority interrupts can be serviced. An IRET instruction at the end of the IR4
procedure returns execution to the mainline program.

6.5 Cascading 8259As

The 8259A can be connected in a system containing one master and eight slaves (maximum) to
handle up to 64 priority levels.

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Note that since the 8086 has only one INTR Input, only one of the 8259A INT pins is connected to
the 8086 INTR pin. The 8259A connected directly into the 8086 INT pin is referred to as the
master. The INT pin from others 8259A connect into IR inputs on the master. These secondary or
cascaded devices are referred to as slaves. Note that the INTA signal from the 8086 goes both the
master and to the slaves devices. Each 8259A has its own addresses so that control words can be
written to it and status bytes read from.

Figure 6.3: 8259A and 8086 program flow for IR4 interrupt followed by IR2 interrupt. (a) Response
with INTR enabled in 1R4 procedure. (b) Response with INTR not enabled in lR4 procedure.

The master controls the slaves using CAS0, CAS1, and CAS2 which act as chip select inputs
(encoded) for slaves. These cascade lines (CASO, CAS1, and CAS2) are left open if we are not
cascading any slave 8259As. The cascade pins (CAS0, CAS1, and CAS2) from the master are
connected to the corresponding pins of the slaves. For the master these pins function as output and
for the slave device they function as inputs.

The multipurpose SP/EN pin is just to be tied high if that 8259A is the master, or if that 8259A is
the only one in the system. On the other hand, the SP/EN pins of the slaves are tied low to let the
devices know that they are slaves.

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Briefly, here is how the master and the slave work when the slave receives an interrupt signal on
one of its IR inputs. If that IR input is unmasked on the slave, and if that input is a higher priority
than any other interrupt level being serviced in the slave, then the slave will send an INT signal to
the IR input of the master. If that IR input of the master is unmasked and if that input is higher
priority than any other IR inputs currently being serviced, then the master will send an NT signal to
the 8086 INTR input. If the 8086 INTR is enabled, it will go through its INTR interrupt procedure
and send out two INTA pulses to both the master and the slave. The slave ignores the first interrupt
acknowledge pulse. When the master receives the first INTA pulse, it outputs a 3-bit slave
identification number on the CAS0, CAS1 and CAS2 lines. (Each slave in a system is assigned 3-
bit ID as part of its initialization.) Sending the 3-bit number enables the slave. When the slave
receives the second INTA pulse from the 8086, the slave will send the desired interrupt type
number to the 8086 on the eight data lines.

When entering the interrupt service routine the software has to check whether this is the only
request from the slave. This is done by sending a non-specific EOI command to the slave and then
reading its ISR, IRR and checking for zero. If its zero, a non-specific EOI can be sent to the master,
otherwise no EOI should be sent.

6.6 Priority Modes and Other Features

Priority Modes

Many types of priority modes are available under software control in the 8259A, and they can be
changed dynamically during the program by writing appropriate command words. Commonly used
priority modes are discussed below.

1. Fully Nested Mode This is the default mode of operation of 8259A. IR0 has the highest priority
and IR7 has the lowest one. If an ISR (in service) bit is set, all the same or lower priority interrupts
are inhibited but higher levels will generate an interrupt. The priorities can afterwards be changed
by programming the rotating priority modes.

2. Automatic Rotation Mode In this mode, a device, after being serviced, receives the lowest
priority. Assuming that the IR2 has just been serviced, it will receive the seventh priority, as shown
below:

IR3 IR4 IR5 IR6 IR7 IR0 IR1 IR2

0 1 2 3 4 5 6 7

the most priority level

3. Specific Rotation Mode This mode is similar to the automatic rotation mode, except that the user
can select any IR for the lowest priority, thus fixing all other priorities.

4. Special Fully Nested Mode This mode is used in more complicated systems, where cascading is
used and the priority has to be programmed in the master. This is somewhat similar to the normal
nested mode. In this mode, when an interrupt request from a certain slave is in service, this slave
can further send requests to the master, if the requesting device connected to the slave has higher
priority than the one being currently served. In this mode, the master interrupts the CPU both when
the interrupting device has a higher or the same priority than the one currently being served. In

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normal mode, other requests with the same priority or a lower than the one being served are masked
out. This mode is important, since in the absence of this mode, the slave would interrupt the master
only once and hence the priorities of the slave inputs would have been disturbed

End of Interrupt

After the completion of an interrupt service, the corresponding ISR bit needs to be reset to update
the information in the ISR. This is called the End-of-Interrupt (EO1) command. It can be issued in
three formats:

1. Nonspecific EOI Command When this command is sent to the 8259A, it resets the highest
priority ISR bit.

2. Specific EOI Command This command specifies which ISR bit to reset.

3. Automatic EOI In this mode, no command is necessary. During the last INTA the ISR bit is reset.
The major drawback with this mode is that the ISR does not have information on which IR is being
serviced. Thus, any JR can interrupt the service routine, irrespective of its priority, if the Interrupt
Enable flip-flop is set.

Poll Command
In polled mode of operation, the INT output of 8259A is neglected, though it functions normally, by
not connecting INT output or by masking INT input of the microprocessor. The 8259A is polled by
using software execution by microprocessor instead of the requests on INT input- The 8259A treats
the next RD pulse to the 8259A as an interrupt acknowledge. An appropriate ISR bit is set, if there
is a request. The priority level is read and a data word is placed on to data bus, after RD is activated.
The data word is shown in Fig. 6.3.

Figure 6.3: Priority Level data word

Interrupt Triggering

The 8259A can accept an interrupt request with either the edge-triggered mode or the level-
triggered mode. The mode is determined by the initialization instructions.

Interrupt Status

The status of the three interrupt registers (IRR, ISR, and IMR) can be read, and this status
information can be used to make the interrupt process versatile.

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6.7 Initializing an 8259A
The 8259A accepts two types of command words generated by the CPU:
1. Initialization Command Words (ICWs): Before normal operation can begin, each 8259A in
the system must be brought to a starting point—by a sequence of 2 to 4 bytes timed by WR
pulses.
2. Operation Command Words (OCWs): These are the command words which command the
8259A to operate in various interrupt modes. These modes are:
a. Fully nested mode
b. Rotating priority mode
c. Special mask mode
d. Polled mode
The OCWs can be written into the 8259A anytime after initialization.

INITIALIZATION COMMAND WORDS (ICWS)

General
Whenever a command is issued with A0 = 0 and D4 = 1, this is interpreted as Initialization
Command Word 1 (ICW1). ICW1 starts the initialization sequence during which the following
automatically occur.
1. The edge sense circuit is reset, which means that following initialization, an interrupt
request (IR) input must make a low-to-high transition to generate an interrupt.
2. The Interrupt Mask Register is cleared.
3. IR7 input is assigned priority 7.
4. The slave mode address is set to 7.
5. Special Mask Mode is cleared and Status Read is set to IRR.
6. If IC4 = 0, then all functions selected in ICW4 are set to zero. (Non-Buffered mode*, no
AutoEOI, MCS-80, 85 system).
* NOTE:
Master/Slave in ICW4 is only used in the buffered mode.

Initialization Command Words 1 and 2 (ICW1, ICW2)

A5 —A1 5: Page starting address of service routines. In an MCS 80/85 system, the 8 request levels
will generate CALLs to 8 locations equally spaced in memory. These can be programmed to be
spaced at intervals of 4 or 8 memory locations, thus the 8 routines will occupy a page of 32 or 64
bytes, respectively.
The address format is 2 bytes long (A0—A15). When the routine interval is 4, A0—A4 are
automatically inserted by the 8259A, while A5—A15 are programmed externally. When the routine
interval is 8, A0—A5 are automatically inserted by the 8259A, while A5—A15 are programmed
externally.
The 8-byte interval will maintain compatibility with current software, while the 4-byte interval is
best for a compact jump table.
In an 8086 system A15—A1 1 are inserted in the five most significant bits of the vectoring byte and
the 8259A sets the three least significant bits according to the interrupt level. A10—A5 are ignored
and ADI (Address interval) has no effect.

LTIM: If LTIM = 1, then the 8259A will operate in the level interrupt mode. Edge detect logic on
the interrupt inputs will be disabled.

ADI: CALL address interval. ADI = 1 then interval = 4; ADI = 0 then interval = 8.

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SNGL: Single. Means that this is the only 8259A in the system. If SNGL = 1 no ICW3 will be
issued.

1C4: If this bit is set—ICW4 has to be read. If ICW4 is not needed, set 1C4 = 0.

Initialization Command Word 3 (ICW3)

This word is read only when there is more than one 8259A in the system and cascading is used, in
which case SNGL = 0. It will load the 8-bit slave register. The functions of this register are:

1. In the master mode (either when SP = 1, or in buffered mode when M/S = 1 in ICW4) a ‘1”
is set for each slave in the system. The master then will release byte 1 of the call sequence
(for MCS80/85 system) and will enable the corresponding slave to release bytes 2 and 3 (for
8086 only byte 2) through the cascade lines.

2. In the slave mode (either when = 0, or if BUF = 1 and M/S = 0 in ICW4) bits 2—0 identify
the slave. The slave compares its cascade input with these bits and, if they are equal, bytes 2
and 3 of the call sequence (or just byte 2 for 8086) are released by it on the Data Bus.

Initialization Command Word 4 (ICW4)

SFNM: If SFNM = 1 the special fully nested mode is programmed.

BUF: If BUF = 1 the buffered mode programmed. In buffered mode SP/EN becomes an enable
output and the master/slave determination is by MIS.

MIS: If buffered mode is selected: MIS = 1 means the 8259A is programmed to be a master, M/S =
0 means the 8259A is programmed to be a slave. If SUE = 0, M/S has no function.

AEOI: If AEOI = 1 the automatic end of interrupt mode is programmed.

µPM: Microprocessor mode: µPM = 0 sets the 8259A for MCS-80, 85 system operation, µPM = 1
sets the 8259A for 8086 system operation.

OPERATION COMMAND WORDS (OCWS)

After the Initialization Command Words (ICWs) are programmed into the 8259A, the chip is ready
to accept interrupt requests at its input lines. However, during the 8259A operation, a selection of
algorithms can command the 8259A to operate in various modes through the Operation Command
Words (OCWs).

Operation Control Word 1 (OCW1)

OCW1 sets and clears the mask bits in the interrupt Mask Register (IMR). M7—M0 represent the
eight mask bits. M = 1 indicates the channel is masked (inhibited), M = 0 indicates the channel is
enabled.

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Figure 6.4: 8259A initialization command word formats and sending order. (a) Formats. (b)
Sending order and requirements.

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Operation Control Word 2 (OCW2)

A, SL, EOI— These three bits control the Rotate and End of Interrupt modes and combinations of
the two. A chart of these combinations can be found on the Operation Command Word Format.

L2, L1, L0— These bits determine the interrupt level accepted upon when the SL bit is active.

Operation Control Word 3 (OCW3)

ESMM—Enable Special Mask Mode. When this bit is set to 1 it enables the SMM bit to set or reset
the Special Mask Mode. When ESMM = 0 the SMM bit becomes a “don’t care”.

SMM— Special Mask Mode. If ESMM = 1 and SMM = 1 the 8259A will enter Special Mask
Mode. If ESMM = 1 and SMM = 0 the 8259A will revert to normal mask mode. When ESMM = 0,
SMM has no effect.

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 Figure 6.5: 8259A operational command words.

Problem 6.1
Show the sequence of command words and instructions that you would use to initialize an 8259A
with a base address of FF10H as follows:
edge-triggered; only one 8259A; 8086 system; interrupt type 40H corresponds to IR0 input; rotation
in AEOI; no buffered mode; IR1 and IR3 masked.
Read IRR, ISR into registers CL, DL respectively.

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Figure 6.6:
Cascading the 8259A

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