644 IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS, VOL. 8, NO.

1, MARCH 2020

An Integrated Interleaved Ultrahigh Step-Up

DC–DC Converter Using Dual Cross-Coupled
Inductors With Built-In Input Current
Balancing for Electric Vehicles
Hadi Moradisizkoohi , Student Member, IEEE, Nour Elsayad , Student Member, IEEE,
and Osama A. Mohammed , Fellow, IEEE

Abstract— An integrated interleaved dc–dc converter with

ultrahigh voltage gain and reduced voltage stress based on the
coupled-inductors and switched-capacitor circuits is proposed
in this article, which is suitable for interfacing the low-voltage
energy sources, such as fuel-cell, with a high-voltage dc bus
in electric vehicle applications. Input-parallel connection of the
coupled-inductors offers a reduced input current ripple and
the current rating of components, as well as automatic input
current sharing without a dedicated current sharing controller.
A promising power-density improvement technique is given,
in which only one magnetic core is utilized to implement two
coupled-inductors that can provide the filter functionality, as well
as transformer behavior. For suppressing the voltage ringing
resulting from the leakage inductors, the active-clamp configura- Fig. 1. General scheme of the power train of an HEV based on the fuel cell.
tion is employed that can facilitate the soft-switching performance
for all switches in a wide range of output power. A voltage
multiplier stage is adapted to not only boost the voltage gain
but help alleviate the reverse-recovery problem of diodes. The FC-powered HEV depicted in Fig. 1, where the voltage levels
steady-state performance, theoretical analysis, and a comparison of FC (about 20–30 V) are relatively low compared to that of
with the state-of-the-art converters are given in this article. dc-bus voltage. So, a high step-up dc–dc converter (HSUC) is
Finally, the experimental results of a 1-kW, 100-kHz prototype recognized as being the essential power conversion unit, which
are provided to confirm the validity of the proposed concept.
is characterized by having high-voltage gain, high power-
Index Terms— Coupled inductor, fuel cell, high step-up density, high reliability, high efficiency, and low cost [5]–[7].
dc–dc converter, soft switching, switched capacitor. Small input current ripple is another characteristic that is a key
performance indicator in FC-based power systems. In other
I. I NTRODUCTION words, the input current ripple directly impacts the lifetime of
FC system [8].
H YBRID electric vehicles (HEVs) have received much
attention in the past decade due to environmental and
economic benefits. Fuel-cell (FC)-powered HEVs are attract-
The conventional boost converter gives the desired voltage
gain with the least number of components; however, it suffers
ing considerable interest as FCs offer high-efficiency per- from high-voltage stress across power semiconductors, high
formance with the lowest emission, and they are cheap in power losses due to operation under extreme values of duty-
terms of capital cost compared to other renewable energy cycle to obtain the required voltage gain, and the reverse-
sources [1]–[4]. General scheme of the power train of an recovery problem of diode [9]. Different topologies have been
proposed to address the drawbacks of the conventional con-
Manuscript received May 31, 2019; revised August 12, 2019; accepted verter, such as multilevel circuit, switched-capacitor, switched
September 3, 2019. Date of publication September 23, 2019; date of current inductor, and so forth [10]–[14]. Generally, current-fed
version February 3, 2020. This work was supported in part by grants
from the U.S. Department of Energy and in part by the Office of Naval dc–dc converters with transformer or coupled-inductor can
Research. Recommended for publication by Associate Editor Zhiliang Zhang. suffice the needs of the system in terms of high-voltage gain
(Corresponding author: Osama A. Mohammed.) and low input current ripple; therefore, they are extensively
The authors are with the Energy Systems Research Laboratory, Depart-
ment of Electrical and Computer Engineering, College of Engineering and applied in different applications. However, a huge voltage and
Computing, Florida International University, Miami, FL 33174 USA (e-mail: current spike appear on the semiconductors due to the leakage
mohammed@fiu.edu). inductance and parasitic capacitance [15], [16]. The discontin-
Color versions of one or more of the figures in this article are available
online at http://ieeexplore.ieee.org. uous input current is responsible for the high electromagnetic
Digital Object Identifier 10.1109/JESTPE.2019.2943301 interference (EMI), while the pulsed output current causes the
2168-6777 © 2019 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

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MORADISIZKOOHI et al.: INTEGRATED INTERLEAVED ULTRAHIGH STEP-UP DC–DC CONVERTER
Fig. 2. Conventional interleaved boost dc–dc converter.
higher output voltage ripple in the circuit [17]. The passive
and active-clamp circuit can be employed to not only suppress
the voltage stress across the power devices but provide the
condition for soft-switching operation. Hence, for application
where galvanic isolation is not necessary, such as for HEV
powertrain applications, using coupled-inductor provides a
parameter other than duty-cycle to level up the voltage of input
source. Numerous studies have attempted to adopt the high-
frequency coupled inductors to boost the voltage level. Along
with high-voltage gain, a family of front-end dc/dc converters
with high efficiency has been introduced in [18], in which a
passive regenerative circuit is employed to recycle the leakage
energy of coupled inductors, as well as alleviate the reverse
recovery problem of the output diode. Multilevel modular
dc–dc converter (MMC) is becoming an indispensable topol-
ogy in high output voltage applications, where the switches
experience high-voltage stress [19]. Nevertheless, the main
drawback of MMC is that the voltage conversion ratio depends
on the number of stages, and thereby, the wide-range voltage
gain cannot be achieved. Besides, the voltage stresses across
the different switches are not identical [20].
To handle high current at the input stage, the interleaved
connection has been introduced that can not only shrink the
input current ripple but also reduce the size of the input
filter [21], [22]. Superior thermal distribution is another merit
of the interleaved configuration. A conventional interleaved
boost dc–dc converter (CIBC) is depicted in Fig. 2, where two
boost inductors are utilized to reduce the input current ripple,
and the transformer is responsible for providing isolation,
as well as high-voltage gain [23]. Nevertheless, the high
number of magnetic cores impedes using this converter for
high-power HEVs where the size is crucial. The combination
of the built-in transformer and interleaved dc–dc converters is
recognized as being the most important solution for increasing
the voltage conversion ratio of high-power applications with
high-voltage gain [24], [25]. However, the main issue is that
any mismatch between the parameters of two phases leads to
an unequal sharing of the input current between two phases.
The solution to this problem would be adopting a complicated
control scheme [26]–[29]. In order to simplify the controller,
a converter has been proposed for automatic current sharing
by means of a particular cross coupling configuration [27].
Nevertheless, due to the small parasitic capacitance of the
switches, realizing soft-switching performance is impossible
since the capacitor cannot store the energy during turn-off,
resulting in high switching losses.
An integrated interleaved ultrahigh step-up dc–dc con-
verter (IIUHSC) using dual coupled-inductors is introduced in
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645
this article, which offers high-voltage conversion ratio and
high efficiency due to the soft-switching performance that
makes it a potential candidate for FC- powered HEVs applica-
tions. The proposed converter provides advantages, including
a high-voltage gain, low voltage-stress of power devices,
zero voltage switching (ZVS) performance at turn-on and turn-
off, and smaller magnetic size by integrating the input filters
and the coupled-inductors, in comparison with CIBC. To step-
up the voltage level of the converter, a voltage multiplier
stage, including a built-in transformer and switched-capacitor
circuit, is adopted. This stage enables recovering the energy of
leakage inductance in to improve the efficiency by storing the
energy in the capacitors and then transferring it to the output
capacitors. Besides, the voltage balance of output capacitors
is realized inherently without the use of extra voltage-sharing
circuit, resulting in equally distributed voltage stress across the
output diodes. For decreasing the voltage stress of switches, as
well as obtain soft-switching performance for all switches, an
active-clamp technique is implemented in the proposed con-
verter. As a result, lower voltage rating switches with smaller
on-resistance RDS(ON) can be employed that leads to more
moderate conduction loss. Furthermore, the cross-coupling of
the coupled-inductors paves the way for sharing the input
current equally between two phases, even in the case, where
there is a mismatch between the parameters of two phases,
which contributes to a reduction in the size of the capacitive
filter and the current rating of power devices.
This article is divided into five sections. Section II presents
the schematic and operating principle of the proposed con-
verter. Steady-state analysis of the proposed converter is
presented in Section III. Also, a comparison with other
state-of-the-art HSUC in terms of main performance charac-
teristics is carried out in this section. Design considerations of
a prototype are given in Section IV. A laboratory prototype
is implemented, and some experimental results are given
in Section V. Some conclusions are drawn in the final section.
II. P ROPOSED I NTEGRATED I NTERLEAVED U LTRAHIGH
S TEP -U P DC–DC C ONVERTER W ITH
D UAL C OUPLED -I NDUCTORS
A. Circuit Configuration
The general layout of the proposed IIUHSC is shown
in Fig. 3(a), which is derived from the interleaved
half-bridge converter. The IIUHSC consists of a current-auto-
balance integrated interleaved stage (CABIIS), a ZVS active-
clamp switching stage (ACSS), and a voltage multiplier stage
(VMS). CABIIS is comprised of the primary windings of
two coupled inductors, connected in a way that the automatic
current distribution can be realized, and the current stress
of semiconductors can be reduced. ACSS paves the way
for the soft-switching performance and confining the voltage
stress across the switches. The high-voltage conversion ratio is
achieved by virtue of the VMS, which is composed of series-
connection of the secondary windings of coupled inductors.
The multiplier capacitors not only help increase the voltage
gain but also serve as the dc-blocking capacitor. As a result,
the converter operates in continuous conduction mode (CCM).
646 IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS, VOL. 8, NO. 1, MARCH 2020
Fig. 3. Proposed IIUHSC converter. (a) Schematic. (b) Equivalent circuit
with magnetic component model.
As shown in Fig. 3(a), in the proposed concept, only one
magnetic core is utilized to fulfill the functions of both
input filters and coupled inductors. Fig. 3(b) demonstrates the
equivalent circuit of the proposed converter, where S1 and S2
represent the main switches; SC1 and SC2 denote the clamp
switches; CC is the clamp capacitor; Do1 and Do2 denote the
output diodes; Dr1 and Dr2 represent the regenerative diodes;
Cm1 and Cm2 denote the multiplier capacitors; Vin , Vout , and
Rout denote the input voltage, output voltage, and the load,
respectively. Also, the coupled inductors are modeled by the
ideal transformers, the leakage inductors L k1 and L k2 , and the
magnetizing inductors L m1 and L m2 . Note that the primary
inductor L 1a with N1a turns is coupled with its secondary
inductor L 2a with N2a turns. Similarly, the primary inductor
L 1b with N1b turns is coupled with its secondary inductor L 2b
with N2b turns. To simplify the analysis, turns-ratio is defined
by n = N2b /N1a = N2a /N1a .
B. Operation Modes
Due to the specific connection of coupled-inductors and
dc-blocking capacitor at the secondary side, the IIUHSC oper-
ates in CCM; so, the duty cycle should be more than 0.5. The
duty cycles (D) of the main switches are identical, and there
is a phase shift of 180◦ between the gate pulses of the main
switches. The operation of the converter during one switching
period Ts can be divided into 16 modes, as illustrated in Fig. 4.
Due to the symmetry of the circuit, only 8 operation modes
are analyzed in this section, which are depicted in Fig. 5 and
are explained in the following.
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Fig. 4. Key waveforms of the proposed converter.
The operating principle and characteristics of the proposed
converter are demonstrated with the following assumptions:
1) the capacitors CC , CO , Caux are large enough so that they
can be taken as constant voltage sources and 2) all switches
S1 –S4 are considered to be ideal.
Mode 1 [t0 ∼ t1 ]: Prior to t0 , the main switches are on,
and the clamp switches are off. All the diodes are reversed-
biased. During this mode, the magnetizing and the leakage
inductors, L m1 and L m2 , L k1 and L k2 , are being charged by the
input voltage linearly. As shown in Fig. 5(a), the load is being
supplied by output capacitors. This mode can be described by
Vin
i Lm1,2 (t) = i Lk1,2 (t) = i Lm1,2 (t0 ) + (t − t0 ).
L m1,2 + L k1,2
(1)
Mode 2 [t1 ∼ t2 ]: At t1 , the gate-pulse of S1 is removed,
and it turns off, as depicted in Fig. 5(b). Since the parasitic
capacitor of switch S1 controls the voltage variation across the
switch, the ZVS performance at turn-off can be achieved. Due
to the small capacitance of the parasitic capacitor, the voltage
of switch S1 charges linearly and can be expressed as
i Lm1 (t1 )
vds1 (t) ∼
= (t − t1 ). (2)
Cs1
At the end of this mode, the voltage of the switch reaches to
the clamp capacitor voltage VCc .
Mode 3 [t2 ∼ t3 ]: This mode starts when the antipar-
allel diodes of switch SC1 start conducting the current. So,
the voltage stress of switch S1 is clamped to VCc , as shown
in Fig. 5(c). In the meanwhile, the energy of the input source
is being stored in the magnetizing and leakage inductors.
MORADISIZKOOHI et al.: INTEGRATED INTERLEAVED ULTRAHIGH STEP-UP DC–DC CONVERTER 647

Fig. 5. Operation modes in one switching period. (a) Mode 1 [t0 ∼ t1 ]. (b) Mode 2 [t1 ∼ t2 ]. (c) Mode 3 [t2 ∼ t3 ]. (d) Mode 4 [t3 ∼ t4 ].
(e) Mode 5 [t4 ∼ t5 ]. (f) Mode 6 [t5 ∼ t6 ]. (g) Mode 7 [t6 ∼ t7 ]. (h) Mode 8 [t7 ∼ t8 ].

Mode 4 [t3 ∼ t4 ]: At the beginning of this mode, the Other components operate in a similar way as in mode 7.
diodes Do1 and Dr2 turn on. In this mode, the energy stored At the end of this mode, the diodes Do1 and Dr2 are cutoff.
in the magnetizing inductors is transferred to the output As shown in Fig. 4, in the remaining operation modes, the
capacitor Co1 . As illustrated in Fig. 5(d), the multiplier circuit performance is similar due to the symmetry of the con-
capacitor Cm1 is discharged in this mode. The equations verter. Indeed, in the CABIIS circuit, the operating principle
describing this mode are given as follows: of switches S2 and Sc2 are similar to those of switches S1
Vin − VCc and Sc1 , and identical commutation process happens between
i Lm1 (t) = i Lm1(t3 ) + (t − t3 ) (3) the switches S2 and SC2 . In the VMS, the diodes Do2 and Dr1
L m1
Vo1 − VCm1 − (n + 1)VCc conduct the current.
i Lk1 (t) = i Lk1(t3 ) + (t − t3 ) (4)
n L k1
Vo1 − VCm1 − (n + 1)VCc III. S TEADY-S TATE P ERFORMANCE A NALYSIS
i Lk2 (t) = i Lk2(t3 ) − (t − t3 ). (5) A. General Assumptions
n L k2
Mode 5 [t4 ∼ t5 ]: At the beginning of this mode, In order to simplify the steady-state analysis, the parameters
the turn-on pulse is applied to the gate of SC1 . Therefore, the of coupled inductors and switches are considered identical, i.e.,
ZVS performance of SC1 is achieved. As shown in Fig. 5(e), L k1 = L k2 = L k , L m1 = L m2 = L m , and CS1 = CS2 = CS .
the equivalent circuit of the converter in this mode is the same Also, the VMS capacitors, as well as the output capacitors,
as that of the previous mode. are assumed to be identical due to the symmetry of converter,
Mode 6 [t5 ∼ t6 ]: At t = t5 , the clamp switch Sc1 i.e., Cm1 = Cm2 = Cm and Co1 = Co2 = Co . Furthermore,
turns off. Then a resonant circuit composed of the leakage it is estimated that the voltage of all the capacitors except
inductor L k1 and the parasitic capacitor of switch CS1 is the parasitic capacitance of switches is constant during one
formed. Accordingly, the current of L k1 changes linearly due switching period since their capacitance is relatively high.
to the small capacitance of CS1 , and the stored energy of
CS1 is transferred to the leakage inductor. During this mode, B. Voltage Gain
the voltage of the switch Sc1 increases linearly as well. The
Similar to the conventional boost converter, the volt-
equivalent circuit in this mode is shown in Fig. 5(f). The
age of the clamp capacitor can be obtained by applying
voltage of switch S1 can be defined by
the volt-second balance to the magnetizing inductors as
i Lm1 (t5 )
vds1(t) ∼
= VCc − (t − t5 ). (6) follows:
Cs1 Vin
VCc = . (8)
Mode 7 [t6 ∼ t7 ]: At t = t6 , the voltage of switch S1 1− D
becomes zero, and its antiparallel diode turns on. The current In (8), D denotes the duty-cycle of the main switches S1
of diodes Do1 and Dr2 decreases linearly, and its slope is and S2 . From (4), the rising rate of the output diode current
controlled by the leakage inductance is defined by
Vo1 − VCm1 Vo1 − VCm1 − (n + 1)VCc
i Lk1(t) = i Lk1(t6 ) − (t − t6 ). (7) krise =
di Do1
= . (9)
n 2 L k1 dt 4n 2 L k
Mode 8 [t7 ∼ t8 ]: At the beginning of this mode,
From (7), the falling rate of the output diode current iDo1
the turn-on pulse of switch S1 is applied while its antiparallel
can be determined by
diode is conducting; therefore, the switch S1 turns on with
ZVS operation. Moreover, the magnetizing and leakage induc- di Do1 −Vo1 + VCm1
kfall = = . (10)
tors, L m1 and L k1 , are being charged by input source. dt 4n 2 L k

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648 IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS, VOL. 8, NO. 1, MARCH 2020

two coupled inductors are decoupled magnetically due to the

short magnetic reluctance of the center leg without air gap.
So, only the mismatches between N1a /N2a and N1b /N2b are
considered. The average magnetizing current can be written
as
Iin 2n i + 1
ILmi, avg = = Iout . (16)
2 (1 − Di )
For the sake of simplicity, the parameter is defined as
ILm,avg/Iin = (ILm1,avg − ILm2,avg )/ILm2,avg + ILm1,avg).
From (4), the ratio of average magnetizing current ILm1,pk
and ILm2,pk can be defined by
ILm2,avg (1 − D1 )(2n 2 + 1)
= . (17)
Fig. 6. Voltage gain of the proposed converter as a function of duty cycle, ILm2, avg (1 − D2 )(2n 1 + 1)
turns-ratio, and leakage inductance.
Assuming that the parameters of the first branch are con-
stant, defined as D2 = D and L m1 = L m , and there are
From (4) and (10), the peak current and the fall time of the variations in the parameters of the first branch; defining D1 =
output diode current i Do1 can be calculated as follows: D+D and L m1 = L m +L m . Then, to simplify the analysis,
VCm1 + (n + 1)VCc − Vo1 a function is defined as follows:
IDo1,Peak = (1 − D)Ts (11) (2n + 1)
4n 2 L k f (D, L) = . (18)
IDo1,Peak VCm1 + (n + 1)VCc − Vo1 (1 − D)
tfall = = (1 − D)Ts
−kfall Vo1 − VCm1 By applying the first-order approximation, we have
(12)
∂f ∂f
f (D + D, L m + L m ) ≈ f (D, L m )+ D + L m .
where Ts denotes the switching period. By applying Kirch- ∂D ∂L
hoff’s Voltage Law (KVL) to the converter when switches S1 (19)
and Sc2 are on and the diodes Do2 and Dr1 are conducting the Combining (18) and (19) and substituting into (17),
current (Mode 13), the voltage of multiplier capacitor Cm1 can the parameter ILm,pk /Iin can be expressed as
be written as
ILm, avg D n L m
VCm1 = (n + 1)VCc . (13) = 0.5 + . (20)
Iin 1− D 2n + 1 L m
In the steady state, the average current of a capacitor is The similar analysis can be applied to the maximum mag-
zero; so, the average current of output diode Do1 is equal to netizing current, which is defined by
the average output current, which can be written as  
2n + 1 Ts Di (1 − Di )
Vout 1 ILmi, pk = Vout + . (21)
Iout = IDo1,avg = = IDo1,Peak [(1 − D)Ts + tfall ]. Rout (1 − Di ) 4L mi (2n + 1)
Rout 2Ts
To simplify analysis, the parameter is defined as
(14)
ILm,pk /Iin = (ILm1,pk − ILm2,pk )/(ILm2,pk + ILm1,pk ). From (4),
By considering (8)–(14), the voltage gain of the proposed the maximum magnetizing current ILm1,pk and ILm2,pk can be
converter can be determined by defined by (22), as shown at the bottom of the next page.
Then, combining (21) and (22) and substituting into (20),
Vout 4(2n + 1)
M= =  (15) the parameter ILm,pk /Iin can be expressed as (23), as shown
Vin (1 − D) + (1 − D)2 + 6k at the bottom of the next page.
where k = 8n 2 (2n+1) L k /(n + 1) Ts Rout . Fig. 6 demonstrates From (17), it is obvious that the magnetizing currents of
the relationship between the voltage gain and the duty-cycle two branches are equal (ILm,pk = 0) if the parameters of two
for different values of leakage inductance L k , which obviously branches are identical, i.e., D = L m = 0. Fig. 7(a) and (b)
indicates that a high-voltage gain is achieved even with a small show the effect of the mismatches in the parameters of coupled
duty cycle. Moreover, the voltage gain reduces as the leakage inductors on the current sharing characteristics, in which
inductance increases. α = D/(1–D), β = L/L, n = 1.5, D = 0.65, Ro = 160,
Ts = 10 μs, and L = 50 μH. It can be seen that the
mismatches in the duty cycle values, as well as the parameters
C. Automatic Input Current Sharing of coupled inductors, has a negligible impact on the sharing
In this section, the effects of mismatches in the individual the input current between two phases.
circuit parameters, including the magnetizing inductance and In Fig. 7(a), the difference between the average of magnetiz-
duty cycle, on the automatic current sharing capability of ing currents is depicted, which clearly indicates that the current
the converter is investigated. These mismatches happen in can be equally divided even with some variations in the circuit
a practical situation. It is noteworthy to mention that the parameters. Also, the maximum magnetizing currents can be

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MORADISIZKOOHI et al.: INTEGRATED INTERLEAVED ULTRAHIGH STEP-UP DC–DC CONVERTER 649

The flux values flowing through outer and center legs can
be expressed as
(NP IP1 + NS IS1 + α(NP IP2 + NS IS2 ))
φ1 = (25)
(1 + α)Ro
(NP IP2 + NS IS2 + α(NP IP1 + NS IS1 ))
φ2 = (26)
(1 + α)Ro
(1 − α)(NP IP1 + NS IS1 − (NP IP2 + NS IS2 ))
φC = (27)
(1 + α)Ro
where α = RC /(RC + RO ), and IP1 and IS1 represent the
current flowing through the primary and secondary windings
of the inductor L 1a and L 2a , respectively. Also, IP2 and
IS2 represent the current flowing through the primary and
secondary windings of the inductor L 1b and L 2b , respectively.
According to the analysis given in the previous sections,
the average value of the current flowing through different legs
can be determined by

IP1,avg = IP2,avg = 0.5Iin (28)

IS1,avg = IS2,avg = 0. (29)

From Fig. 8(b), the dc analysis of the fluxes in the outer

and center legs can be calculated by

Fig. 7. Automatic current sharing performance. (a) Effect of mismatches NP Iin (1 + α)L P Iin
in the parameters on the average current of magnetizing inductors. (b) Effect φ1,dc = = (30)
2Ro 2NP
of mismatches in the parameters on the maximum current of magnetizing
NP Iin (1 + α)L P Iin
inductors. φ2,dc = = (31)
2Ro 2NP
φC,dc = φ1,dc − φ2,dc = 0 (32)
approximately equal even with the presence of the mismatch
in the circuit parameters, as illustrated in Fig. 7(b). From where L P1 = L P2 = L P = NP2 /((1 + α)RO ).
the aforementioned analysis, the current sharing characteristics The ac-component of the flux in different mode can be
of the converter is realized even with the presence of the obtained from Fig. 8(c). In mode 1, the following equations
mismatches in the different parameters of circuit resulting from can be written as follows:
the driver cell, as well as fabrication of coupled inductors.
DTS Vin (1 + α)L m Iin
φ1,ac = φ2,ac = = (33)
D. Magnetic Integration NP 2
φC,ac = φ1,ac − φ2,ac = 0. (34)
In this section, implementing the advanced magnetic inte-
gration technology as a means to improve the power density Similarly, the ac-component of the flux in mode 2 can be
of the proposed converter is discussed. The coupled inductors expressed by
are wound around outer legs, which provides the condition
(1 − D)TS (Vin − VCc ) −DTS Vin
to decouple them magnetically as the center leg enables a φ1,ac = = (35)
low permeable magnetic path. The magnetic and electrical NP NP
equivalent circuit of the coupled inductors can be established (1 − D)TS Vin
φ2,ac = (36)
according to Fig. 8(a) and (b), respectively. For simplifying NP
the analysis, it is assumed that the reluctance values of the −TS Vin
φC,ac = φ1,ac − φ2,ac = . (37)
outer legs are equal. The maximum value of the flux density NP
can be calculated according to (24)
  Due to the symmetry of the circuit, the flux variation in
 φac 
φMax = φdc +  . (24) other operation modes can be calculated similarly. Similar to
2  Mode 2, the ac-component of the flux in the center leg is zero

ILm2, pk L m2 (1 − D2 ) 4L m1 (2n + 1)2 + Rout Ts D1 (1 − D1 )2

= (22)
ILm2, pk L m1 (1 − D1 ) 4L m2 (2n + 1)2 + Rout Ts D2 (1 − D2 )2
ILm, pk 4L m (2n + 1)2 + Ro Ts (1 − 2D)(1 − D)2 D Ro Ts D(1 − D)2 L
= − (23)
Iin 8L m (2n + 1)2 + 2Ro Ts D(1 − D)2 1− D 8L m (2n + 1)2 + 2Ro Ts D(1 − D)2 L

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650 IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS, VOL. 8, NO. 1, MARCH 2020

Fig. 8. Flux flow path, the electrical equivalent circuit, and flux and current waveforms during different operation modes. (a) Flux flow path. (b) Electrical
equivalent circuit of the coupled-inductors. (c) Flux and current waveforms during different operation modes.

in mode 3. From (24)–(37), the maximum value of the flux in

different legs can be determined by
(1 + α)L m Iin DTS Vin
φ1,Max = + (38)
2NP 2NP
(1 + α)L m Iin DTS Vin
φ2,Max = + (39)
2NP 2NP
TS Vin
φC,Max = . (40)
2NP
The cross-section area of the core is essentially defined by
the maximum flux density so that there is no core saturation
occurs when flux density reaches its peak value. According
to (24) and (32), it can be concluded that there is no need to Fig. 9. ZVS condition for the proposed converter as a function of input
current (Iin ) and parasitic capacitance (Cs) when n = 1.5 and Vout = 600 V.
adopt an air gap in the center leg as the dc-component of the
excited flux will cancel in the center leg, leading to lesser flux light load. Because of low parasitic capacitance, (42) implies
density; and consequently, lower core loss. From (34), with that the GaN switches can offer soft-switching performance
reduction of ac flux in the center leg, the proposed integrated with smaller leakage inductance, leading to higher efficiency.
coupled-inductors have a lower core loss in the center leg than From Fig. 9, it can be concluded that to extend the soft-
do conventional magnetizing. switching region, higher leakage inductance should be used.
Nevertheless, it has to be taken into account that increasing the
E. Soft-Switching Characteristics leakage inductance will decrease the voltage gain, as shown
in Fig. 6.
As described in Section III-B, the ZVS performance at turn-
on and turn-off is an inherent merit of the proposed converter, F. Voltage and Current Stress of Semiconductors
which is enabled by the energy stored in the magnetizing Due to the active clamp circuit, the voltage stress of
inductance. Regarding ZVS performance of the main switches switches is confined to the clamp capacitor voltage
at turn-on, as depicted in Fig. 5(c) and (g), the parasitic
Vout
capacitance of the switch must be completely discharged Vs1,max = Vs2,max = Vsc1,max = Vsc2,max = . (43)
before applying the gate pulse to the switch. In other words, 4n + 2
the following condition should be met: Equation (16) reveals that the voltage stress of switches is
much lower than the output voltage, decreasing with increase
1 1
L ki Iin2 ≥ CSi VSi2 for i=1,2. (41) in turns ratio. Thus, to limit the voltage stress of switches,
2 2 a proper n can be selected. As a result, a switch with a
It is assumed the converter works in ideal lossless condition small rated voltage, as well as a small ON-resistance can
for simplification purposes. Now, from (16), the ZVS condition be employed. The voltage stress of diodes can be achieved
can be determined by from (44)
CSi Vout2 Vout
L ki ≥ for i = 1, 2. (42) VDo1 = VDo2 = VDr1 = VDr2 = . (44)
(4n + 2) Iin2 2
The peak current of the main switches can be obtained as
Fig. 9 shows the leakage inductance L k versus input follows:
current Iin and the parasitic capacitance of switch Cs . It can be
seen that if the parasitic capacitance of switch decreases, lower IS1,peak = 0.5Iin,avg + 2n IDr1,peak + IDr1,peak (45)
leakage inductance is required to realize the soft-switching in IS2,peak = 0.5Iin,avg + 2n IDo1,peak + IDo1,peak . (46)

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MORADISIZKOOHI et al.: INTEGRATED INTERLEAVED ULTRAHIGH STEP-UP DC–DC CONVERTER 651

TABLE I
P ERFORMANCE C OMPARISON OF THE P ROPOSED C ONVERTER AND THE C ONVERTER C ITED IN [21], [24], [28], AND [29]

Fig. 10. Comparison of the voltage gain and voltage stress of active switches. (a) Proposed converter versus CIBC. (b) Proposed converter versus converter
in [21], [24], and [29]. (c) Proposed converter versus converter in [28]. (d) Voltage stress of active switches.

Under the steady-state condition, the average current of
diodes equals to the output current due to the capacitor current-
second balance
2Iout
IDr1,peak = IDr2,peak = IDo1,peak = IDo2,peak = . (47)
1− D
By substituting (47) into (45) and (46), the peak current of
main switches can be expressed as
IS1,peak = IS2,peak = 3(2n + 1)Iout/(1 − D).
The peak current of clamp switches can be derived from
ISc1,peak = ISc2,peak = 0.5Iin = (2n + 1)Iout/(1 − D).
G. Comparison of the Proposed Converter and
Other HSUCs
In order to investigate the features of the proposed converter
in comparison with some of the well-known nonisolated
interleaved high step-up converters, the key characteristics of
converters, including voltage gain, voltage stress of semicon-
ductors, and the number of passive and active components, are
summarized in Table I.
A comparison of the voltage gain of the proposed converter
with other HSUCs for different values of the duty-cycle is
shown in Fig. 10(a)–(c). It can be seen that the proposed con-
verter offers the desired voltage gain without working under
extreme duty-cycle values. Besides, as depicted in Fig. 10(d),
the proposed converter offers the lowest voltage stress across
the semiconductors, and therefore, switches with lower rated-
voltage and smaller on-resistance can be adopted, resulting in
(48) improved efficiency and cost. Also, as indicated in Table I,
the voltage stress of diodes for the proposed topology is half
of the output voltage, implying that the diodes with smaller
(49) voltage drop can be used bringing about lower conduction loss.
Due to the use of active-clamp circuit, the number of power
switches is the same in the proposed converter, converter [21],
and converter [29], and CIBC. Although the converter [24]
has the least number of active switches, it suffers from the
hard-switching performance that deteriorates the efficiency.
Moreover, the total number of semiconductors for the proposed
converter is the same as the converter introduced in [24].
It should be noted that the higher number of active switches
does not increase the complexity of the control circuit because
the similar asymmetrical pulse width modulation (PWM) is

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652 IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS, VOL. 8, NO. 1, MARCH 2020

TABLE II
C OMPARISON OF MAGNETIC COMPONENTS SIZE BETWEEN THE PROPOSED CONVERTER AND OTHER CONVERTERS
( Pout = 1000 W, Vin = 30 V, Vout = 600 V, f s = 100 K H Z , AND Iin = 10%)

used in the proposed converter. Due to using three-level
structure in the output stage, the voltage ripple of the output
capacitors in the proposed converter is lower than that of other
converters.
As the magnetic cores occupy the most volume of the
converter, reducing the number of cores, remarkably, shrinks
the size of the converter. According to [30], the stored energy
and total apparent power give a rough estimate for the size of
the inductor and transformer, respectively. A comparison of the
size of the magnetic components is carried out, which evalu-
ates the converters by comparing the total apparent power of
coupled inductors. The converters have been designed and sim-
ulated under same specifications, as follows: Pout = 1000 W,
Vin = 30 V, Vout = 600 V, f s = 100 kHz, and Iin = 10%.
Table II presents the stored energy and total apparent power
for most recent high step-up converters. The total apparent
power of coupled inductors is ample support for this claim
that the magnetic volume of the proposed converter is less than
that of the converter introduced in [21], [24], [28], and [29].
Compared to the converter introduced in [24], [28], and [29],
less magnetic cores are utilized in the proposed converter
due to applying the integrated magnetic technology, which
advances the power density.
Now, a comparison of the size of capacitors is performed
between the proposed converter and other recent high step-
up converters. The energy volume of capacitors can give
an insight into the size of capacitors [30]. So, the energy
volume of capacitors for different converters are calculated
and presented in Table III. It can be seen that the proposed
converter and converter [28] have the lowest total energy
volume of the capacitors, implying these converters have the
smallest capacitors.
should be higher than 0.5. From (15), along with ignoring
the leakage inductance, the turns-ratio can be calculated
from
1 Vout
n< − 0.5. (50)
8 Vin
2) Magnetizing Inductance: By limiting the input current
ripple, the magnetizing inductors operate similar to the boost
inductor in the conventional boost converter. So, the value of
the magnetizing inductors can be determined by
2Vin DTs D(1 − D)Vin Ts
L m1 = L m2 = = (51)
k Iin k(2n + 1)Iout
where k is the current ripple on the magnetizing inductor. For
ensuring that the input current ripple is 15%, the minimum
magnetizing inductance can be calculated by
5D(1 − D)Vin Ts
L m1 = L m2 > . (52)
3(2n + 1)Iout
3) Leakage Inductance: According to (10), the leakage
inductance plays an important role in the soft-switching per-
formance of semiconductors, as well as the voltage gain and
the falling rate of the output diodes current. For extending the
ZVS range of switches and restrain the slope of diodes
current in the proposed converter, higher leakage inductance
is required, whereas, the voltage gain decreases. Although
increasing the leakage inductance widens the ZVS region
and restrains the slope of diodes current, the voltage gain
decreases.

IV. D ESIGN C ONSIDERATIONS B. Capacitor Design

A. Coupled Inductors Design Based on the assumption made in Section III, the capac-
1) Turns-Ratio: As mentioned before, the converter is itors should be designed so large that they operate as
working in CCM, and the duty cycle of the main switches a voltage source during one switching period. So, the

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MORADISIZKOOHI et al.: INTEGRATED INTERLEAVED ULTRAHIGH STEP-UP DC–DC CONVERTER 653

TABLE III
C OMPARISON OF SIZE OF CAPACITORS BETWEEN THE PROPOSED CONVERTER AND OTHER CONVERTERS
( Pout = 1000 W, Vin = 30 V, Vout = 600 V, f s = 100 K H Z , AND V = 10%)

capacitors can be chosen as where IRMS,D and ID,avg are the rms and average current of
Iout Ts diodes, which can be derived from
Cm1 = Cm2 > (53)
Vm 2Iout
(1 − D)Vout Ts IRMS,D = √ (61)
Co1 > (54) 3(1 − D)
Rout Vout ID,avg = Iout . (62)
DVout Ts
Co2 > (55) The conduction loss due to equivalent series resistance
Rout Vout
(2n + 1)Iout Ts (ESR) of capacitors can be derived by
CC > . (56)
4Vout PC = RESR,C IRMS,C
2
(63)
V. E FFICIENCY A NALYSIS where IRMS,C is the rms current of capacitors and can be
There are totally five major losses in the dc-dc converter: derived by
switching loss, switches conduction loss, diodes conduction 
loss, capacitors conduction loss, and inductor conduction loss. 4 + 3D(1 − D)
IRMS,Co1 = IRMS,Co2 = Iout (64)
The switching loss can be ignored in the proposed converter 3(1 − D)
due to the ZVS performance of switches and zero current 
switching (ZCS) operation of diodes. The switches conduction 8
IRMS,Cm1 = IRMS,Cm2 = Iout (65)
loss can be calculated by 3(1 − D)

PS = RDS(ON) IRMS,S
2
(57) (2n + 1)Iout 2(1 − D)
IRMS,Cc = . (66)
where RDS(ON) is the ON-resistance of the switch. For simplify- (1 − D) 3
ing the current analysis, the leakage inductance is assumed to The conduction loss due to ESR of inductors can be derived
be zero. The rms current of switches, IRMS,S , can be obtained by
from
 PL = (RESR,p )IRMS,Lk
2
+ 2n(RESR,s )IRMS,D
2
(67)
(2n + 1)Iout 10 − 7D
IRMS,S1 = IRMS,S2 = (58)
(1 − D) 3 where RESR,p and RESR,s are the total ESR of primary and

(2n + 1)Iout (1 − D) secondary windings, respectively. RMS current of leakage
IRMS,Sc1 = IRMS,Sc2 = . (59) inductance can be calculated by
(1 − D) 3
The diode conduction loss can be determined by using the (2n + 1) Iout
IRMS,Lk =
diode equivalent model of the forward voltage drop VF in 1 − D
series with resistance RD , which can be calculated from 8n D 16n 2 (1−D 3 + (1−D)3 )
× 1+ + . (68)
PD = 2
RD IRMS,D + VF ID,avg (60) 2n + 1 3 (2n + 1)2 (1-D)

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654 IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS, VOL. 8, NO. 1, MARCH 2020
Fig. 11. Theoretical efficiency versus duty-cycle for different values of output
power. (RESR,P = RESR,S = 15 m, RESR,C = 22 m, RDS(ON ) = 5 m,
RD = 7 m, n = 1.2, VF = 1.25, and Vout = 600 V).
Fig. 12. Photograph of the laboratory prototype with a microcontroller.
The total loss in the coupled inductors can be calculated by
PL,tot = PL + PCore
where PCore can be obtained from the datasheet given by the
manufacturer. The efficiency of the proposed converter can be
obtained from
Pout
η= . (70)
Pout + PS + PD + PC + PL,tot
Fig. 11 shows the efficiency of the proposed converter ver-
sus duty cycle at different values of output power, where
RESR,P and RESR,S represent the parasitic resistance of primary
and secondary winding the coupled-inductors, respectively,
RDS(ON) represents the ON-resistance of the switches, RD rep-
resents the parasitic resistance of the diodes, RESR,C represents
the parasitic resistance of the capacitors, and VF is the forward
voltage drop of the diodes.
VI. E XPERIMENTAL R ESULTS
For validating the theoretical analysis, a 1-kW prototype of
the proposed topology operating at 100 kHz is implemented,
shown in Fig. 12. The parameters and components used
in the prototype are listed in Table IV. For implementing
the desired coupled inductors, an EE55 ferrite core is used.
A TMS320F28337S is employed to generate the signal pulses
for the control scheme. For handling high current, as well
as reduce the conduction losses, two switches EPC2034 are
connected in parallel.
The experimental results at the full-load condition for two
different values of input voltage 30 and 40 V are presented
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TABLE IV
PARAMETERS AND C OMPONENTS OF THE P ROTOTYPE
in Figs. 13 and 14, respectively. The gate–source pulse of
all switches are shown in Fig. 13(a). According to (15),
to achieve a voltage gain around 20, the control circuit should
generate pulses with a duty cycle of 0.66. As can be seen
from Fig. 13(a), the experimental results match the theoretical
analysis reasonably. Thereby, the operation with extreme val-
ues of duty-cycle to obtain a high-voltage gain is avoided in
the proposed topology. The voltage of output capacitors Co1
(69) and Co2 , the voltage across the clamp capacitor CC , and the
input voltage are displayed in Fig. 13(b). It can be seen that
the voltage ripple are so small, which confirms the correctness
of the design of capacitors. The automatic current sharing
performance is explained in Fig. 13(c), in which the current of
leakage inductors and input current are demonstrated. As can
be seen, the automatic equal current sharing can be obtained
without adopting any special control scheme. Also, it is clear
that the magnetizing inductance of the coupled inductors acts
like the input filter so as to reduce the input current ripple. The
voltage stress across switches S1 and SC1 are demonstrated
in Fig. 13(d). Due to use of active-clamp technology, the volt-
age stress of switches is limited to the voltage of capacitor CC ,
which is about 70 V. It can be concluded that the voltage stress
of switches are much less than the output voltage (600 V);
therefore, switches with smaller ON-resistance RDS(ON) can
be adopted that leads to higher efficiency. As discussed in
the previous section, the soft-switching of main switches S1
and S2 is more challenging than that of the clamp switches.
So, the soft-switching operation of the main switch S1 is
considered in this section. For investigating the soft-switching
performance of the switch S1 , the gate–source and drain–
source voltage are shown in Fig. 13(e). It is obvious that ZVS
at turn on for the main switch S1 is accomplished. The voltage
and current of diodes DO1 and DO2 are given in Fig. 13(f).
As can be seen from this figure, the diodes turn off under
ZCS condition due to controlling their current by the leakage
inductance, alleviating the reverse recovery issue.
MORADISIZKOOHI et al.: INTEGRATED INTERLEAVED ULTRAHIGH STEP-UP DC–DC CONVERTER 655

Fig. 13. Experimental results at full-load condition and input voltage 30 V. (a) Gate pulse of switches. (b) Voltage across different capacitors. (c) Current of
leakage inductors L k1 and L k2 . (d) Voltage stress across switches S1 and Sc1 . (e) Gate–source and drain–source voltage of switch S1 . (f) Voltage and current
of diodes Do1 and DO2 .

Fig. 14. Experimental results at full-load condition and input voltage 40 V. (a) Gate pulse of switches. (b) Voltage stress across switches S1 and Sc1 .
(c) Gate–source and drain–source voltage of switch SC1 . (d) Gate–source and drain–source voltage of switch S2 . (e) Gate voltage of switch S1 , current of
diode DO1 , and input current. (f) Voltage and current of diodes Do1 and DO2 .

The experimental results of the proposed converter at input
voltage 40 V are shown in Fig. 14. The gate pulses of switches
are shown in Fig. 14(a). It can be seen that for achieving a volt-
age gain of 15, the duty cycle is about 0.55, which is in accor-
dance with (15) fairly. The input voltage and voltage stress
across switches S1 and SC1 are demonstrated in Fig. 14(b).
It can be observed that the voltage stress of switches (90 V)
are much less than the output voltage (600 V); thus,
the proposed circuit enables using switches with smaller
ON -resistance RDS( ON) that results in lower conduction losses.
Fig. 14(c) and (d) shows the gate–source and drain–source
voltage of switch S1 and S2 , respectively, where the ZVS at
turn-on instant is demonstrated. The input current, the gate
voltage of switch S1 , and the current of output diode Do1 are
presented in Fig. 14(e), following the theoretical analysis. The
waveform of voltage and current of diodes DO1 and DO2
are presented in Fig. 14(f), in which the current of diodes
are controlled by the leakage inductance of the coupled-
inductors. Therefore, ZCS at turn-off instant is fulfilled that
helps alleviate the reverse recovery issue.

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656 IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS, VOL. 8, NO. 1, MARCH 2020
Fig. 15. Efficiency variation under different voltage level and comparison of efficiency. (a) Measured and theoretical efficiency of the proposed converter.
(b) Efficiency comparison (Vout = 600 V, Vin = 30 V, f s = 100 kHz, Pout = 1 kW).
Fig. 16. Loss breakdown at full-load condition for different input voltage.
(a) Vin = 30 V. (b) Vin = 40 V.
The theoretical and measured efficiency of the proposed
converter for different output power and input voltage values
are shown in Fig. 15(a). The theoretical and measured effi-
ciency of the converter at the nominal output power (1000 W)
and input voltage 40 V are 97.1 % and 97.0 %, respectively.
From Fig. 15, it is clear that the maximum efficiency occurs at
the output power 600 W, where theoretical and measured effi-
ciency values are 97.7 % and 97.5 %, respectively. Fig. 15(b)
compares the efficiency curves of the proposed converter and
other converters versus output power. In this comparison, it
has been assumed that all the converters are working under the
same operating conditions (given in Table IV). Also, the same
switches and diodes are being used in all the converters. It can
be seen that the efficiency of the proposed converter is higher
than the other converters due to the reduced voltage stress of
the semiconductors.
The loss breakdown at the full-load condition for different
input voltage Vin = 30 V and Vin = 40 V are presented
in Fig. 16(a) and (b), respectively. It can be seen that the
coupled-inductor losses, especially conduction losses, is the
dominant power losses in the proposed circuit. To further
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improve the efficiency of the proposed system, the better-
graded wires for coupled-inductors can be adopted.
VII. C ONCLUSION
In this article, a soft-switched dc–dc interleaved converter
with a high-voltage gain was proposed that integrates two
coupled inductors and switched-capacitor circuit so as to
improve the power density, which is suitable for applica-
tions demanding high-voltage conversion ratio, such as for
FC-based HEV systems. For absorbing the voltage spike
across the switches and recycle the leakage energy to the
load, a promising integrated regenerative snubber circuit is
adopted. Compared to the other HSUC, the salient advan-
tages of proposed topology are high-voltage gain, small input
current ripple, low-voltage stress across the semiconductors,
and built-in automatic current sharing. ZVS performance of
switches, along with ZCS operation of diodes, paves the
way for improving the efficiency of the proposed converter.
As the asymmetrical pulse-width modulation is used as a
control technique, there is no complexity added to the control
technique. As the diode’s current is controlled by the leakage
inductance, the reverse recovery problem is alleviated, and the
EMI noise is restrained as well. The experimental results of
a 1-kW prototype of the converter were presented to validate
the proposed topology, which demonstrates the converter suits
well for applications demanding with high-voltage gain.
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Hadi Moradisizkoohi (S’16) received the B.S.
degree from the University of Guilan, Guilan, Iran,
in 2010, and the M.S. degree from the Amirkabir
University of Technology, Tehran, Iran in 2013.
He is currently pursuing the Ph.D. degree with the
Department of Electrical and Computer Engineering,
Florida International University, Miami, FL, USA.
He is currently a Graduate Assistant with the
Department of Electrical and Computer Engineering,
Florida International University. His current research
interests include power converters for renewable
energy applications, electric vehicle powertrain system, and high-efficiency
converters using wide bandgap semiconductors.
Nour Elsayad (S’15) received the B.Sc. and M.Sc.
degrees in electrical engineering from Ain Shams
University, Cairo, Egypt, in 2010 and 2014, respec-
tively. He is currently pursuing the Ph.D. degree with
the Department of Electrical and Computer Engi-
neering, Florida International University, Miami,
FL, USA.
He is currently a Graduate Assistant with the
Department of Electrical and Computer Engineer-
ing, Florida International University. His current
research interests include high-frequency link con-
verters, bidirectional dc–dc converters, wide-input dc–dc converters, multilevel
power electronic architectures, and high-frequency power converters design
using wide bandgap devices.
Osama A. Mohammed (S’79–M’83–SM’85–F’94)
received the M.S. and Ph.D. degrees in electrical
engineering from Virginia Tech, Blacksburg, VA,
USA, in 1981 and 1983, respectively.
He is currently a Distinguished Professor and
the Associate Dean of Research with the College
of Engineering and Computing, Florida Interna-
tional University (FIU), Miami, FL, USA. He is
also the Director of the Energy Systems Research
Laboratory, Electrical and Computer Engineering
Department, FIU. He is a world-renowned leader in
electrical energy systems. He has current active research projects for several
federal agencies dealing with power system analysis and operation, smart grid
distributed control and interoperability, cyber physical systems, and co-design
of cyber and physical components for future energy systems applications.
He has authored more than 750 articles in refereed journals and other IEEE
refereed international conference records. He has also authored a book and
several book chapters. His research interests include various topics in power
and energy systems in addition to design optimization and physics based
modeling in electric drive systems and other low-frequency environments,
electromagnetic signature, wide band gap devices and switching, and ship
power systems modeling and analysis.
Dr. Mohammed is a fellow of the Applied Computational Electromagnetic
Society. He was a recipient of the prestigious IEEE Power and Energy Society
Cyril Veinott Electromechanical Energy Conversion Award. He was also a
recipient of the 2012 Outstanding Research Award and the 2017 Outstanding
Doctoral Mentorship Award from Florida International University. He was
designated Distinguished University Professor in 2018.