Circuit analysis of active mode parasitic oscillations

in IGBT modules
P.R. Palmer and J.C. Joyce

Abstract: The susceptibility of multi-chip IGBTs to differential oscillations between chips has been
noted experimentally. The authors present a theoretical analysis of such oscillations during the
transient active operation at turn off and turn on. They take into account the stored charge within
the IGBT, the nonlinear transconductance and capacitances and the basic stray inductance
elements found within an IGBT module or capsule. Two small-signal analyses are given. The first
of these is based on the characteristic equation and exploits symmetry withn the module, if
appropriate. The second extends the analysis to asymmetrical designs. It is concluded that the
methods are complementary and aid understanding of the operation of such devices. Both will also
be of use in the design of future devices, especially in malung the choice of the gate resistance.

1 Introduction 2 Analysis of IGBT chips connected in parallel

The IGBT has become the power semiconductor device of
choice in modern medium-power converter circuits. It
shares a number of features with the MOSFET, particularly
a high input impedance and controllable switching proper-
ties. High voltage, high current IGBT modules are
constructed from a number of parallel connected IGBT
chips mounted in an array within the case.
The stability of the parallel operation of MOSFETs was
analysed by Kassakian and Lau [l]. They showed that
differential oscillations between the chips may occur and
that gate sharing resistors were essential to suppress such
behaviour. Since the terminal characteristics of the IGBT
are broadly similar to those of the MOSFET, gate sharing
resistors are adopted in IGBT modules, where clups are
connected in parallel [2].
The susceptibility of paralleled IGBTs to such oscillations
has been noted experimentally [3] (see [4] for the IEGT.)
However, the theoretical analysis for the IGBT is more
involved than that for the MOSFET due to the presence of
stored charge within the IGBT and the typical size and
scaling of the chips employed in IGBT modules. The use of
individual gate resistors for each chip degrades the current
sharing between the chips during the turn off transients [SI.
Therefore it is essential to reduce the resistor values to those
whch are sufficient rather than employing excessive
stabilisation at the cost of the current sharing properties
and switching speed. Identifying other features of the
module design which influence the stability is also necessary.
In this paper, we present a detailed analysis of the
stability of the IGBT module, noting regions of interest in
the active operation of the IGBT.
0IEE, 2003
IEE Proceedings online no. 20030336
doi: 10.1049/ip-~ds:20030336
Paper first received 15th February and in revised form 17th July 2002
The authors are with the Department of Engineering, University of Cambridge,
Trumpington Street, Cambridge CB2 IPZ. UK
IEE Proc.-Cirarirs Devices Sjsr., Vol. 150. No. 2, April 2003
The analysis of Kassakian and Lau [I] is extended to take
into account the strongly nonlinear behaviour of the IGBT
and its stored charge. The analysis is also enhanced by the
use of Bode and Nyquist plots of the behaviour.
2. I The small-signal IGBT model
The ‘active’ (saturated) region of operation of an IGBT can
be successfully modelled for our purpose by adapting the
basic small-signal MOSFET model: within the chip, an
additional parallel output capacitance CO is required, as
shown in Fig. 1. CO accounts for the charge stored in the
wide n base region of the elementary pnp transistor [&9].
Clearly its value varies from zero at zero collector current to
a very large value at hgh currents.
C
‘GC Q
E
Fig. 1 Small-signal equivalent circuit of u single IGBT
As CO appears in parallel with CCE, for convenience it is
incorporated into a current-dependent CcEin the remainder
of this paper. A further difference between the case of the
IGBT chips in modules and MOSFETs is the presence of
the auxiliary ‘Kelvin’ emitter contact in IGBT modules, for
the gate circuit return [5].However each chip on1 has one
Y
Kelvin contact, and IGBT chips are around 1 cm , so some
emitter impedance will inevitably appear.
2.2 Circuit analysis
Following the approach of Kassakain and Lau [l], for a
symmetrically arranged pair of chips, with differential
we can the circuit the
stray inductances, see the Appendix. Hence we find the
85
 minimum RG required for stability for a given set of device
and parasitic impedance parameters. This is straightforward
to acheve with a mathematical package such as MATH-
CAD [lo].
Then we investigate how this minimum value of &.
changes as the parameters change. Some of the IGBT’s
electrical characteristics, particularly CG, and CCE, are
heavily dependent on the collector voltage; meanwhile, g,
and ‘CCE’are dependent on collector current. So it is
necessary to find the minimum value of & over the whole
range of conditions to assure stability of a given design. The
impact of design changes can also be investigated.
The analysis in the Appendix does not, however, reveal
the nature of a stable system. To deduce how the module or
chip design may be improved, it is necessary to investigate
the IGBT circuit model further. PSPICE [ll] provides a
convenient method for doing this, avoiding the complexity
of analysing the circuit to find its characteristic equation.
The susceptibility to oscillation of the system is revealed
by opening the equivalent circuit of the IGBT and stray
inductances at the ideal gate as shown in Fig. 2. Sweeping
the frequency response of the circuit, with a fixed set of c h p
and module parasitic elements, whilst varying & will
produce a family of Bode response curves (loop gain and
phase against frequency). From these, or from the respective
Nyquist plots, it is possible to estimate the minimum RG
required for stability. Clearly, analysing the circuit of Fig. 2
in PSPICE gives the same minimum value of RG as
calculated with MATHCAD, for the same parameter
values in the circuits. However, the gain and phase margins
of the circuit can be determined if RG is such that the circuit
is stable and the expected frequency of oscillation can be
estimated if it is not stable. Thus, (for example) parallel
devices can be examined with a degree of asymmetry in
their connections.
1 G (transconductance)
,O*,,+J (-1
+ I
collector
L,
20 n H
I
(RGATE)
Fig. 2 Single IGBT equivalent circuit, us used in the Mathcud
analysis, but split for analysis of the loop transfer -function in
PSPICE
3 Determining model parameters
3.1 Module parasitic impedances
A set of parameters was estimated for two lSOOV, 75A
chips operating in a half-bridge module. Resistance Rc,of
the order of 2mQ was measured by probing an open
86
module passing a known DC current. RE,was estimated to
be 0.2mQ.
The inductance Lc, representing the differential collector
inductance and the differential emitter impedance not
coupled into the gate loop, was found from the experi-
mental switching transients using V= Ldlldt, making LC
approxiniately 20nH. LG was estimated at lOnH from
consideration of the length of the wires and the inductance
of the emitter Kelvin connection not included within the
high current circuit. LE was estimated to be 2nH from
consideration of the bond wire layout.
3.2 Device parameters
The parameters gm and Ro are easily found from data sheet
or curve tracer measurements. For the 1800V chip used, g,
is approximately 80 S at rated current (75 A), falling to I O S
at 10A. Ro can be determined from the slope of the IC
against VCE graph at a particular gate voltage. At rated
current and moderate collector voltages, Ro is estimated to
be approximately 100Q a low value due to the integral
bipolar action. Ro takes on a significantly higher value
below a VCE of approximately 1OOV.
The terminal capacitances of a module are usually given
on manufacturers’ data sheets as functions of collector-
emitter voltage, and the chip capacitances, Fig. 1, can be
deduced from them. However, these are quoted at zero gate
voltage (zero collector current), for a single test frequency
(usually I MHz). The data supplied are not sufficient for the
purpose here: at turn-off, the capacitances CcEand CGCare
much larger due to the charge stored in the wide drift region
of the device during the conduction period.
The device simulator ATLAS [12] may be used to
determint: the device capacitances [8]. Here we perform a
full transient simulation. Two D C voltage sources (gate and
collector) bias the device to the operating point of interest,
and then a small AC source is applied in series with the gate
or collector. By examining the resulting current in the AC
source, the capacitance at that terminal can be deduced.
The collector test circuit is shown in Fig. 3. This
approach yields Cos, under high current conditions as
desired, although some care is needed with this test to avoid
the effects of &. Consideration of IG and ZE separately
enables CGc and C,, to be distinguished. Testing at the
gate yields CIS,. The third device capacitance CGEcan then
be deduced from these measurements. As expected from
manufacturers’ data sheets, at zero gate voltage (IC = 0),
CGE is practically constant over the range of collector
voltages, Fig. 4a; CCEand C, are of similar magnitude to
each other and heavily voltage-dependent due to the
extension of the depletion layer as VCE increases. The value
of the ratio CGC:CCE is approximately constant at around
0.75.
A different picture emerges at around the rated current of
the chip (75 A), Fig. 46. All three capacitances are voltage-
dependent, and much larger. CGC is seen to have risen to
Fig. 3 IGBT test circuit with bias and AC sources
IEE Proc.-Circuits Device.7 Syst.. Vol. 150, No. 2,April 2003
 the centre of a single wafer. Differential oscillations are
observed when operated with typical gate resistor values [3],
Fig. 5, where the currents were measured noninvasively [13].

4.2 Baseline results from the analyses

Our first objective is to map RGmn as a function of many

-
other variables, but mapping the whole spread of possible
circumstances is clearly impractical. Here, we choose the
known point of interest, taken from the experiment above,
%
-: and investigate the behaviour around that point.
10’0 CGC
Values used for an initial calculation were & = 2 mR;
~~

RE= 0.2ma; gm= 80 s; Lc = 20 nH; LE= 2 nH;

10-11 L G = 20 nH; C,, = 95 pF; CcE= 7.8 nF; CGE= 5.5 nF;
10 102 I o3 Ro = 100 0. The capacitances were chosen at VcE = 200 V,
voltage, V I, = 75 A as in range with those measured above during the
a switching transistion and potentially unstable, Fig. 5.
Inserting these values into the characteristic equation (see
1 (5) in the Appendix) and evaluating the Routh Hunvitz
criterion for stability using MATHCAD gives a baseline
value for RG of 2.2 R, which is consistent with the 5 !2 to 7 R
used in practice.
T h s baseline result is reproduced in PSPICE as shown in
Fig. 6, where a detailed portion of the Nyquist plot presents
the magnitude and phase response for a small range in &.
The response passes through the unity magnitude zero
phase condition, with a gate resistor of 2 . 2 Q as expected.
The Nyquist stability criterion refers to ‘encirclements’ of
the unity magnitude zero phase point. Thus, with 2.6 R and
10-l1 J I 2.4 0 the system is stable, although more than unity gain at
10 102 1o3 zero phase is indicated.
voitage, V
b
The Bode plots for this baseline condition are shown in
Fig. 7, where RG again is varied. Oscillation is shown to be
Fig. 4 Device capacitances as a function of collector voltage expected between 12MHz and 33MHz, for values of
(ATLAS simulation) RG <2.18 SZ (approximately 16 MHz is observed in Fig. 5).
a off (vG=ov), The frequency response is dominated by three distinct
b High current ( VG= 7 V) resonances: two pole pairs and a zero pair. At 12 MHz, CCE
resonates with Lc and LE and is not damped by &. At
15MHz, CGE resonates with LE and LG and &
over 10nF. CGEhas risen to approximately 75nF at low significantly damps this resonance. The resonant zero near
collector voltage, and CCEis now large at 220nF. It is also 33MHz involves CGc, Lc, LG and LE, damped by &.
notable that the ratio CGC:Cc, is now approximately 0.015 Varying the capacitances appropriately with the collector
for VCE> 10OV. This has important implications for the voltage, as occurs during a turn off switching transition,
stability analysis. allows the curve of Fig. 8 to be produced.

4 Results 4.3 Variations in device parameters

The stability analysis given in the Appendix, can now be
4.1 Experimental used to consider the effects of variations in the parameters
Tests were conducted using a 150A module constructed of the IGBT chips themselves, for the baseline set of module
with a pair of matched 75 A, 1800 V IGBT chps taken from package stray elements. Fig. 9 is an example result.

. . , . . . . .

160 660 1160

time, ns

Fig. 5 D@rential collector current oscillations seen experimentully, during turn oj’at a nominal module current of 40 A and reduced voltage
Standard 150A, 1600V module

IEE Proc.-Circuits Devices Syyt., Vol. 150, No. 2, April 2003 87

 5

3
C:
@
2

0
0 200 400 600
CGC,PF
Fig. 6 Nyquist diugram showing the +I Nyquist point for the
baseline conditions Fig. 9 Minitnuin value of RG requiredfor dlfferent values of CcE
RG varied over a small range (PSPICE) with varying C,,

EO 4.4 Variations in stray impedance

Again, using the same characteristic equation above, with
the baseline IGBT parameters, the effects of the niodule
$ 40 package stray elements can be investigated, Figs. 10 and 1 1.
a- In considering Fig. 10, we can see that LE is undesirable
U
._ here, even at very low values. In Fig. 11, the effect of Lc is
C
0

E o quite clear, with a large Lc allowing the stability to be

ensured using a small gate resistor. The bond wire contact
resistance., represented by RE, has a negligible effect.
-40
0

-180
a
2
c
Q

-360 *
m

$ 4

-540 2
1 10 100
frequency, MHz

Fig. 7 Bode plot for the baseline conditions for values of RG of 0

0.1, 0.8, 2.18, 6.452 (PSPICE) 0 5 10 15 20
LG, nH

4 Fig. 10 Minimum value of RG required for dfferent values of LE

with varying LG

c:2
2
lo i I
i
I

0
10 100 1000
",e, "
Fig. 8 Minimum RGvarying with voltage at 75 A collector current I

Naturally Ccc falls as the voltage increases, although CcE

would also be changing with voltage. However, in Fig. 9, it
is noticeable that a high value of C,, practically eliminates
the need for gate resistors.
88
4.5 Asymmetric modules
Symmetry may be sacrificed in an IGBT module for the
sake of a more compact internal layout. Once symmetry is
lost, the analytical approach becomes unattractive, since the
half-circuit method cannot be applied and the complexity of
the equations increases. However, the PSPICE circuit
analysis method presented will be of use, although
interpretation of the resulting bode and Nyquist diagrams
requires care. Fig. 12 shows a sample asymmetrical pair of
chps, where the coupled-in emitter inductance is different
for each chip.
20 nH
Lc2
collectoR
i
1 1
Re2 0.2 m n
Rg, "'
(RGATE)
5 nH kH
Fig. 12 Asymmetrical pair modelled in PSPICE (emitter induc-
tances of 2nH and 5nH)
With two IGBT chips in circuit, there is no longer a
simple single oscillator. The Bode plot of the response for
the loop indicated is given in Fig. 13. The system is
marginally stable when & = 3.52 R (from the Nyquist
stability criterion). The same result is obtained if the side
with the other IGBT is investigated.
1 10
frequency, MHz
Fig. 13 Bode plots for the asymmetrical circuit shown in Fig. 12
jor values of Rc;of 0.1, 0.8, 1.6, 3.51, 6.452 (PSPICE)
IEE Psoc.-Circuits Devices Syst.. Vol. 150, No. 2, April 2003
5 Discussion
The investigation of the open loop transfer function of the
small signal equivalent circuit for the IGBT, using Bode and
Nyquist diagrams, directly yields the minimum RG for
stability, in agreement with the approach in the Appendix.
The methods presented here show that it is practical to
investigate the issues involved in parallel operation of
IGBTs in a module without disregarding particular stray
elements. The main advantage of mathematical packages
rests in the convenience of plotting a range of design curves.
The PSPICE AC analysis of the full asymmetrical
module is simple to perform although the results require
careful consideration. As modelled in Fig. 12, the differ-
ential assumption is almost entirely lost, except that the
impedances of the load are removed [l]. This is a safe
approximation, as the impedance of the load is likely to be
very high at the frequencies of interest.
Simulating the symmetrical case with the full circuit
confirms that a value of RG of 2.18 R is marginal for the
benchmark conditions. However, for lower values of RG,
the Nyquist and Bode plots produced imply that there is
insufficient phase shift for instability to occur. This
anomalous situation can be seen in Fig. 13 for the
asymmetrical case presented, where a value of 1.6R allows
oscillation, but 0.8R appears not to. As the second IGBT
(RGATE) chip is in the feedback circuit for the IGBT being studied, it
does not necessarily settle into differential oscillations in the
R92 AC frequency sweep simulation. In reality it will oscillate
(confirmed by transient analysis). Thus values of RG lower
than that for marginal stability are not reliable. The value
for marginal stability, obtained for Fig. 13, from the
PSPICE Nyquist plot is 3.52 R. The same value is obtained
if the loop around the second IGBT is investigated rather
than that around the first.
Used in combination, the analyses demonstrated above
allow a thorough review of a number of interesting issues
within high current IGBT module design. Two approaches
may be taken to stabilising the differential oscillations: One
is to damp them by increasing RG; the alternative is to
redesign the module and the chips. The former is not
attractive, as a high value of RG will slow the switching and
increase the switching losses. It also decouples the chip
gates, possibly compromising the performance of advanced
gate drives [14, 151. The latter approach may be assisted by
the use of numerical modelling packages, which can solve
for various inductance effects, such as skin effect and
mutual couplings (features which may be added easily to the
analysis presented). Gutsmann et al. [I61 and Consoli et al.
[I71 obtained the parasitic values for a module, but did not
perform any stability analysis.
It is clear from the frequency response plots that
relocating the second pole pair after the zero pair would
create an unconditionally stable module. This can be
achieved by adding additional inductance to each gate lead,
as suggested earlier [I, 181. Other steps could also be
suggested [19, 201 and analysed thoroughly using the
methods presented here. Collector inductance (which
includes emitter inductance outside of the gate loop) also
appears to be beneficial for stability. However, increased
inductance in the module is usually unattractive, as it leads
to a higher overshoot voltage at turn off, and increased
switchng losses.
While the results described here are typical of plastic
100 module IGBTs, capsule IGBTs are becoming available for
high power applications [20]. The experiences of the device
manufacturers indicate that these require low values of RG.
They also observe oscillations during the tail time [20]; these
89
are not covered by this analysis, as they do not appear to
involve the active behaviour of the IGBT [21].
6 Conclusions
The existing Routh-Hurwitz method used to analyse the
half circuit for the case of MOSFETs in parallel is equally
applicable to the IGBT. However, careful consideration of
the effects of the capacitances is required, especially those
relating to the stored charge in the drift region. The stray
inductance elements are also very important in the case of
paralleled IGBT chips, thus simplification of the circuit is
not advisable. Stability cannot be ensured until all states of
the IGBT parameters are considered. However, the use of a
modem mathematical software package allows the various
circuit conditions to be swept, and the trends may be
conveniently plotted.
The stability analysis may be conducted using PSPICE or
similar software, although finding the marginal conditions
requires a manual algorithm and Nyquist plots are
indispensable. Bode plots of the frequency response for
the open loop system reveal the circuit interactions in the
form of poles and zeros, which are of interest when
considering the topographical design of a module. The
PSPICE approach, using Nyquist and Bode plots, is also
applicable to modules with no symmetry. Using the
analyses presented, module IGBTs may be designed, which
use the smallest possible gate resistor, allowing fast, low loss
switching.
7 Acknowledgments
The Authors would like to thank Dynex Semiconductors
Ltd, Lincoln for the specially prepared open modules and
the EC Framework 1V for funding (RAPSDRA project).
References
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gate bipolar transistor’, Solid-State Electron., 1988, 31, (IO), pp. 1513
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7 HEFNER, A.R.: ‘An improved understanding of the transient
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13 PALM-ER, P.R., STARK, B.H., and JOYCE, J.C.: ‘Noninvasive
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16 GUTSMANN, B., MOURICK, P., and SILBER, D.: ‘Exact
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9 Appendix
We consider the symmetrical case. Thus, we can draw the
model shown in Fig. 14 for a pair of IGBTs in parallel,
switching a load. This is a more general case than the two
situations considered previously by Kassakian and Lau [ 11.
The concern here is with differential current oscillations,
so VG, RL and Vcc in the system of Fig. 14 can be
dispensed with, as they will play no part in any differential
oscillations; their terminals can be considered as small-
signal ground. This leaves a circuit which can be split into
its two halves and one half considered on its own, Fig. 15. If
one of these half circuits is oscillatory, the other will be too,
with the two oscillations being in antiphase. The resulting
circuit analysis is straightforward.
IEE Proc.-Circuits Devices Syst.. Vol. 150, No. 2, April 2003
 Fig. 15 Differential mode circuit o f a single IGBTfbr unalysis

The characteristic equation of the system of Fig. 15 can

be derived and analysed for stability. For convenience, a
+s(RGCISS+ RECE+ RCCOSS + gmLE + (Lc + L E ) / R o
number of constants are defined at thls point: + (RE/R~)(CGCRC+ CGCRG+ CGERG)
CISS= CGC CGE + (1) + (Rc/Ro)(CGCRG+ CGERG+ CGERE)
+ (gmCGC)(RGRE+ RGRC+ R C R E ) )
+ (BmRE + (Rc + RE)/& f 1) = 0 (5)
The chal.acteristic equation is thus a 4th-order polynomial
+
Ct = CGCCGE CCCCCE CGECCE + (4) of the form
The characteristic equation is then: a4s4 + a3s3 + a2s2 + a l s + uo = o (6)
s4Ct(LGk + LGLE + & L E ) The Routh-Hurwitz criterion can then be used to analyse
this polynomial for stability, the criteria being
ala2a3 >aou3a2 - ala2u4 (7)
a,>O (8)
By finding the largest value of RG whch produces equality
in (7), we find the minimum RG required for stability for a
given set of device and parasitic impedance parameters. The
criteria in (8) must also be checked.

IEE Prm-Circuits Devicm Syst., Vol. 150, No. 2, April 2003

91