MCMP Lab Record 1919106016

SONA COLLEGE OF TECHNOLOGY
Junction Main Road, Sona Nagar,

Suramangalam (P.O), Salem -636005.
Name. : Balaji G
Branch : IT
Semester :4
Register No.: 1919106016
Certified that this is the Bona-fide Record of the work done by the
above Student in U19IT406 – MICROPROCESSORS LAB during the
year 2020-2021.
Lab-in-charge Head of the Department

Submitted for the University Practical Examination held on .
Internal Examiner. External Examiner.

CONTENTS
S. Date Name of the Experiment Page Marks Signature
No No awarded of the Staff
1. 29.01.21 Study of 8085 Transfer 1 20

2. 05.02.21 8-bit Manipulations 3 20
4. 12.02.21 Code conversion 23 20
19.02.21 Decimal Arithmetic and Bit 32 20
5.
Manipulation
6. 26.02.21 Study of 8086 Trainer 38 20
7. 26.02.21 Addition and Subtraction 40 20
8. 26.02.21 Multiplication and Division 49 20
9. 05.03.21 String Manipulation 53 20
10. 12.03.21 Keyboard control and Display control 55 20
11. 12.03.21 File Manipulation 57 20
12. 8255 Interface
19.03.21 Experiments with mode 0 using 8085 59 20
Experiments with mode 0 using 8086 64
13. 8279 Interface
26.03.21 Keyboard/ Display Interface with 8085 67 20
Keyboard/ Display Interface with 8086 77
14. 8253 Interface
16.04.21 Timer Interface with 8085 81 20
Timer Interface with 8086 83
8251 Interface
Programmable Communication 85
15. 23.04.21 Interface with 8085
20
Programmable Communication 88
Interface with 8086
16. 30.04.21 Study of 8051 Microcontroller 92 20
19. 07.05.21 Array Operations-Sum of N Elements 98 20
STUDY OF 8085 TRAINER
AIM:
To study the component layout and functional block diagram of 8085-EB trainer.
Microprocessor Lab
DESCRIPTION:
The functional block diagram provides the complete system design in blocks. The
component layout is also provided for the reference. Referring to the figure F1.1 the
following explanation outlines the working of the trainer as a system.
i) Inputs to and outputs from the CPU
The CPU gets the clock from the clock generator which is a crystal at 6.144 MHz. The
reset*, interrupt lines, and data lines are also inputs to the CPU. The CPU outputs comprise
the clock, reset, address lines, data lines and control lines.
ii) Address and Data bus:
The lower order address lines are latched using ALE and thus demultiplexed from the
data lines. The higher order address lines are taken directly from the 8085. These two sets of
lines make the 16 bit address bus. The 8 data lines are taken directly from the 8085.
iii) Control bus:
The other bus is the control bus. The control signals required for proer operation of the
system are the IOR* (I/O read), IOW*(I/O write), MR*(Memory Read) and MW*(Memory
Write). The peripherals on the trainer are all I/O mapped and hence to input from or output to
a peripheral IOR* and IOW* are utilized. The memory read and memory write signals are
used to enable an EPROM & RAM and write into a RAM respectively. These signals are
generated from the IO/M* and WR*, RD* signals.
iv) Chip select logic:
The selection of any peripheral or memory requires a CS* to enable that particular
device. This requires address decoding, both memory and I/O. All the above signals address,
data, control and chip select are routed to all the peripherals and memory devise in thee
trainer.
v) Keypad and display:
The block diagram shows a 21 keys keyboard and an eight digit display. This is the unit
with which the user communicates with the system. The keypad and display are interfaced
with the CPU with the help of an 8279, I/O mapped with the CPU. The display is driven by
display drivers driven by the KDC (8279). The keyboard lines are encoded and sent to the
KDC.
Name:Balaji G Reg.No:1919106016 Section:IT-A

Microprocessor Lab
vi) Memory:
The block diagram shows an 8 KB EPROM or 32 KB EPROM and an 8 KB RAM or 32

KB RAM.
vii) Peripherals:
The 8253 TIMER for baud clock generation and single step operation; the 8251 USART
for serial communication with associated drivers for interference immunity and overcoming
attenuation; the 8255 PPI for TTL I/O drivers; the audio cassette interface are also depicted
in the block diagram.
System expansion is facilitated by virtue of the expansion slots provided on board.
CONCLUSION:
Thus the component layout and functional block diagram of 8085-EB trainer
is studied.
Name:DILOSHAA SRI.R Reg.No:1919106024 Section:IT-A

Microprocessor Lab
8-BIT MANIPULATION
AIM
To write an assembly language program to perform
1. Addition on two 8 bit numbers 2.
Subtraction on two 8-bit numbers.
3. Multiplication on two 8-bit numbers
4. Division on two 8-bit numbers
APPARATUS REQUIRED:
Sl.No Apparatus Specification Quantity

1 Microprocessor Kit 85 EB2 Kit 1
2 Power Supply I/P 230 V, 50 Hz, O/P 5V 1
3 Opcode Sheet 8085 Opcode 1

Microprocessor Lab
FLOW CHART Addition of two 8-bit numbers:

Microprocessor Lab
START
Load addend and augend in two consecutive locations
Move addend to accumulator and augend to some register
Add accumulator and the register contents
No
Is carry
flag
set?
YES
CARRY =CARRY+1
Store the sum and the carry in the respective locations
STOP
PROGRAM:
Addition of two 8 bit numbers:
Memory Machine – Code Mnemonics

Label
Opcode Operand Opcode Operand
Comment
Address
4100 AF XRA A ;Clear Accumulator
;Clear the C register for
4101 4F MOV C,A
carry

Microprocessor Lab
4102 3A LDA 4200 H ;load accumulator with
4103 00 data from the address
4104 42 4200
4105 47 MOV B,A ; Load to the B register
4106 3A LDA 4201 H ; Load accumulator
4107 01 with data from the
4108 42 address 4201 H.
; Perform the addition
4109 80 ADD B
of two 8 bit numbers
410A D2 JNC 410E H
;If no carry then skip
410B 0E
carry
410C 41
; Increment the carry
410D 0C INR C
register
410E 32 STA 4202 H
; Store the sum in 4202
410F 02
H
4110 42
; Move carry to
4111 79 MOV A,C
accumulator
4112 32 STA 4203 H
4113 03 ; Store carry in 4203.
4114 42
4115 76 HLT
OBSERVATION:
SNo Addend at location Augend at Sum at location Carry in location

4200 H location 4201 H 4202 H 4203 H
1. 05 05 0A 00
2. AB CD 78 01
FLOW CHART Subtraction of two 8-bit numbers:

Microprocessor Lab
START
Load minuend and subtrahendconsecutive

in two
locations
Move minuend to accumulator and subtrahend to some

register
Subtract accumulator and the register contents
No
Is carry
flag
set?
YES
Increment the borrow register
Store the difference and the borrow in the respective locations
STOP
PROGRAM
Subtraction of two 8-bit numbers:

Label Comment
Address Opcode Operand Opcode Operand
4400 Start AF XRA A ;Clear Accumulator
4401 4F MOV C,A ;Clear the C register for

Microprocessor Lab
carry
4402 3A LDA 4500 H
;load accumulator with data
4403 00
from the address 4500H
4404 45
4405 47 MOV B,A ; Load to the B register
4406 3A LDA 4501 H ; Load accumulator with
4407 01 data from the address 4501
4408 45 H.
; Perform the addition of two
4409 SUB B
8 bit numbers
440A D2 JNC 440E H
440B 0E ;If no carry then skip carry
440C 44
; Increment the borrow
440D 0C INR C
register
440E 32 STA 4502 H
;Store the difference in 4502
440F 02
H
4410 45
4411 79 MOV A,C ; Move carry to accumulator
4412 32 STA 4503 H
4413 03 ; Store carry in 4503H.
4414 45
4415 End 76 HLT
OBSERVATION
S No Subtract at location Subtrahend at Difference at Borrow in location

4500 H location 4501 H location 4502 H 4503 H
1. 05 0A 05 00
2. 58 AB 53 00

Microprocessor Lab
FLOW CHART Multiplication of two 8-bit numbers
Section:IT-A
Microprocessor Lab
Start
Load the multiplicand and multiplier from storage locations
Initialize product register to zero, counter register to multiplier
PRODUCT=PRODUCT+MULTIPLICAND
No
Is the carry
flag set?
Yes
CARRY=CARRY+1
Multiplier =Multiplier- 1
NO
Is Multiplier
is =0?
YES
Store product and the carry in the respective locations
: ILOSHAA SRI.R Reg.No:19S1t9o1p06024

NameD

Microprocessor Lab
PROGRAM Multiplication of two 8 bit numbers
Memory Machine - Code Mnemonics

Address Opcode Operand Label Opcode Operand comments
4100 3A 00, 42 LDA 4200 H
4101 00 ; Load accumulator

with multiplicand
4102 42
; Move multiplicand to
4103 47 MOV B, A B-register
4104 3A LDA 4201H Load accumulator with

4105 01 multiplier
4106 42
; Move multiplier to D
4107 57 MOV D, A reg
; Clear register for
4108 0E MVI C, 00 H storing carry
4109 00
410A AF XRA A ; Clear the acc
; Add multiplicand to
410B 80 LOOP ADD B acc
410C D2 JNC OUT1(4110 H)
410D 10
410E 41 ; If no carry then skip
; If carry then
increment carry
410F 0C INR C register
; Decrement the
4110 15 OUT1 DCR D multiplier
4111 C2 JNZ LOOP(410B H) ; If multiplier is not
4112 0B zero then repeat the
4113 41 loop
4114 32 STA 4202 H
4115 02 ; Store the product in

4116 42 location
4117 79 MOV A, C ; Move carry to acc
4118 32 STA 4203 H
4119 03
Microprocessor Lab
411A 42 ; Store the carry in

location
411B 76 HLT ; Halt the execution
OBSERVATION
S No Multiplicand at Multiplier at Product at Carry in location

location 4200 H location 4201 H location 4202 H 4203 H
1. 05 05 19 -
2. AC 05 5C 03
FLOW CHART Division of two 8-bit numbers
Start
Load divisor from storage location
Initialize quotient register
Comp dividend with divisor
Yes
Is
CR=1
No
Sub divisor from dividend
Increment quotient register
Store remainder and quotient

in respective location
Stop
PROGRAM Division of two 8-bit numbers
Microprocessor Lab
Memory Machine - Code Mnemonics

Address Opcode Operand Label Opcode Operand comments
Load accumulator with
4100 3A LDA 4200H divisor
4101 00
4102 42
Move divisor to B-
4103 47 MOV B, A register
Load accumulator with
4104 3A LDA 4201H dividend
4105 01
4106 42
Clear register to store
4107 0E MVI C, 00H carry
4108 00
Compare divided with
4109 B8 LOOP1 CMP B divider
OUT1 If dividend is larger
410A DA JC 4112H than divisor stop
410B 1 12
410C 41
410D 90 SUB B Subtract dividend
Increment quotient.
410E 0C INR C Register
410F C3 JMP LOOP1
4110 09 Go to location 4109
4111 41
4112 32 OUT1 STA 4202H Store remainder
4113 02
4114 42
Move quotient to
4115 79 MOV A, C accumulator
4116 32 STA 4203H Store quotient
4117 03
4118 42
4119 76 HLT End of program
OBSERVATION
S No Divisor at location Dividend at Quotient at Remainder in

4200 H location 4201 H location 4203 H location 4202 H
1. 04 FF 3F 00

Microprocessor Lab
2. 15 BD 09 00
RESULT

Microprocessor Lab
The assembly language program for addition, subtraction, multiplication and division
of two 8-bit numbers are performed and the results are verified with the manual
work.
16-BIT MANIPULATIONS
AIM
1. Addition of two 16- bit numbers 2.
Subtraction of two 16-bit numbers.
3. Multiplication of two 16-bit numbers
APPARATUS REQUIRED:


Microprocessor Lab
FLOW CHART Addition of two 16-bit numbers:

Microprocessor Lab
START
Load addend and augend in four consecutive locations
Move addend to HL pair and augend to DE register
Double Add HL to DE
No
Is carry
flag
set?
YES
CARRY =CARRY+1
Store the sum and the carry in the respective locations
STOP
PROGRAM:

Label Comment
4100 AF XRA A ; Clear Accumulator
; Clear the C register for
4101 4F MOV C,A
carry
4102 2A LHLD 4200 H ; Load HL register pair with
4104 42 H and 4201 H
Microprocessor Lab
; Exchange the contents of

4105 EB XCHG
HL and DE
4106 2A LHLD 4202 H ; Load HL register pair with
4108 42 H and 4203 H
; Perform the double
4109 19 DAD D addition of two 16 bit
numbers
410A 22 SHLD 4204 H
;Store the 16 bit sum in the
410B 04
locations4204Hand 4205H.
410C 42
410D D2 JNC 4111 H
410E 11 ; If no carry then skip carry
410F 41
; Else increment the
4110 0C INR C
contents of carry register
; Move carry to
4111 79 MOV A,C
accumulator
4112 32 STA 4206 H
4113 06 ; Move carry in 4206.
4114 42
4115 76 HLT ;stop the program
OBSERVATION
SNo Lower Higher Lower Higher Lower Higher Carry in

byte of byte of byte of byte of byte of byte of location
addend addend augend augend sum sum
at at at at at at
location location location location location location
4200 H 4201H 4202 H 4203H 4204 H 4205 H 4206 H
1. 54 C2 92 8A E6 4C 01
2. CD AB 86 45 53 F1 00

Microprocessor Lab
FLOW CHART Subtraction of two 16-bit numbers:
START
Load minuend and subtrahend in four consecutive locations
Move minuend to HL pair and subtrahend to DE register pair
Subtract lower order value of minuend from the subtrahend
Store in a memory location
Subtract higher order value of minuend from the subtrahend with borrow
Store in a memory location
No
Is carry
flag
set?
YES
Increment the borrow register
Store the difference and the borrow in the respective locations
STOP
PROGRAM Subtraction of two 16-bit numbers

Microprocessor Lab
Memory Machine – Code Mnemonics Comment

Address Label Opcode Operand Opcode Operand
4400 AF XRA A ;Clear Accumulator

; Clear the C register
4401 4F MOV C,A
for carry
4402 2A LHLD 4500 H ; Load HL register
4403 00 pair with data from
the address
4404 45 4500and 4501
; Exchange the
4405 EB XCHG contents of HL and
DE register pairs
4406 2A LHLD 4502 H ; Load HL register
4407 02 pair with data from
the address
4408 45 4502and 4503
;Move lower order
4409 7D MOV A,L byte of HL to
accumulator
;Subtract contents of
440A 93 SUB E E from
L(accumulator)
440B 32 STA 4204 H ; Load lower order
440C 04 difference in a
440D 42 location 4204 H
; Move higher order
440E 7C MOV A,H
to accumulator
; Subtract higher
440F 9A SBB D orders with the
previous borrow
4410 32 STA 4405 H ; Load higher order
4411 05 difference in the
4412 44 location 4205 H
4413 D2 JNC 4417 H
; If no carry flag set
4414 17
then skip
4415 44
; Increment carry
4416 0C INR C
flag
;move borrow to
4417 79 MOV A,C
accumulator.
4418 32 STA 4506 H
; Load borrow in a
4419 06
Microprocessor Lab
441A 45 location
441B 76 HLT ; Halt the execution
OBSERVATION
S.No Lower Higher Lower byte Higher Lower Higher Carry in

byte of byte of of byte of byte of byte of location
minuend minuend subtrahend subtrahend difference difference 4506H
at location at at at at at location
4500 H location location location location 4505 H
4501H 4502 H 4503H 4504 H
1. AB B2 2C 92 7F 20 00
2. 28 92 60 45 C8 4C 00

Microprocessor Lab
FLOW CHART Multiplication of two 16-bit numbers:

Microprocessor Lab
START
Clear the carry register for storing carry
Load the multiplier and multiplicand from respective

memory location and exchange with contents of DE and
Sp respectively
Clear the product register pair HL
Perform Double addition of

- bit
16numbers
NO
I Is carry
flag
set?
YES
Carry = carry + 1
Multiplier = multiplier
–1
NO Is
multipli
er=0?
YES
Store the product and carry in the respective memory locations
STOP
Name:DILOSHAA
SRI.R Reg.No:1919106024
Section:IT
-A
PROGRAM
Microprocessor Lab
MEMORY MACHINE LABEL MNEMONICS COMMENTS

ADDRESS CODE
4100 06 MVI B, 00 H ; Clear the carry
4101 00 register
4102 2A LHLD 4200 H ; Load the

4103 00 multiplicand from
4104 42 4200
4105 EB XCHG ; Exchange the

contents with DE
register pair
4106 2A LHLD 4202 H ; Load the

4107 02 multiplier from
4108 42 4202 H
4109 F9 SPHL ; Exchange the

contents SP
410A 21 LXI H, 0000 H ; Clear the product

410B 00 register
410C 00 pair
410D 39 MULT DAD SP ; Perform double
addition of 16 bit
numbers
410E D2 JNC NEXT ; If no carry then

(4112) skip incrementing
410F 12 carry register
4110 41
4111 04 INR B ; Else increment
the carry register
4112 1B NEXT DCX D ; Decrement the

multiplier
4113 7A MOV A,D : Check for the

zero flag set in
the following 3
instructions
MEMORY MACHINE LABEL MNEMONICS COMMENTS

ADDRESS CODE
Microprocessor Lab
4114 B3 ORA E ; OR contents of
accumulator with
E reg values
4115 C2 JNZ MULT ; If multiplier is
(410D) not Zero, perform
4116 0D continuous
4117 41 addition
4118 22 SHLD 4300 H ; Store the
4119 00 accumulator in
411A 43 4300 H
411B 78 MOV A, B ; Move carry to
accumulator
411C 32 STA 4302 H ; Store the
411D 02 accumulator in
411E 43 4302 H
411F 76 HLT ; Halt the
execution
RESULT
The assembly language program for addition, subtraction and multiplication of two
16-bit numbers are performed and the results are verified with the manual work.

Microprocessor Lab
CODE CONVERSION
AIM

1. BCD to Binary code conversion and
2. Binary to BCD code conversion
APPARATUS REQUIRED


Microprocessor Lab
FLOW CHART BCD to Binary Conversion
Start
Initialize memory pointer to store data
Mask the higher order nibble
Move same BCD number to accumulator
Separate higher order nibble
Rotate acc content to convert it to lower order nibble
Multiply MS digit by 10
Add B Register Content
Store result in memory location
Stop
PROGRAM BCD to Binary Conversion
Memory Machine Code Mnemonics

Label Comment
; Initialize memory
4100 Start 21 LXI H,5100 H pointer to store BCD
number
4101 00
4102 51

Microprocessor Lab
; Move data to
4103 7E MOV A,M
accumulator
; Mask most significant
4104 E6 ANI 0F
nibble
4105 0F
4106 47 MOV B, A ; Store it in B reg
4107 7E MOV A, M ; Move BCD to acc again
4108 E6 ANI F0 ; Mask lower nibble
4109 F0
410A 0F RRC
410B 0F RRC ; Convert it to lower nibble
410C 0F RRC
410D 0F RRC
410E 57 MOV D, A ; Store it in D reg
410F 1E MVI E, 0A Move the value 0A to
4110 0A register E
4111 AF XRA A ;clear the accumulator
; Multiply most significant
4112 MULT 83 ADD E
bit by 10
Decrement the content of
4113 15 DCR D
register D
MULT
4114 C2 JNZ
(4112 H) If there is no zero ,
4115 12 continue the loop
4116 41
; Add with least significant
4117 80 ADD B
nibble
4118 23 INX H Increment the H content
; Store the equivalent
4119 77 MOV M, A
binary value in memory
411A End 76 HLT ; End of the program
OBSERVATION
Sl.No Input Input Data Output Output Data

Memory Memory
Location Location
1. 5100 45 5101 2D
2. 5100 72 5101 48
3. 5100 96 5101 60

Microprocessor Lab
FLOW CHART Binary to BCD Conversion
Start
Initialize memory pointer to store data
Move data to accumulator
Move data 64 H in Register
Call Subroutine DIVSUB

(Number of 100’s)
Call Subroutine DIVSUB

(Number of 100’s)
Store number of 1’s in memory
Stop
Sub Routine DIVSUB

Microprocessor Lab
DIVSUB
Move FF to B register
Count Number of 100’s, 10’s and 1’s
Subtract from content of C reg
No
Is
Carry=1
Yes
Extract the remainder
DIVSUB
PROGRAM Binary to BCD Conversion

Label Comment
4200 Start 31 LXI SP, 5800 H
; Initialize stack
4201 00
pointer
4202 58
4203 21 LXI H, 4400 H
; Initialize memory
4204 00
pointer
4205 44
; Move memory
4206 7E MOV A, M
contents to acc
4207 0E MVI C, 64 H ; Move divider
4208 64 (100)10 to C reg
4209 CD CALL DIV SUB
; Call division
420A 00
subroutine.
420B 43
420C 23 INX H
; Store result in
420D 70 MOV M, B
memory location
; Move divider (10)10
420E 0E MVI C, 0A H
to C reg
420F 0A

Microprocessor Lab
4210 CD CALL DIV SUB
; Call division
4211 00
subroutine.
4212 43
4213 23 INX H
; Store result in
4214 70 MOV M, B
memory location
4215 23 INX H
; Store number of 1’s
4216 77 MOV M, A
in memory location
4217 76 HLT ; End of the program
SUB ROUTINE DIVSUB:

Label Comment
; Move 00 to B register
4300 06 MVI B,00 H
4301 00
;Subtract content of C
4302 91 SUB C
from acc content
4303 DA JC 430A H
; Jump on carry, if
4304 0A
carry set to 4302 H
4305 43
4306 04 INR B ; Increment B reg
4307 C3 JMP 4302H
; Move divider (100)10
4308 02
to C reg
4309 43
;Add content of C with
430A 81 ADD C
acc content
;Return from
430B C9 RET subroutine
unconditionally

Microprocessor Lab
OBSERVATION
Sl.No Input Memory Input Data Output Memory Output Data

Location Location
1. 4400 FF 4401,4402,4403 02,05,05
2. 4400 B9 4401,4402,4403 01,08,05

Microprocessor Lab
RESULT
Thus the assembly language program to convert a
i) BCD number to a binary number and ii) Binary number

to BCD number are written and verified.
DECIMAL ARITHMETIC AND BIT MANIPULATION
AIM:
To write an assembly language program for decimal arithmetic using 8085 & bit
manipulation of 8085
APPARATUS REQUIRED


Microprocessor Lab
FLOW CHART
Start
Load H,L pair and exchange to D,E pair
Load H,L pair register
Move L register to A register and ADD

with E register
Convert to decimal
Store the
result
Move A register to H
register and add D
register and carry
Microprocessor Lab
Convert to decimal
Stop
PROGRAM Decimal Arithmetic
Memory Machine Code Mnemonics Comment

4100 2A LHLD 4000

4102 40
4103 EB XCHG ; Exchange to DE pair
4104 2A LHLD 4002
4105 02 ; Load HL Pair
4106 40
;Move L register
4107 7D MOV A,L
content to accumulator
;Add E register content
4108 83 ADD E
to accumulator
4109 27 DAA Double addition
410A 32 STA 4000H Store the result
410B 04
410C 40
;Move H register
410D 7C MOV A,H
content to accumulator
410E 8A ADC D ;Addition with carry
410F 27 DAA
4110 32 STA 4005H ;Store the result
4111 05
4112 40
4113 76 HLT ;Halt the program
OBSERVATION
Sl.No
Input Memory Input Data Output Memory Output Data
Location Location
1. 4200 72 4202 71
Microprocessor Lab
4201 99 4203 01
FLOW CHART
Start
Load accumulator and move to B register
Load accumulator with next number
Logical AND between accumulator and B

register
Store the result in a memory location
Logical OR between accumulator and B

register

Microprocessor Lab
Storehe
t result
Logical XOR bet

weenaccumulator
and Bregister
Store resultmemory
in location
Complement the accumulator content
Stop
PROGRAM: Bit Manipulation
Memory Lab Machine Code Mnemonics Comment

Address el Opcode Operand Opcode Operand
4200 3A LDA 4400

4202 40
; Move accumulator
4203 47 MOV B,A
content to B register
4204 3A LDA 4401
4205 02 ; Load Accumulator
4206 40
;Logical AND with B
4207 A0 ANA B
register
4208 32 STA 4500
4209 00 ; Store the result
420A 45
Logical AND with B
420B B0 ORA B
register
420C 32 STA 4501H
420D 01 Store the result
420E 45
Logical AND with B
420F A8 XRA B
register
4210 32 STA 4502
4211 02 ;Store the result
4212 45
Microprocessor Lab
; Complement the
4213 2F CMA
accumulator content
4214 32 STA 4503H
4215 03 Store the result
4216 45
4217 76 HLT ;Halt the program
OBSERVATION

Location Location
1. 4400 94 4500,4501 04,24

4401 24 4502,4503 00,FF

Microprocessor Lab
RESULT
Thus the assembly language program for decimal arithmetic and bit manipulation
using 8085 is executed successfully.
STUDY OF 8086 TRAINER
AIM:
To study the component layout and functional block diagram of 8086/88-LCD trainer.
DESCRIPTION:
following explanation outlines the working of the trainer as a system.. To locate the
individual components refer to the component layout.
i) Inputs and output of the CPU:
The CPU gets the clock from the clock generator 8284 which uses a crystal at 15 or 14.318
MHZ and if it is an 8 MHZ trainer, 24 MHZ. The reset, interrupt lines, and data lines are also
inputs to the CPU. The CPU output5s comprise the Address lines, Data lines and control
lines.
ii) Address and Data Bus:
The 16 bit 8086 bidirectional multiplexed ADDRESS / Data lines and the higher order 4
address lines are brought to latches and buffers. The address lines are latched using ALE and
thus demultiplexed from the data lines. The data lines are buffered through octal transceiver.
The outputs of these IC comprised the 20 bit address and 16/8 bit data bus as the case may
be. The direction of data transfer is decided by direction selection input of transceiver which
is the DT/R* output of the CPU
iii) Control Bus
The other bus is the control bus. The Control signals required for proper operation of the
systems are the IOR* (I/O Read). IOW* (I/O Write), MR* (Memory Read) and MW*
(Memory Write) signals. The Peripherals on the trainer are all I/O mapped and hence to
input from or out[put to a peripheral, IOR* and IOW* are utilized. The MR* and MW* signals
are used to output enable an EPROM & RAM respectively. These signals are generated from
the IO*/M or M/IO* and WR*, RD* signals in minimum mode operation.
Microprocessor Lab
iv) Chip Select Logic
The selection of any peripheral or memory requires a chip select signal CS* to enable that
particular device. This requires address decoding, both memory and I/O where in decoding is
separately achieved for EPROM,RAM and I/O devices. All the above signals- address, data,
control and chip select are routed to all the peripherals and memory devices in the trainer.
v) Keypad and Display:
The block diagram shows a AT keyboard nd LCD display. Thia is the unit with the user
communicates with thw system 16 * 2 LCD module is used for displaying the command and
data. IBM-PC keyboard is used for entering data and control commands. 16x2 LCD module
is used for displaying the commands and data. Eight digits of seven segment displays are
available as an optional peripheral.
vi) Memory
The block diagram shows two sockets for RAM both odd and even in the case of 8086
and 2 RAM sockets for contiguous locations in memory in the case of 8088. Two sockets are
provided for RAM expansion. The basic EPROM capacity available is 16 KB arranged as
odd and even banks in the case of 8086 and continuous locations in the case of 8088.The
remaining EPROM capacity which is 16 KB can be availed as an optional facility. Each of
the EPROM sockets can support 8 /16 / 32 KB memory devices and the RAM sockets 8 / 32
KB devices.
vii) Peripherals
The peripherals depicted in block diagram include

• 8253 Timer for Baud clock generation.
• 8251A USART for RS232C serial communication with associated drivers.
• 8259 – Programmable Interrupt controller
• Audio cassette interface
• 8255 PPI for parallel TTL I/O
System expansion is facilitated by the expansion slots available provided onboard. The
data bus to the expansion slots is sent through a second layer of buffering, the buffers being
degated for addresses of all devices present on board.
CONCLUSION
Thus the component layout and functional block diagram of 8086 trainer is
studied.
ADDITION AND SUBTRACTION

Microprocessor Lab
AIM:
To write an assembly language program to perform 16-bit addition and subtraction ,
double precision addition and subtraction using 8086.
APPARATUS REQUIRED

2 Power Supply +5V 1
3 User interface - 1
4 Bus VMT 1
PROGRAM: 16-Bit addition

1300 8B MOV AX,[1400H] It copies the content

1301 06 of memory location of
1302 00 1400H to the register
1303 14 AX
1304 8B MOV BX,[4102H] It copies the content
1305 1E of memory location
1306 02 of 1402 to the register
1307 14 BX
Add the contents of
1308 01 ADD AX,BX
AX & BX
1309 DB MOV [1500],AX
130A 89 Move the content of
130B 06 AX & BX
130C 00
130D 15
130E F4 HLT Halt the execution
FLOW CHART

Microprocessor Lab
Start
Load the addend from offset address specified in AX
Load the addend from offset address specified in BX
Perform addition [ADD AX, BX] and stores result in AX
Store the output sum from AX into the offset specified
Stop
OBSERVATION:

Location Location
1. 1400,1401 5A,20 1500 47
1402,1403 ED,40 1501 61
PROGRAM: Double precision- Addition

1000 8B MOV AX,[1100H]

1001 06 Load the LSW of
1002 00 addend from 1100
1003 11
1004 03 ADD AX,[1104] Load the LSW of
1005 06 augend from 1104
1006 02 and add with the acc
1007 11 content
1008 89 MOV [1200],AX
Move the accumulator
1009 06

Microprocessor Lab
100A 00 content to 1200
100B 12
100C 8B MOV AX,[1102] Add the acc content
100D 06 with the MSW of
100E 04 augend from 1106
with the previous
100F 11
carry
1010 13 ADC AX,[1106]
1011 06 Move the accumulator
1012 06 content to 1202
1013 11
1014 89 MOV [1202],AX
1015 06 Move the MSW of
1016 02 addend from [1202]
1017 12
Load AM with flag
1018 9F LAHF
register
1019 89 MOV [1204],AX
101A 06 Move AX content to
101B 04 [1204]
101C 12
101D F4 HLT Halt the program
FLOW CHART
Start
Load addend from 1100 and load augend from 110A
Lsw of addend in AX [AX]=1100
AX=[AX]+[1104]
Store the sum in 1200
AX=[1102]

Microprocessor Lab
Add with carry, AX = AX + [1106]
Move [AX] as sum in [1202]
Load AH wit h flag register
Move AH to [1204]
Stop
OBSERVATION:

Location Location
1. 1100,1101,1104, 10,20,20,40 1200,1201 30,60
1105
1102,1103,1105, 30,40,30,10 1202,1203,1204 60,50,00
1106
PROGRAM: 16-Bit Subtraction

2300 8B MOV AX,[2400H]

Move the content of
2301 06
2400H to the register
2302 00
AX
2303 24
2304 8B MOV BX,[2402H]
Move the content of
2305 1E
2402H to the register
2306 02
Microprocessor Lab
2307 24 BX
2308 29 SUB AX,BX Subtract BX from AX
2309 D8 MOV [2500],AX
230A 89 Move the AX from the
230B 06 location 2500H
230C 00
230D 25
230E F4 HLT Halt the execution
FLOW CHART
Start
Load the minuend from offset address specified in AX
Load the subtrachend from offset address specified in BX
Perform subtraction [SUB AX,BX] and stores result in AX
Store the output difference from AX into the offset specified
Stop
OBSERVATION:

Location Location
1. 2400,2401 0C,84 2500 BE
2402,2403 CA,B2 2501 2E

Microprocessor Lab
PROGRAM: Double precision- Subtraction

1200 8B MOV AX,[1300H]

1201 06 Move the LSW of
1202 00 minuend from 1300
1203 13
1204 2B SUB AX,[1304] Subtract the acc
1205 06 content with the LSW
1206 04 of subtrachend rom
1207 13 1304
1208 89 MOV [1400],AX
120A 00 content to 1400
120B 14
120C 8B MOV AX,[1302]
120D 06 Move the MSW of
120E 02 minuend from 1302
120F 13
1210 1B SBB AX,[1306] Subtract the acc
1211 06 content with the
1212 06 MSW of subtrahend
from 1306 with
1213 13
Borrow
1214 89 MOV [1402],AX
1216 02 content to 1402
1217 14
Load AH with flag
1218 LAHF
register
1219 89 MOV [1404],AX
121A 06 Move the acc content
121B 04 to [1404]
121C 12
121D HLT Halt the program

Microprocessor Lab
FLOW CHART
Start
Load minuend from 1300 and load subtrahend from 130A
Lsw of subtrahend, [AX]=1300
Subtrachend LSW of Minuend

AX=[AX] -[1304]
Move AX to [1400],[1400]=[AX]
MSW of Subt
rachend in [AX]
AX=[1302]
Sub with borrow

[1300], AX = AX - [1306]
Store resul
t in [1402]
Load AH with flag register
Move AH to [1404]
Stop
OBSERVATION:

Microprocessor Lab
Location Location
1. 1100,1101,1104, 50,60,20,40 1200,1201 30,20
1105
1102,1103,1105, 30,40,30,10 1202,1203,1204 00,30,00
1106
RESULT:

Microprocessor Lab
Thus the assembly language program for 16-bit & double precision addition and
subtraction has been performed.
MULTIPLICATION AND DIVISION
AIM:
To write an assembly language program to perform 16-bit multiplication and division
using 8086.
APPARATUS REQUIRED

2 Power Supply +5V 1
3 User interface - 1
4 Bus VMT 1
PROGRAM: 16-Bit Multiplication

3000 8B MOV AX,[1100]

3001 06 Load multiplicand
3002 00 from [1100] in AX
3003 11
3004 8B MOV BX,[1102]
3005 1E Loads multiplier in BX
3006 02 from [1102]
3007 11
Performs multiplication
3008 F7 MUL BX
3009 E3
300A 89 MOV [1200],DX Store the MSW in
300B 06 [1200]
300C 00
300D 12
300E 89 MOV [1202],AX
300F 06 Store the LSW in
3010 02 [1202]
3011 12

Microprocessor Lab
3012 F4 HLT Halt the execution
FLOW CHART
Start
Load the multiplicand from [1100] in AX
Load the multiplier from [1102] in BX
Multiply MUL AX,BX
Store MSW of products in DX
Store LSW of product in AX
Stop
OBSERVATION:

Location Location
1. 1100,1101 1A,EF 1200,1201 20,BA
2. 1102,1103 50,CD 1202,1203 C2,BF
PROGRAM: 16-Bit Division

Microprocessor Lab
4000 86 MOV AX,[1100]

4001 06 Load the dividend in
4002 00 [1100] [msw] intoAX
4003 11
4004 8B MOV BX,[1102]
4005 16 Loads dividend in DX
4006 02 from [1102]
4007 11
4008 8B MOV BX
4009 0E Load divisor in CX
400A 04 from [1104]
400B 11
400C F7 DIV CX
Performs Division
400D F1
400E 89 MOV [1200],AX
400F 06 Moves the AX content
4010 02 to 1200
4011 12
4012 89 MOV [1202],DX Moves DX content to
4013 16 [1202]
4014 02
4015 12
4016 F4 HLT Halt the execution
FLOW CHART
Start
Loaddividend and divisor from [1100] & [1102] in AX, DX, CX
Perform Division DIV DX=AX/CX
Store the result in offset [1200] & [1202]
Stop

Microprocessor Lab
OBSERVATION:

Location Location
1. 1100,1101 0A,58 1200,1201 EE,75
2. 1102,1103 C2,71 1202,1203 0E,29

1104,1105 F2,F6 - -
RESULT:
Thus the assembly language program for 16-bit multiplication and division has been
performed.
STRING MANIPULATION
AIM:
To write an 8086 based assembly language program to move a string from one
location to another location
APPARATUS REQUIRED:
• Personal Computer
• MASM assembler
PROGRAM:
ASSUME CS: CODE, DS: CODE, ES: EXTRA

DATA SEGMENT
DATA1 EQU 5000H

Microprocessor Lab
SRC EQU 1000H
COUNT EQU 05H
DATA ENDS
EXTRA SEGMENT
EXTRA1 EQU 6000H
DES EQU 2000H
EXTRA ENDS
CODE SEGMENT
ORG 1000H
START: MOV AX, DATA1

MOV DS, AX
MOV AX, EXTRA1
MOV ES, AX
MOV CX, COUNT
MOV SI, SRC
MOV DI, DES
CLD
REP MOVSW
MOV AH,4CH
INT 21H
CODE ENDS
END START

Microprocessor Lab
RESULT:
Thus the 8086 based assembly language is written to search and replace a string and
to move a string from one location to another location.
KEYBOARD CONTROL & DISPLAY CONTROL
AIM:
To write an 8086 based assembly language program to read a code and scan code
from keyboard and display control using a MASM assembler in 8086
APPARATUS REQUIRED:
• MASM assembler
PROCEDURE:
• The program is typed through the keyboard. • It is then executed in the DOS prompt
Microprocessor Lab
• The .obj and .exe files are created.
• The files are then debugged.
• The output is viewed in the screen by specifying the starting address of the program.
PROGRAM:
• To read a code and scan it from keyboard.
CODE SEGMENT
ASSUME CS: CODE, DS: DATA

ORG 1000H
MOV SI, 1200H
MOV AH, 00H
INT 16 H
MOV [SI], AL
INC [SI]
MOV [SI], AH
MOV AH, 4CH
INT 21 H
CODE ENDS
END
PROGRAM: DISPLAY CONTROL

DATA SEGMENT
Microprocessor Lab
MESSAGE DB ODH,OAH,”MICROPROCESSOR”,ODH,OAH,”$”
DATA ENDS
CODE SEGMENT
ORG 1000H
MOV AX,DATA
MOV DX, AX
MOV AH, 09H
MOV DX,OFFSET MESSAGE
INT 21 H
MOV AH, 4CH
INT 21 H
CODE ENDS
END
RESULT:
Thus the display control has been implemented using a MASM assembler in 8086 and
also keyboard control has also been implemente
FILE MANIPULATION
AIM:
To create and delete a file using a MASM assembler in 8086.
APPARATUS REQUIRED:
• MASM assembler
PROCEDURE:
• The program is typed through the keyboard. • It is then executed in the DOS prompt
• The .obj and .exe files are created.
• The files are then debugged.
• The directory content is then viewed to see if the file is created or deleted.
PROGRAM:

Microprocessor Lab
• FILE CREATION
CODE SEGMENT
ORG 1000H
MOV AX, DATA
MOV DS, AX
MOV DX, 1300H
MOV CX, 0000H
MOV AH, 3C H
INT 21 H
INT 20 H
MOV AH, 4C H
INT 21 H
CODE ENDS
DATA SEGMENT
ORG 1300H
DB ‘TEST.asm’
DATA ENDS
END
• FILE DELETION

CODE SEGMENT
ORG 1000H
MOV AX, DATA

MOV DS, AX
MOV DX, 1300H
MOV AH, 41 H
INT 21 H
MOV AH,4CH
INT 21H

Microprocessor Lab
CODE ENDS
DATA SEGMENT
ORG 1300H
DB ‘ TEST.asm’
DATA ENDS
END
RESULT:
Thus the 8086 based assembly language is written to create and delete a
EXPERIMENTS WITH 8255 IN MODE 0 USING 8085
AIM:
To perform Experiments with 8255 in mode 0 using 8085 trainer
Apparatus required:
S.NO Apparatus Specification Quantity

1 Microprocessor 85 EB2 System 1
2 Power supply +5 V 1
3 Interface Board VMB 008 1
4 BUS VXT 1

Microprocessor Lab
CONTROL WORD FORMAT
Program I
Getting Input through Port A and Store data in memory location
Memory Machine Comments

Address Label Code Mnemonics

Microprocessor Lab
4100 3E 90 MVI A,90 ;initialize Port
A as input
4102 D3 C6 OUT C6 ;Out to Control
register
4104 DB C0 IN C0 ;Read port A
4106 32 00,45 STA 4500 ;store in
memory
location
4109 76 HLT ;End of
program
Program II
Getting Input through Port A and Send the data to port B output port
Memory Machine
Mnemonics Comments
Address Label Code
4100 3E 90 MVI A,90 ;initialize Port
A as input
register
4104 DB C0 IN C0 ;Read port A
4106 D3 C2 OUT C2 ;out to port B
4108 76 HLT ;End of program
BSR MODE CONTROL WORD REGISTER FORMAT:
B7 B6 B5 B4 B3 B2 B1 B0
0 -RESET
1 - SET
BIT SELECT FLAGS

0 – BSR MODE
B3, B2 , B1 are from 000 to 111 for PC0 to PC7

Microprocessor Lab
Program III :
Initializing Port C as Output Port and send data to Port C.
Memory Machine
Mnemonics
Address Label Code Comments
4100 3E 90 MVI A,90 ;Initialize Port
A as input
register
4104 3E 80 MVI A,80 ;Read input data
4106 D3 C4 OUT C4 ;Out to Port c
4108 76 HLT ;End of

program
Program IV :
To send data to port C in mode 0 and set or Reset 1 Bit in BSR Mode.
Memory Machine
Mnemonics
Address Code Label Comments
4100 3E 90 MVI A,90 ;Initialize Port
A as input
register
4104 3E 01 MVI A,01 ;Move 01 To
Acc
4106 D3 C4 OUT C4 ;Out to Port C
4108 3E 07 MVI A,07 ;Move 07 To

Acc to set Bit 3
410A D3 C6 OUT C6 ;Out to Control

register
410C 76 HLT ;End of
program
Observation:

Microprocessor Lab
Experiment Input Input Port Input Output Output Port Output
Number memory Port address Data memory Port address Data
location location
1. 4104 C0 C0 AA 4500 - - AA
2. 4104 C0 C0 F0 - C2 C2 F0
3. 4105 - - 80 - C4 C4 80
4. 4109 - - 70 - C4 C4 07
Result:
Thus experiments with 8255 in mode 0 have been carried out successfully.
EXPERIMENTS WITH 8255 IN MODE 0 USING 8086
AIM:
To perform Experiments with 8255 in mode 0 using 8086
APPARATUS REQUIRED:
S.No Apparatus Specification Quantity

3 Interface Board VMB 008 1
4 BUS VXT 1
Program I
Getting Input through Port A and Store data in memory location
Memory
Machine
Address Mnemonics Comments
Code
4100 BE 00 15 MOV SI, 1500H ;initializes SI
with 1500H
4103 B0 90 MOV AL, 90 Loads AL with
90
4105 E6 C6 OUT C6, AL ;out to control
register
4107 E4 C0 IN AL, C0 ;read port A
Microprocessor Lab
4109 88 04 MOV [SI], AL ;move AL to
[SI]
410B F4 HLT ;end of program
Program II
Getting Input through Port A and Send the data to port B output port
Memory
Machine
Code
4100 B0 90 MOV AL, 90H ;initializes port
A
register
4104 E4 C0 IN AL, C0 ;read port A
register
4108 F4 HLT ;end of program

Program III :
Initialising Port C as Output Port and send data to Port C.
Memory Machine
Mnemonics Comments
Address Code
4100 B0 90 MOV AL, 90 ;initializes port
A
register
4104 B0 80 MOV AL, 80 ;loads AL with
80
register
4108 F4 HLT ;end of program
Program IV :
To send data to port C in mode 0 and set or Reset 1 Bit in BSR Mode.

Microprocessor Lab
Memory
Machine
Code
4100 B0 80 MOV AL, 80 ;initializes port A
register
4104 B0 01 MOV AL, 01 ;moves AL with 01
register
4108 B0 07 MOV AL, 07 ;moves AL with 01
410A E6 C6 OUT C6, AL ;out to control
register
410C F4 HLT ;end of program
OSERVATION:
Experiment Input Input Port Input Output Output Port Output

Number memory Port address Data memory Port address Data
location location
1. 1104 C0 C0 AA 4500 - - AA
2. 1104 C0 C0 F0 - C2 C2 F0
3. 1105 - - 80 - C4 C4 80
4. 1109 - - 07 - C4 C4 07

Microprocessor Lab
Result:
Thus experiments with 8255 in mode 0 have been carried out successfully.
KEYBOARD/DISPLAY INTERFACE WITH THE 8085
AIM :
To interface a keyboard and a display with the 8085 microprocessor and
write assembly language programs for
1. Displaying a character.
2. Reading the scan code of a key.
APPARATUS REQUIRED :
1. Micro 85EB2 trainer kit.

2. VBMB-001 8279 interface board.
3. 8085 opcode sheet.
4. Power supply – 5 V power supply.

Microprocessor Lab
THEORY :
INTEL-8279 Keyboard and Display controller (KDC) is responsible for the Keyboard
/ Display interface of Micro-85EB. It’s main features are
a. Simultaneous keyboard and Display operation.

b. 3 input modes such as Scanned keyboard mode, Scanned Sensor mode, Strobed
input entry mode.
c. 2 output modes such as 8 or 16 character multiplexed displays, right or left entry
display formats.
d. Clock prescalar.
e. Programmable scan timing.
f. 2 key lockout or N-Key Roll-over with contact debounce.
System interface functional description :
The control signals of the 8279 with the CPU are Active low read input(/RD), Active
low write input(/WR), Reset input(RST), Active low chip select(/CS), Buffer address
select(A0), Interrupt request output(IRQ). The functional definition depending upon the
status of the above signals are.
A0 /RD /WR FUNCTION

0 0 1 Read display RAM or Keyboard
FIFO

Microprocessor Lab
0 1 0 Write Display RAM
1 0 0 Read status
1 1 0 Write command
Programming Sequence :
The Keyboard and the Display controller requires proper loading of the following
command words for satisfactory operation…
1. Keyboard / Display mode setup word.

2. Program clock select word.
3. FIFO / Sensor RAM read word.
4. Display RAM read word.
5. Display RAM write word.
6. Blank / Write inhibit word.
7. Clear display word.
8. End Interrupt Setup word.
9. FIFO status initialization word.
The following steps show the sequence to be followed for displaying and inputting a
key, using the KDC….
1. Select the display mode, with the proper number of digits and entry mode.
2. Select the keyboard mode whether encoded, decoded etc..
3. Clear the digits of the display.
4. Select row address for display and auto – increment or non-auto-increment
mode.
5. Write the data to be displayed in the correct segment definition into the data
buffer, or input the key code after the keyboard read operation in the data
buffer.
(Steps 1. to 4. are to be performed with the control section and step 5. is the actual
data section).
SEGMENT DEFINITION
a
f b
g
e c

Microprocessor Lab
.dp d
Data BUS D7 D6 D5 D4 D3 D2 D1 D0
8279 output A3 A2 A1 A0 B3 B2 B1 B0
Segments d c b a dp e g f
8279 Commands
1) KEYBOARD / DISPLAY MODE SETUP
0 0 0 D D K K K
DD – Display mode
00 - 8 8 bit character display – Left entry

01 - 16 8 bit character display – Left entry
10 - 8 8 bit character display – Right entry
11 - 16 8 bit character display – Right entry
KKK – Keyboard mode
000 - Encoded scan keyboard – 2 key lockout

001 - Decoded scan keyboard – 2 key lockout
010 - Encoded scan keyboard – N key rollover
011 - Encoded scan keyboard – N key rollover
100 - Encoded scan Sensor matrix.
101 - Decoded scan Sensor matrix.
110 - Strobed input, Encoded display scan.
111 - Strobed input, Decoded display scan.
2) WRITE DISPLAY RAM
1 0 0 AI A A A A

Microprocessor Lab
This command is written with A0 = 1. All subsequent writes with A0 = 0 will be to the
display RAM.
AI <= Auto Increment Flag. If AI = 1 row address is incremented
automatically.
AAAA <= Row Address of the display RAM to be selected.
3) CLEAR DISPLAY
1 1 0 CD CD CD CF CA
CD CD CD
0 x
- A0- A3 B0-B3 = 00 = ( 0000 0000 )
0
x - A0- A3 B0-B3 = 00 = ( 0000 0000 )
0
x - A0- A3 B0-B3 = 20 = ( 0010 0000 )
1 x - A0- A3 B0-B3 = FF = ( 1111 1111 )
Enables clear display when CD = 1. The rows of display RAM are cleared by the code set
by lower CDbits. If CD = 0 contents of RAM will be displayed
Clear Display Flag (CF) -0 - display

2 - no display
Clear all (CA) -0 - idle
-1 - clears all (FIFO & display)

Microprocessor Lab
FIFO status word:
DU S/E O U F N N N
no of characters in FIFO
FIFO full
Error under run
Error over run
Sensor closure /error

flag for multiple closures
Display unavailable
1-available
0-unavailable
FIFO RAM:
0 1 0 AI * A A A
Initial RAM
address
Not used
Auto increment
mode AI
1-enabled
0-disabled
PROGRAMS :
OBJECTIVE
To initialize 8279 and to display the required character in the required digit of the
display
FLOWCHART

Microprocessor Lab
START
Select the keyboard / display mode which-BITis 00character

for 8
display– Left entry for display and encoded scan keyboard, and output it
to the command word register
Clear the display using the clear display command word
Select the control

ordwto select the Row address and set
- the auto
increment mode.
Write the data to be displayed, which is found in the data bus and display
correspondence given below.
STOP
PROGRAM
Memory Mnemonics Opcode / Comments

Address Operands
4100 MVI A, 00 h 3E, 00 Keyboard / Display mode setup

word
4102 OUT C2 h D3, C2 Out to the control word register
4104 MVI A, CC h 3E, CC Clear display control word
4106 OUT C2 h D3, C2 Out to the control word register
4108 MVI A, 90 h 3E, 90 Control word to select the row

address of the display RAM
410A OUT C2 D3, C2 Out to the control word register

Microprocessor Lab
410C LXI H, 4200 h 21, 00, 42 Point memory to data to be
displayed
410F MOV A, M 7E Move the data from memory to
accumulator
4110 OUT C0 D3, C0 Out to the data register
4112 HLT 76 Halt the execution
2. Read a key code
OBJECTIVE
To read a code of a key pressed from 8279.
FLOWCHART

Microprocessor Lab
START
Read the status of the FIFO
Check for a Key press by checking whether the LS 3 bits is less than 0111
because any key closure will increment the row indicated by AAA bits.
NO
Closure
met
YES
Write the command word for Reading the FIFO RAM and then read the
FIFO RAM
STOP
PROGRAM
Memory Mnemonics Opcode / Comments

Address operands
4100 IN C2 H DB, C2 Read the FIFO status word

with port address c2
4102 ANI 07 H E6, 07 Check for a key press
4104 JZ LOOP (4100) CA, 00, 41 Closure not met

Microprocessor Lab
4107 MVI A, 40 H 3E, 40 Command word for reading
the FIFO RAM
4109 OUT C2 H D3, C2 Output it to the command
word reg
410B IN C0 H DB, C0 Read the FIFO data from the
data reg with address C0
410D STA 4200 H 32, 00, 42 Store the value in a memory
4110 HLT 76 Halt the execution
OSERVATION:(DISPLAY)

Location Location
1. 4200 68 - E
2. 4200 FF - 0
3. 4200 98 - 1
OSERVATION:(KEYBOARD)
Sl.No Control Shift Input Data Output Memory Output

Location Data
1. 0 0 2 4200 02
2. 0 1 4 4200 44
3. 0 0 6 4200 86
4. 0 1 6 4200 C8

Microprocessor Lab
RESULT:
Thus the 8279 Keyboard / Display controller is interfaced with the 8085
microprocessor and programs for displaying a character and reading the key code of the key
pressed are executed and verified.
KEYBOARD/DISPLAY INTERFACE WITH THE 8086
AIM:
To interface a keyboard and a display with the 8085 microprocessor and
write assembly language programs for
2. Reading the scan code of a key.
APPARATUS REQUIRED :
1. Micro 86 EB2 trainer kit.

2. VBMB-001 8279 interface board.

Microprocessor Lab
PROGRAMS :
PROGRAM
Memory Machine code Mnemonics

Address Label Comments
4100 C7 MOV AL, 00H Move 00 data to
4101 C0 the accumulator
4102 00
4103 E6 OUT C2,AX Give the content
C2 of accumulator to
4104 Control used
register
4105 C7 MOV AX.00CC Move the value
4106 C0 00cc to
4107 CC accumulator
4108 00
4109 E7 OUT C2, AX Out to control
410A C2 register
410B C7 MOV AL, 0090 Initialize port A
410C C0
410D 90
410E 00
410F E7 OUT C2,AX Out to control
4110 C2 register
4111 C7 MOV AL ,0088 Move the value
4112 C0 0088 to
4113 88 accumulator
4114 00
4115 E7 OUT C0,AX Write the content
4116 C0 of AX to port A
4117 C7 MOV AL, 00FF Move the content
4118 C0 of 00FF to
4119 FF accumulator
411A 00
411B C7 MOV CX, 0005 Move the content
411C C1 of 0005 to CX
411D 05
411E 00
411F NEXT E7 OUT C0,AX Write the content
411A C0 of acc to port A
411B E2 LOOP NEXT Continue the loop
411C FC
Microprocessor Lab
411D F4 HLT Halt the program
2. Read a key:
Memory Machine code Mnemonics

Address Label Opcode Operand Opcode Operand Comments
4100 C7 MOV BX, 5000H Initializes BX

4101 C3 with 5000H
4102 00
4103 50
4104 LOOP E4 IN AX,C2 Read port B
4105 C2
4106 F6 TEST AX, 0007 Test the 07 to
4107 C0 accumulator
4108 07
4109 74 JZ LOOP(4104) If zero, jump to
410A F9 the loop
410B 41
410C C6 MOV AX, 0040 Load AX with 40
410D C0
410E 40
410F 00
4110 E6 OUT C2, AX Write the content
4111 C2 of AX with port B
4112 E4 IN AL, C0 Read port A
4113 C0
4114 88 MOV [BX], AX Move AX to
4115 07 [BX]
4116 F4 HLT Halt the
execution

Microprocessor Lab
RESULT :
Thus the 8279 Keyboard / Display controller is interfaced with the 8086 microprocessor and programs for displaying a
character and reading the key code of the key pressed are executed and verified
TIMER INTERFACE WITH THE 8085
AIM:
To generate square waveform using 8253 timer interface card.
APPARATUS REQUIRED:
1. Micro 85EB2 trainer kit.

Microprocessor Lab
4. 8253 timer Interface card.
THEORY:
The 8253 is organized, as three 16-bit counters each with a count rate of up to
2MHZ.The three counters are identical in operation. Each counter consists of a single, 16-bit,
pre-settable, down counter. The counter may operate in either binary or BCD and its input
gate and output are configured by the selection of modes stored in the control register.
The counters are fully independent and each can have separate mode configuration
and counting operation. The reading of the contents of each counter is available to the
programmer with simple READ operations for event counting applications.
The control word register controls the operation mode of each counter, selection of
binary or BCD counting and the loading of each count register depending upon the
information stored in it.
Program – 1
Generate Square waveform using mode-3 of 8253
Memory
Opcode /
operands
4100 3E
MVI A, 36 Move the data 36 to the accumulator
4101 36
4102 D3 Initialize timer in channel-0 and in
OUT CE
4103 CE mode-2
4104 3E
MVI A, 0A Move the data 0A to the accumulator
4105 0A
4106 D3 OUT C8
Move LSB to counter
4107 C8
4108 AF
XRA A Clear the accumulator
4109 D3
410A C8 OUT C8 Move MSB to counter
410B 76 HLT Halt the execution

Microprocessor Lab
RESULT:
Thus Square waveform is generated using timer interface 8253.

TIMER INTERFACE WITH THE 8086
AIM:
To generate pulse and square waveform using 8253 timer interface card.
APPARATUS REQUIRED:
1. Personal Computer System

2. VDA 107 interface board.
3. 8253 timer Interface card.
4. CRO.
THEORY:
The 8253 is organized, as three 16-bit counters each with a count rate of up to
2MHZ.The three counters are identical in operation. Each counter consists of a single, 16-bit,
pre-settable, down counter. The counter may operate in either binary or BCD and its input
gate and output are configured by the selection of modes stored in the control register.
The counters are fully independent and each can have separate mode configuration
and counting operation. The reading of the contents of each counter is available to the
programmer with simple READ operations for event counting applications.

Microprocessor Lab
The control word register controls the operation mode of each counter, selection of
binary or BCD counting and the loading of each count register depending upon the
information stored in it.
Memory
Opcode /
operands
4100 B0 AL,
MOV
4101 36 36H
4102 E6 Initialize timer in channel-0 and in
OUT CE,AL
4103 CE mode-2
4104 B0
MOV AL, 0A
4105 0A
4106 E6 OUT C8,AL
Move LSB to counter
4107 C8
4108 B0
MOV AL,00H
4109 00
410A E6
OUT C8,AL Move MSB to counter
410B C8
410C F4 HLT Halt the execution

Microprocessor Lab
RESULT:
Thus Square waveform and pulse waveform are generated using timer interface 8253.
PROGRAMMABLE COMMUNICATION INTERFACE WITH THE 8085
AIM:
To transmit and receive a character using 8251 interface card.
APPARATUS REQUIRED:
Microprocessor Lab
S.No Apparatus Specification Quantity

3 Interface Board RS 232C 1
4 BUS VXT 1
THEORY:
The 8251A is used here as a peripheral device for serial communication and is
programmed by the CPU to operate using virtually any serial data transmission technique.
The USART accepts data characters from the CPU in parallel format and then converts them
into a continuous serial data stream for transmission. Simultaneously, it can receive serial
data streams and convert them into parallel data characters for the CPU. The CPU can read
the complete status of the USART at any time. These include data transmission errors and
control signals.
The 8251A commands are written into two registers, namely the mode instruction
register and the command instruction register. These two registers cannot be read from.
Mode instruction definition:
This format defines the general operational characteristics of the 8251A. it must
follow a reset operation immediately. This format defines the baud rate, character length,
parity and stop bits required to work with asynchronous data communication. By selecting
the baud factor to sync mode the 8251A can be made to operate in the synchronous mode.
Command Instruction definition:
This format defines a status word that is used to control the actual operation of
8251A. all control words written into 8251a after the mode instruction will load the
command instruction. The command instruction can be written into 8251A at any time in the
data block during the operation of the 8251A. to return to the mode instruction format, a
master reset is required. The command instruction format controls the actual operation of the
selected format.
RS232 serial definition:
It is the standard developed by EIA (Electronics industries Association) for serial data
transfer. The standard follows the following voltage level i.e., logic high – 12V and for a
logic low +12V.

Microprocessor Lab
Program : To transmit data
Memory
Opcode /
operands
1000 3E move the 36 to
MVI A, 36
1001 36 accumulator
1002 D3 out the accumulator
OUT CE
1003 CE data to CE
1004 3E move the 0A to
MVI A,0A
1005 OA accumulator
1006 D3 OUT C8 out the accumulator
1007 C8 data to C8
MVI A, 00
1009 00 accumulator
100A D3 out the accumulator
OUT C8
100B C8 data to C8
100C 3E move the 4E to
MVI A, 4E
100D 4E accumulator
100E D3 ; out the accumulator
OUT C2
100F C2 data to C2
MVI A,37
1011 37 accumulator
1012 D3 ; out the accumulator
OUT C2
1013 C2 data to C2
1014 37 move the 41 to
MOV A,41
1015 41 accumulator
1016 D3 out the accumulator
OUT CO
1017 CO content to C0
1018 CD
INT 2
1019 O2
To receive data:
Memory Machin code

Address opcode / Mnemonics Comments
operands
1200 DB move the content
IN C0
1201 C0 to CO
1202 32
store the result in
1203 50 STA 1250
1250
1204 12

Microprocessor Lab
1205 76 HLT halt the program
RESULT:
Thus a character is transmitted and received using the programmable communication

interface 8251.
PROGRAMMABLE COMMUNICATION INTERFACE WITH THE 8086
AIM:
To transmit and receive a character using 8251 interface card.
APPARATUS REQUIRED:
S.NO Apparatus Specification Quantity

3 Interface Board RS 232C 1
4 BUS VXT 1
THEORY:
Microprocessor Lab
The 8251A is used here as a peripheral device for serial communication and is
programmed by the CPU to operate using virtually any serial data transmission technique.
The USART accepts data characters from the CPU in parallel format and then converts them
into a continuous serial data stream for transmission. Simultaneously, it can receive serial
data streams and convert them into parallel data characters for the CPU. The CPU can read
the complete status of the USART at any time. These include data transmission errors and
control signals.
The 8251A commands are written into two registers, namely the mode instruction
register and the command instruction register. These two registers cannot be read from.
Mode instruction definition:

This format defines the general operational characteristics of the 8251A. it must
follow a reset operation immediately. This format defines the baud rate, character length,
parity and stop bits required to work with asynchronous data communication. By selecting
the baud factor to sync mode the 8251A can be made to operate in the synchronous mode.
Command Instruction definition:
This format defines a status word that is used to control the actual operation of
8251A. all control words written into 8251a after the mode instruction will load the
command instruction. The command instruction can be written into 8251A at any time in the
data block during the operation of the 8251A. to return to the mode instruction format, a
master reset is required. The command instruction format controls the actual operation of the
selected format.
RS232 serial definition:
It is the standard developed by EIA (Electronics industries Association) for serial data
transfer. The standard follows the following voltage level i.e., logic high – 12V and for a
logic low +12V.
To initialize 8253 & 8251 & to check the transmission & reception of a character.
The program first initializes the 8253 to give an o/p clk frequency of 150KHZ at
channel 0 which will give a 9600 band rate of 8251.Then 8251 is also initialized with data
4E & 37.
Make sure that the o/p of channel 0 is connected to transmitter clk & receiver clk of
8251 connect the RTS with CTS & TXD with RXD by setting the jumpers accordingly.
Execute the program starting from location 4100(Hex). It instructs the 8251 to send data 41
serially & it also resets the system. Now execute the following program which receives the
character 41H & stores it at location 1250H.

Microprocessor Lab
Program : To transmit data
Memory
Opcode /
operands
1000 B0 Move the content 36
1001 MOV AL,36
36 to AL
1002 E6 Move the lower
OUT CE,AL accumulator content
1003 CE
to CE
1004 B0 Move the 0010
1005 MOV AL,10
10 content to AL
1006 E6 Move the AL content
1007 OUT C8,AL
C8 to C8
1008 B0
1009
MOV AL,00 Move the 00 to AL
00
100A E6 Move the AL content
100B
OUT C8,AL
C8 to C8
100C B0 Move the 4E to lower
100D MOV AL,4E
4E accumulator
100E E6 Move the lower
100F OUT C2,AL
C2 content to C2
MOV AL,37 to lower ac23c
1011 37
content
1012 E6 Out the AL content to
1013 OUT C2,AL
C2 C2
1015 MOV AL,41
41 to AL
1016 E6 Out the AL content to
1017 OUT C0,AL
C0 C0
1018 C0 2
1019
INT
02 Halt the program
101A
HALT
FE
Program : To Receive data
Memory
Opcode /
operands
1200 E4 Move the content 36
1201 CO MOV AL,36
to AL
1202 BB 50 MOV BX,1250 Move the content to

Microprocessor Lab
1203 BX
1204 12
1205 88 MOV [BX],AL Move AL TO bx
1206 07
1207 CD
1208
INT 2
02
1209 FE HLT Halt the program
RESULT:
Thus a character is transmitted and received using the programmable communication

interface 8251.
STUDY OF 8051 MICROCONTROLLER
AIM:
To study the component layout and functional block diagram of 8051-EB trainer.
DESCRIPTION:

Microprocessor Lab
following explanation outlines the working of the trainer as a system.
i) Inputs to and Outputs from the CPU
The CPU gets the clock from the clock generator which is a crystal at 12 MHz. The
reset, interrupt lines, and data lines are also inputs to the CPU. The CPU outputs
comprise the address lines, data lines and control lines.
ii) Address and Data Bus
In 8051, Port 0 is (also) the multiplexed low-order address and data bus. Port 2 emits
the high-order address byte during accesses to external program and data memory. The
multiplexed address/data lines are brought to address latches and data transceivers
respectively. The higher order address lines are brought to the address latches. The
outputs of the address latches and transceivers comprise the 16-bit address bus (A0-A15)
and 8-bit data bus (D0-D7) respectively. The direction select input of the transceiver
depends upon RD* and WR* signals.
iii) Control Bus
The other bus is the control bus. The Control signals required for proper operation of
the system are the IOR* (I/O Read). IOW* (I/O Write), MR* (Memory Read) and MW*
(Memory Write) signals. The Peripherals on the trainer are all memory mapped utilizing
the memory address from FF00 to FFFF. Hence, IOR* and IOW* will select for address
from FF00 to FFFF. The MR* and MW* signals are utilized to read or write the memory
devices namely, EPROM and RAM.
iv) Chip Select Logic
The selection of any peripheral or memory requires a chip select signal CS* to enable
that particular device. This requires address decoding, both memory and I/O. All the
above signals address, data, control and chip select are routed to all the peripherals and
memory devices in the trainer.
v) IBM-PC Keyboard and LCD
In this version of Micro-51 EB, IBM-PC keyboard is used for entering data and
control commands. 16x2 LCD module is used for displaying the commands and data.
Eight digits of seven segment displays are available as an optional peripheral.
vi) Memory
The block diagram shows an 32 Kbytes EPROM, and 32 Kbytes RAM (the address
locations FF00-FF1F and FFC0-FFFF can not be used as they are used for I/O mapping).
The external Program memory and Data memory of 8051 are combined in Micro-51 EB
with the help of appropriate circuitry.
vii) Peripherals
Serial port of 8051 is used for serial communication with associated driver IC 232 for
interface immunity and overcoming attenuation; two 8255 PPI (Programmable Peripheral
Microprocessor Lab
Interface) for TTL I/O drivers. System expansion is facilitated by the VXT_bus provided
Onboard.
CONCLUSION:
Thus the component layout and functional block diagram of 8051-EB trainer
is studied
8-BIT MANIPULATION
AIM:
To write an 8051 assembly language program to perform

1. Addition of two 8 bit numbers 2.
Subtraction of two 8 bit numbers and
3. Multiplication of two 8-bit numbers.
APPARATUS REQUIRED:

1 Microcontroller Micro 51 EB with power 1
trainer cord
PROGRAM

Microprocessor Lab
Memory Address Object Codes Mnemonics

8100 C3 CLR C
8101 74 MOV A,#20
8102 20
8103 34 ADDC A, #10
8104 10
8105 90 MOV DPTR, #8500
8106 85
8107 00
8108 F0 MOVX @DPTR, A
8109 80 HERE : SJMP HERE
810A FE
Subtraction of two 8 bit numbers:

8100 C3 CLR C
8101 74 MOV A, #DATA1
8102 20
8103 94 SUBB A, #DATA2
8104 10
8105 90 MOV DPTR, #8500H
8106 85
8107 00
8109 80 HERE : SJMP HERE
810A FE
Multiplication of two 8-bit numbers:

8100 74 MOV A, #DATA1
8101 0A
8102 75 MOV B, #DATA2
8103 F0
8104 88
8105 A4 MUL AB
8106 90 MOV DPTR, #8500
8107 85
8108 00
810A A3 INC DPTR
810B E5 MOV A, B

Microprocessor Lab
810C F0
810D F0 MOVX @DPTR, A
810E 80 HERE:SJMP HERE
810F FE
RESULT
The assembly language program for addition, subtraction and multiplication of two 8-
bit numbers are performed and the results are verified with the manual work.
16-BIT MANIPULATION
AIM
To write an 8051 assembly language program to perform addition of two 16 bit

numbers.
APPARATUS REQUIRED

trainer cord
PROGRAM

Microprocessor Lab

8100 C3 CLR C
8101 74 MOV A, #DATAM1
8102 20
8103 34 ADDC A, #DATAM2
8104 40
8105 90 MOV DPTR, #8550
8106 85
8107 50
8109 A3 INC DPTR
810A 74 MOV A, #DATAL1
810B 50
810C 34 ADDC A, #DATAL2
810D 46
810E F0 MOVX @DPTR, A
810F 80 HERE: SJMP HERE
8110 FE
OSERVATION:

Location Location
1. 8102,8104 20,40 8550 60
2. 810B,810D 50,46 8551 96

Microprocessor Lab
RESULT
The assembly language program for addition and multiplication of two 8-bit numbers
are performed and the results are verified with the manual work.
ARRAY OPERATIONS – SUM OF N ELEMENTS
AIM:
To write an 8051 assembly language program to perform sum of N elements present

in a block of memory.
APPARATUS REQUIRED

trainer cord
PROGRAM

8100 90 MOV DPTR, #8200
8101 82
8102 00
8103 E0 MOVX A, @DPTR
8104 A3 INC DPTR
8105 F8 MOV R0, A
8106 75 MOV B, #0
8107 F0
8108 00
8109 A9 MOV R1, B
810A F0
810B C3 ADD : CLR C
Microprocessor Lab
810C E0 MOVX A, @DPTR
810D 25 ADD A, B
810E F0
810F F5 MOV B, A
8110 F0
8111 50 JNC NC
8112 01
8113 09 INC R1
8114 A3 NC : INC DPTR
8115 D8 DJNZ R0, ADD
8116 F4
8117 90 MOV DPTR #8500
8118 85
8119 00
811A E9 MOV A, R1
811B F0 MOVX @DPTR, A
811C A3 INC DPTR
811D E5 MOV A, B
811E F0
811F F0 MOVX @DPTR, A
8120 80 HLT : SJMP HLT
8121 FE

Microprocessor Lab
RESULT
The assembly language program for sum of N elements is performed and the
results are verified with the manual work.

MCMP Lab Record 1919106016

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SONA COLLEGE OF TECHNOLOGY

Junction Main Road, Sona Nagar,

Register No.: 1919106016

Lab-in-charge Head of the Department

Internal Examiner. External Examiner.

1. 29.01.21 Study of 8085 Transfer 1 20

STUDY OF 8085 TRAINER

i) Inputs to and outputs from the CPU

ii) Address and Data bus:

v) Keypad and display:

Name:Balaji G Reg.No:1919106016 Section:IT-A

The block diagram shows an 8 KB EPROM or 32 KB EPROM and an 8 KB RAM or 32

System expansion is facilitated by virtue of the expansion slots provided on board.

Name:DILOSHAA SRI.R Reg.No:1919106024 Section:IT-A

Sl.No Apparatus Specification Quantity

Name:DILOSHAA SRI.R Reg.No:1919106024 Section:IT-A

FLOW CHART Addition of two 8-bit numbers:

Name:DILOSHAA SRI.R Reg.No:1919106024 Section:IT-A

Load addend and augend in two consecutive locations

Move addend to accumulator and augend to some register

Add accumulator and the register contents

Store the sum and the carry in the respective locations

Addition of two 8 bit numbers:

Memory Machine – Code Mnemonics

Name:DILOSHAA SRI.R Reg.No:1919106024 Section:IT-A

SNo Addend at location Augend at Sum at location Carry in location

FLOW CHART Subtraction of two 8-bit numbers:

Name:DILOSHAA SRI.R Reg.No:1919106024 Section:IT-A

Load minuend and subtrahendconsecutive

Move minuend to accumulator and subtrahend to some

Subtract accumulator and the register contents

Increment the borrow register

Store the difference and the borrow in the respective locations

Subtraction of two 8-bit numbers:

Memory Machine – Code Mnemonics

Name:DILOSHAA SRI.R Reg.No:1919106024 Section:IT-A

S No Subtract at location Subtrahend at Difference at Borrow in location

Name:DILOSHAA SRI.R Reg.No:1919106024 Section:IT-A

FLOW CHART Multiplication of two 8-bit numbers

Load the multiplicand and multiplier from storage locations

Initialize product register to zero, counter register to multiplier

Store product and the carry in the respective locations

: ILOSHAA SRI.R Reg.No:19S1t9o1p06024

Name:DILOSHAA SRI.R Reg.No:1919106024 Section:IT-A

PROGRAM Multiplication of two 8 bit numbers

Memory Machine - Code Mnemonics

4100 3A 00, 42 LDA 4200 H

4101 00 ; Load accumulator

4104 3A LDA 4201H Load accumulator with

4115 02 ; Store the product in

411A 42 ; Store the carry in

S No Multiplicand at Multiplier at Product at Carry in location

FLOW CHART Division of two 8-bit numbers

Load divisor from storage location

Initialize quotient register

Comp dividend with divisor

Increment quotient register

Store remainder and quotient

Memory Machine - Code Mnemonics

S No Divisor at location Dividend at Quotient at Remainder in

Name:DILOSHAA SRI.R Reg.No:1919106024 Section:IT-A

Name:DILOSHAA SRI.R Reg.No:1919106024 Section:IT-A