Micro CH 04

Microprocessor System - Microprocessor
CHAPTER: 04
Microprocessor System
4.1 PIN CONGURATION OF 8085
1
2
2
1
6
2
3
4
1 Frequency and power supply signals
2 Externally or peripheral initiated signals
3 Multiplexed address/data bus
4 Higher order address bus
5 Control and status signals
6 Serial IO signals
baikunth2a@gmail.com 1 Compiled by: Baikuntha Acharya

Sagarmatha Engineering College
CHAPTER: 04
8085 is a 40 pin IC, DIP package. Signals from the pins can be grouped as follows:
a Power Supply and Clock frequency:

q VCC: +5V power supply
q VSS: Ground reference
q X1 and X2: A crystal oscillator to generate clock signal (6MHz internally
divided into 3MHz)
q CLK OUT: It can be used as the system clock for other devices.
a Externally Initiated signals:

q INTR (Input): Interrupt request, used as a general purpose interrupt.
q INTA (Output): This is used to acknowledge an Interrupt.
q RST 7.5, 6.5, 5.5 (inputs): These are vectored interrupts.
l RST7.5 has the highest priority and it is edge triggered.
l RST6.5 is level triggered.
l RST5.5 has the lowest priority and it is edge triggered.
q TRAP (input): This is a non-maskable interrupt with highest priority.

l This is a vectored interrupt. It is edge as well as level triggered.
q HOLD (input): Request use of Address and data bus by peripheral (Like DMA).
q HLDA (output): Hold Acknowledge: This signal acknowledges the HOLD
request.
q READY (Input) : Ready signal from slow- responding peripheral.
l Used to delay the microprocessor read and write cycles until a slow
responding peripheral is ready to send or accept data.
q RESET IN : MPU gets reset, PC->0000H, resets the Interrupt Enable

and HLDA Flip-flop.
q RESET OUT : Indicates that the MPU is being reset to other devices.
aAddress bus:
q 16 signal lines that are used as the address bus.
q These lines are split into two segments.
A15-A8-Unidirectional Higher Order (most significant 8 bits of the memory
address or the 8 bits of the I/O address.) Bus.
AD7-AD0-Multiplexed Lower Address/8-bit Data Bus

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a Data bus:
q The signal lines AD7- AD0 are multiplexed to carry bidirectional data.
q AD7- AD0 are used the low order address bus as well as data bus.
a Control and status signals:

q Two control signals:
RD- Read control signal (active low)
-commands to read data from selected I/O or Memory.
WR- Write control signal (active low)
-commands to write data to selected I/O or Memory.
q Three status signals:

IO/M- Used to differentiate between I/O and memory .
HIGH-I/O operation. LOW-Memory operation.
S1 and S0- Used identify various operations (Op-code fetch, Operand Fetch,
Read, Write).
ALE (Address Latch Enable)- Used to latch low-order address from the
multiplexed bus.
IO/M S0 S1 Operation
0 0 0 Halt
0 0 1 Memory Write
0 1 0 Memory Read
1 0 1 I/O Write
1 1 0 I/O Read
0 1 1 Opcode Fetch
1 1 1 Interrupt Acknowledge

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a Serial IO Signals:
q SID (input) - Serial input data line
q SOD (output) - Serial output data line
l These signals are used for serial communication.
PIN DIAGRAM OF 8086 MICROPROCESSORS
The Microprocessor 8086 is a 16-bit CPU available in different clock rates and
packaged in a 40 pin CERDIP or plastic package.
OPERATES IN TWO MODES:

- Single processor configuration
- Multiprocessor configuration to achieve high performance
DIP: Dual in-line package
8086 Signals: (i) Common functions signals
(ii) Functions for minimum mode
(iii) Functions for maximum mode

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a Functions for minimum mode ( MN/MX=0)
q M/IO - Used to differentiate between I/O and memory .
l HIGH- Memory operation. l LOW-I/O operation.
q INTA – Interrupt Acknowledge - Responces to peripheral that interrupt
has been accepted.
q ALE – Address Latch Enable: Latches the address into BUS.
q DT/R – Data Transmit/Receive – Direction of data flow through the
trans-receivers (bidirectional buffers).
q DEN – Data Enable: It is used to enable the trans-receivers (bidirectional
buffers) to separate the data from the multiplexed address/data signal.
q HOLD, HLDA - Hold Hold/Acknowledge - For requesting the bus access.
l After receiving the HOLD request, issues the hold acknowledge signal on.
TIMING DIAGRAM: MINIMUM MODE
WRITE CYCLE TIMING DIAGRAM READ CYCLE TIMING DIAGRAM

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a Functions for maximum/multiprocessor mode ( MN/MX=0)
iWorks with 8288 Bus Controller.
q S2, S1, S0 – Status Lines - These are the status lines which reflect
the type of operation, being carried out by the processor.
q LOCK (output) – If LOCK signal is low: other system bus master will be
prevented from gaining the system bus,
q RQ/GT0 , RQ1/GT1 – Request/Grant - used for bus requests by other

processors like 8087 or 8089.
S0 S1 S2 Operation S3 and S4: Shows which segment

is currently accessed.
0 0 0 Interrupt Acknowledge
S3 S4 Operation
0 0 1 Read I/O port
0 0 Extra Segment (ES)
0 1 0 Write I/O port
0 1 Stack Segment (SS)
0 1 1 Halt
1 0 Code Segment (CS) or
1 0 0 Code Access
Idle
1 0 1 Read Memory 1 1 Data Segment (DS)
1 1 0 Write Memory
S5: It serves as an interrupt flag.
1 1 1 Passive S6: Shows status of the bus master
TIMING DIAGRAM: MAXIMUM MODE

WRITE CYCLE TIMING DIAGRAM READ CYCLE TIMING DIAGRAM
DEN

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a Common signals for both modes
q AD15-AD0 - Multiplexed memory I/O address and data lines.
q A19/S6,A18/S5,A17/S4,A16/S3 - multiplexed address and status lines.
q BHE/S7-Bus High Enable: Transfers data over higher order( D15-D8 ) data bus.
q RD – Read - Low signal performs memory or I/O read operation.
q READY - Acknowledgement from the slow device for data ready.
q INTR-Interrupt Request - For sending interrupt request.
q TEST - Exaimed by WAIT instruction.
l If TEST pin goes low, execution will continue,
l Else the processor remains in an idle state.
q CLK- Clock Input - Provides the basic timing information for processor.
4.2 BUS STRUCTURE

q A bus is a communication pathway between two or more microprocessor
components (CPU, Memory and I/O units).
√ System bus consists of number of separate lines which connects
microprocessor components (CPU, Memory and I/O) by transmitting ‘0‘ or ‘1‘.
l System bus = Data Bus + Control Bus + Address Bus
a Data Bus:
√ Group of wires which carries data between the system modules.
√ Width of data bus (No. of bits) can be 4, 8, 16, 32, or 64 lines.
√ These number represents the no. of bits they can carry.
a Address Bus:
√ Group of wires which carries address between the system modules.
√ Carries address of memory in which R/W has to be performed
√ Also used to address I/O ports.

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a Control Bus:
√ Group of wires which carries control Informationas.
√ Transmits command and timing info between system modules.
√ Memory Write, Memory Read, I/O Write, I/O Read, Transfer
Acknowledge, Bus Request, Bus Grant, Interrupt Request,
Interrupt Acknowledge
a BUS TYPES:
q Transmitter and receivers are synchronized of clock.
q Data bits are transmitted with synchronization of clock.
q Devices connected by synchronous bus should be at same speed.
q All the events start at beginning of the clock cycle.
q Used in high – speed transmission.
Advantages: Involves very little logic and can run very fast.
Dis-Advantages: Clock skew limits bus length.
2) Asynchronous Bus:
q Transmitters and receivers are not synchronized by clock
q Devices connected by synchronous bus may not be at same speed.
q Start and stop bits are required to establish communication of each data.
q Occurrence of one event on the bus follows and depends on the occurrence
of previous event.
q Used in low
speed transmission.
l MSYNC-Master synchronous signal
l SSYNC-Slave synchronous signal

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3) Read and Write Bus Timing of 8085 and 8086 Microprocessors:
Operation of microprocessor are:
l Op- Code fetch
l Memory Read /Write
l I/O Read/ Write
l Request acknowledgement
Instruction Cycle :- the time required completing the execution of an instruction. The
8085 instruction cycle consists of one to six machine cycles or one to six operations.
- Fetch cycle.
- Decode instruction.
- Reading effective address.
- Execution cycle
Machine Cycle :- It is defined as the time required to complete one operation of accessing
memory, I/O, or acknowledging an external request. This cycle may consist of three to six
T-states.
Clock Cycle (T state) :- It is defined as one subdivision of the operation performed in one
clock period.
- T states starts at the falling edge of a clock pulse.
Clock Frequency of 8085: 3.125 MHz

Time (T) for one clock: 1/3.125 MHz = 0.32uS
Time taken for execution = Number of T-States in instructions * 0.32uS.
- Opcode fetch & execute(4T states)

At T1, address is placed on the address bus
At T2. Memory places the data on data bus
At T3. Data is moved to the concerned location i.e. IR.
At T4 Execution of instruction takes place
But there are cases where more than 4T states are required. Eg (6-T States): CALL,
Conditional CALL, DCX, INX, PCHL, SPHL, PUSH, Conditional RET.

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OPCODE FETCH MACHINE CYCLE
ADDRESS OPCODE
2000H MOV A,B (78H)
Explanation of above Timing Diagram:
√ The first operation in any instruction is always Op-Code fetch from Memory.
√ Let’s consider the instruction MOV A, B stored at memory location 2000H.
√ Op-Code for the instruction is 78H and Op-Code fetch cycle is of 4 clock cycles.
STEP1: √ PC --> Address Bus

√ At T1:
l 20H -> A8-A15 Higher Order Address bus.
l 00H --> AD0-AD7 bus by Activating ALE.
√ Status signals: IO/M = 0, S0=1, s1=1 for opcode fetch operation.
STEP2: √ At T2 & T3: CU sends RD to enable the memory chip.
STEP3: √ The byte from the memory location --> Data bus.
√ Data (78H) into D0-D7 and RD goes high impedance.
STEP4: √ The instruction 4FH is decoded.

√ Content of B will be copied into A during clock cycle T4.

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MEMORY READ MACHINE CYCLE (EG: SECOND CYCLE OF MVI A, 32H)
ADDRESS OPCODE HERE TWO MACHINE CYCLES:
2000H MVI A, __ (3EH) √ First machine cycle is Opcode Fetch (4T-State).

√ Second machine cycle is Memory Read (3T-State).
2001H 32H
TIMING DIAGRAM FOR 2ND MACHINE CYCLE:
(20H)
(01H) (32H)
√ Reads a data byte in a memory location.
STEP1: √ OPCODE FETCH CYCLE ( Identical to previous example)

√ PC = 2000H+01H
STEP2: √ After completion of Op-Code fetch cycle:

l 01H --> AD0-AD7 bus by activating ALE.
√ PC = 2001H+01H
√ Status signals: IO/M = 0, S0=1, S1=0 for memory read operation.
STEP3: √ For T2 & T3, when RD =0 (Active Low):
l Memory places the data byte 32H on the data bus.

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EXAMPLE: COMPLETE INSTRUCTION CYCLE (MVI B, 43H)
ADDRESS OPCODE HERE TWO MACHINE CYCLES:

√ First Machine cycle is Opcode Fetch (4T-State).
2000H MVI B (06H)
√ Second Machine cycle is Memory Read (3T-State).
2001H 43H
* Here the Instruction moves immediate data (43H) to register B.

STEP1: √ Fetching the Opcode 06H from the memory 2000H.
STEP2: √ Read (move) the data 43H from memory 2001H.

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MEMORY WRITE MACHINE CYCLE (EG: LAST CYCLE OF STA 526AH)
ADDRESS OPCODE HERE FOUR MACHINE CYCLES:

41FFH STA (32H)
4200H 6AH √ Third Machine cycle is Memory Read (3T-State).
4201H 52H √ Fourth Machine cycle is Memory Write (3T-State).
TIMING DIAGRAM FOR FOURTH MACHINE CYCLE:
(52H)
(6AH) (C7H)
Let Accumulator
contains C7H.
√ Writes a data byte in a memory location.

STEP1: √ OPCODE FETCH CYCLE ( IR <- 32H)
√ MEMORY READ CYCLE (Reads a byte i.e. 6AH)
√ MEMORY READ CYCLE (Reads a byte i.e. 52H)
STEP2: √ After completion of Instruction fetch cycle :
l 6AH --> AD0-AD7 bus by activating ALE.
√ Status signals:IO/M = 0, S0=0, S1=1 for memory write operation.
STEP3: √ For T2 & T3, when WR =0 (Active Low):
l Contents of Accumulator are placed on Data bus

which are to be written into the Memory ([526A] <--A).

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EXAMPLE: COMPLETE INSTRUCTION CYCLE (STA 526AH)
ADDRESS OPCODE HERE FOUR MACHINE CYCLES:

41FFH STA (32H)
4200H 6AH √ Third Machine cycle is Memory Read (3T-State).
4201H 52H √ Fourth Machine cycle is Memory Write (3T-State).
* Here the Instruction stores the content of accumulator in to specified memory location, so
we need to fetch operation code as well as 16-bit memory address.
STEP1: √ Reads opcode by Opcode Fetch Machine Cycle.
STEP2: √ Reads lower byte of address by memory read cycle.
STEP3: √ Reads Higher byte of address by memory read cycle.
STEP4: √ Stores the content of accumulator into the memory location by
memory write cycle.

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EXAMPLE: COMPLETE INSTRUCTION CYCLE (IN C0H)
ADDRESS OPCODE HERE THREE MACHINE CYCLES:

4125H IN (DBH)
4126H COH √ Third Machine cycle is I/O Read (3T-State).
* Here the Instruction reads data to accumulator from port having address C0H.
STEP1: √ Fetching the Opcode DBH from the memory 4125H.
STEP2: √ Read the port address C0H from 4126H.
STEP3: √ Read the content of port C0H and send it to the accumulator.
l Let the content of port is 5EH.

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EXAMPLE: COMPLETE INSTRUCTION CYCLE (INR MH)
ADDRESS OPCODE HERE THREE MACHINE CYCLES:

4105H INR M (34H)
√ Third Machine cycle is Memory Write (3T-State).
* Here the Instruction increments the content of memory pointed by HL pair.

STEP1: √ Fetching the Opcode 34H from the memory 4105H
l Let the memory address (M) be 4250H, i.e. H=42, L=05H.
l Let the content of that memory is 12H

STEP2: √ Read data from memory 4250H.
STEP3: √ Increment the memory content from 12H to 13H and store at
same memory location.

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4.3 MEMORY DEVICE CLASSIFICATION AND HIERARCHY
MEMORY
PRIMERY MEMORY SECONDARY MEMORY
ROM RAM HDD

FDD
EPROM CDROM
EEPROM DVD
FLASH DRAM SRAM PENDRIVE
MASKED ROM MAGNETIC TAPE

PROM CCD
1) PRIMERY MEMORY:
Primary memory is computer memory that is accessed directly by the CPU. This
includes several types of memory, such as the processor cache and system ROM.
However, in most cases, primary memory refers to system RAM.
l ROM : √ ROM contains a permanent pattern of data that cannot be changed.

√ ROM is non-volatile; even after you turn off your computer, the
contents of ROM will remain.
i) Erasable PROM (EPROM): √ Can be erased by exposing ultra violet radiation.

√ Can be set a bit by using EPROM programmer.
ii) Electrically Erasable PROM(EEPROM):√Bit can be altered by electrical signal.

√ EEPROM chip is erased and reprogrammed in the
circuit of the computer itself.
iii) Flash: √ It is variation of EPROM.

√ EPROM can be erased in register level but flash memory must be
erased in its entirety or at block level.

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iii) Masked ROM: √ A bit pattern is permanently recorded by the manufactures
during production.
iii) Programmable ROM (PROM): √ Can be modified once by a user.

√ Can be program using a special machine
called a PROM programmer.
l R/W Memory (RAM) : √ Microprocessor can read and write frequently and randomly.
√ Random Access Memory is volatile (i.e. the content will be lost
if the power is turned off.)
√ When the computer is rebooted, the OS and other files are
reloaded into RAM, usually from an HDD or SSD.
i) Dynamic RAM (DRAM): √ Made up of MOS transistor gates and it stores bit as charge.
√ Comprised of 1 Transistor and 1 Capacitor.
√ Has high density, low power consumption.
√ The bit information leaks therefore needs to be rewritten
again every few milliseconds.
√ Slower due to extra refrashing circuit.
ii) Static RAM (SRAM): √ Made up of flip flops and it stores bit as voltage.
√ Each cell (Flip-flop) requires six transistors.
√ Has low density but high speed.
√ Expensive and consumes more power.
1) SECONDARY MEMORY:
Provide backup storage. It is nonvolatile memory.
i) Access time (Ta ): √ Average time required to read/write the unit of information.
√ Access rate (R a ) = 1/Ta
ii) Cycle time (Tc ): √ Average time that lapses between two successive read operation.
Cycle rate (R c )= bandwidth = 1/Ta
Access modes: Random access, Sequential access, Semi random-access.

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Memory Hierarchy:
√ There is a tradeoff between three characteristics:
l Cost
l Capacity: if greater application will get space to run smoothly.
l Access time: achieves a greater performance.
√ If capacity increases, access time increases (slower) and due to which

cost per bit decreases.
√ If access time decreases (faster), capacity decreases and due to which cost
per bit increases.
√ As we go down in the hierarchy:
l Cost per bit decreases
l Capacity of memory increases
l Access time increases
l Frequency of access of memory by processor also decreases.

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4.4 INTERFACING I/O AND MEMORY
8085 doesn’t have its internal memory or I/O buffers inside its chip, so we have to
interface it externally by external circuit.
1) ADDRESS DECODING: refers to the way a computer system decodes the addresses
on the address bus to select memory locations in one or more memory or peripheral
devices.
√ The 8085’s 16-bit address bus permits 64k words to be uniquely addressed.
√ Each cell (which contains data) in main memory has its own unique address.
√ Address decoding selects the required memory location for data read or write.
i) Unique/Full/Absolute Address Decoding:
√ each memory location or I/O port corresponds to a unique address
value on the address bus.
√ all the address lines on that mapping mode are used for address
decoding. ( i.e. 8 lines in I/O mapped, 16 lines in Memory mapped)
Here All 8-bit

lines are used
for selecting
I/O port
PORT ADDRESS= 01H
00000001 selects chip.

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i) Non-unique/Partial/Linear Select Address Decoding:
√ memory location or I/O port is addressed by fewer address lines.
√ all the address lines on that mapping mode are not used for address
decoding. (Though it is cheaper there may be a chance of address
conflict.)
Here only a least

significant bit
A 0 is used in for
selecting I/O port.
PORT ADDRESS= Any
address having last bit
0, selects the port.
I/O Mapped I/O :

√ a device is identified with an 8 bit address ( 2 8 devices can be identified uniquely.)
√ operated by I/O related functions IN and OUT.
√ Status Signal IO/M = 1.
√ Generally low order address bits A0-A7.
Memory mapped I/O :
√ a device is identified with an 16 bit address ( 2 16 devices can be identified uniquely.)

√ operated by I/O related functions STA , LDA.
√ Status Signal IO/M = 0.
√ chip select signal of each device is derived from 16 bit address lines.

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Q.N:01 Design an address decoding circuit for two RAM chips each of 256 bytes at
address starting from 5300H.
√ Required address bit for 256 bytes = ( 2 x=256 ), x = log (256)/log (2) = 8bit
MEMORY MAPPING
Block Address A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
1 Start 5300H 0 1 0 1 0 0 1 1 0 0 0 0 0 0 0 0
End 53FFH 0 1 0 1 0 0 1 1 1 1 1 1 1 1 1 1
2 Start 5400H 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0
End 54FFH 0 1 0 1 0 1 0 0 1 1 1 1 1 1 1 1
Same bits Unique bits 8-bit required

Decoder Select Chip Select Input address lines

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Q.N. Design a minimum system to interface the following specification:
1. 32kB of ROM using 2 x 16kB ROM IC
2. 32kB of RAM using 2 x 16kB RAM IC
√ Required address bit for 16kB = ( 2 x= 16x1024)

x = log (16384)/log (2) = 14bit
MEMORY MAPPING
1 Start 0000H 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
End 3FFFH 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 Start 4000H 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
End 7FFFH 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
3 Start 8000H 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
End BFFFH 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
4 Start C000H 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
End FFFFH 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Unique bits 14-bit required

Chip Select Input address lines
CS
ROM1
16 kB
RD
2*4
Decoder CS
ROM2
16 kB
RD
A15
DATA
A14
8085
Microprocessor CS
A13
.
. Address Bus (A13.......A0) RAM1
.
A. 0 16 kB
WR RD
WR
RD
IO/M CS
RAM2
16 kB
WR RD

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Q.N. Design a minimum system to interface the following specification:
i). 74LS138: 3 to 8 decoder
ii). 2732 (4k*8) EP-ROM address range should begin at 0000H and
additional 4k memory space should be available for future expansion.
iii). 6116 (2k*8) CMOS R/W Memory
√ Required address bit for 4 kB = 12-bit.
√ Required address bit for 2 kB = 11-bit.
MEMORY MAPPING
1 Start 0000H 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
End 0FFFH 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
2 Start 1000H 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
FOR FUTURE USE
End 1FFFH 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1
3 Start 2000H 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
End 27FFH 0 0 1 0 0 1 1 1 1 1 1 1 1 1 1 1
Unique bits 12-bit required

Chip Select Input address lines
EN
2732
EP-ROM
4 kB
EN
RD
74LS138
3*8
A15
DATA
A14
Decoder
A13
A12
8085
Microprocessor
A11 EN
A10
.
. Address Bus (A10.......A0) CMOS
A. 0 2 kB
WR RD
WR
RD
IO/M

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Q.N. Design a address decoding interface of an input port and output port for 8085 at
82H and 81H address.
EN
A7 OUTPUT
A6 BUFFER
A5
WR
A4
A3
A2
8085 A1
Microprocessor A0
EN
5V
INPUT
BUFFER
RD
5V
WR
RD
IO/M

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DATA TRANSMISSION INTERFACE
l Asynchronous
Transmission Format
l Synchronous
Modes of data transfer

l Parallel Data
l Serial Data
l I/O mapped I/O (IN/OUT)

Types of I/O
l Memory Mapped I/O (LDA, STA)
Microprocessor Controlled Device Controlled
DMA (With HOLD Signal)
Simple I/O (Wait) Simple Interrupt Pooling Handshaking

strobe I/O
Single Handshaking Double Handshaking
PARALLEL INTERFACE:
√ The device which can handle data at higher speed
√ N bits of data are handled simultaneously by the bus.
√ Expensive due to need of multiple wires.

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Synchronous : √ Reciever and Transmitter uses same clock pulse.
Asynchronous : √ Reciever and Transmitter uses different clock pulse.
MICROPROCESSOR CONTROLLED DATA TRANSFER
l Simple I/O, Unconditional data transfer :

√ Microprocessor assumes that the peripherals are always available.
√ Eg: LED are always connected to the input and output ports.
√ The devices are always ready to send or receive data.
l Wait Interface( Simple strobe I/O) :

√ Microprocessor need to wait until the device is ready for the operation.
√ Strobe signal indicates the time at which data is being activated to transmit.
√ Microprocessor should wait until peripheral asserts a active low strobe signal
l Single Handshaking :
√ Peripheral outputs data and send STB signal to MP. “Here is the data for you.”
√ MP detects asserted STB signal, reads the data and sends an acknowledge
signal (ACK) to indicate data has been read and peripheral can send next
data. “I got that one, send me another.”
√ MP sends or receives data when peripheral is ready.

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l Double Handshaking :
√ The peripheral asserts its STB line low to ask MP “Are you ready? ”
√ The MP raises its ACK line high to say “I’m ready”.
√ Peripheral then sends data and raises its STB line low to say “Here is some
valid data for you.”
√ MP then reads the data and drops its ACK line to say, “I have the data, thank
you, and I await your request to send the next byte of data.”
PROGRAMMABLE PERIPHERAL INTERFACE (PPI)-8255A

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√ 8255A is used to parallel data transfer between processor and slow peripheral devices
like ADC, DAC, keyboard.
√ The three ports are further grouped as follows:

l Group A consisting of port A and upper part of port C.
l Group B consisting of port B and lower part of port C.
√ The 8255 has three ports:

l Port-A (8-bit) - one 8-bit output latch/buffer and one 8-bit input buffer.
l Port-B (8-bit) - similar to PORT A.
l Port-C - Port-C upper (PC4-PC7) -4bit, Port-C lower (PC0-PC3)-4bit
√ The 8255 has Modes:

l Mode-0 ( Port-A, Port-B, Port-C upper, Port-C lower acts as simple I/O)
- Simple or basic I/O mode
- Outputs are latched but the inputs are not latched.
- Port A and B is used as two 8-bit ports and Port C as two 4-bit ports.
l Mode-1 ( Same as Mode 0 but Port C is used for handshaking and control)
- Port A and B is used as 8-bit either input or output ports.
- Each port uses three lines from port C as handshake signals.
- Inputs and outputs are latched.
l Mode-2 ( Port A is bidirectional (both I/O) and Port C is used for handshaking.)
- Port A can be configured as the bidirectional port.
- Port B either in Mode 0 or Mode 1
- Port A uses five signals from Port C as handshake signals for data transfer.
- Other signals from Port-C: either as simple I/O or as handshake for port B.
A0 A1 RD WR CS Input-Output Operation
0 0 0 1 0 PORT A --> Data bus
0 1 0 1 0 PORT B --> Data bus
1 0 0 1 0 PORT C --> Data bus
0 0 1 0 0 Data bus --> PORT A
0 1 1 0 0 Data bus --> PORT B
1 0 1 0 0 Data bus --> PORT C
1 1 1 0 0 Data bus --> Control Word Read

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SERIAL INTERFACE
√ Transmits data as a series of voltage pulses down a wire.

√ Data are transferred serially one bit at a time starting from Least Significant bit.
√ Slow due to single communication link but inexpensive to implement.
√ Its data bus has n data lines, the serial I/O interface accepts n bit of data
simultaneously
l Synchronous serial data transmission

√ Data is transmitted or received based on a clock signal i.e. synchronously.
√ The transmitting device sends a data bit at each clock pulse.
√ Usually one or more SYNC characters are used to indicate the start of each
synchronous data stream.
√ Transmitting device sends data continuously to the receiving device.
√ If the data is not ready to be transmitted, the transmitter will send SYNC
character until the data is available.
√ SYNC characters for each frame of data.

CHAPTER: 04
l Asynchronous serial data transmission
√ Receiving device does not need to be synchronized with transmitting device.
√ Transmitting device send data units when it is ready to send data.
√ Each data unit must contain:

- 1 start bit: beginning of data.
- 1 stop bit: End of data.
- 1 Parity bit: even or odd parity.
- 7 or 8 bit character: actual data transferred.
Parameter Asynchronous Synchronous
Transmission does not Transmission based on clock

Fundamental
based on clock signal. signal.
Group of characters i.e a block

Data Format One character at a time.
of characters
Speed Low (<20 kbps) High (>20 kbps)
Framing Start and stop bit are sent SYNC characters are sent with
Information with each character. each character.
Implementation Hardware / Software Hardware
Printer, Terminal, Modem,

Connections between com-
Uses home connections to the
puter and telephony networks.
Internet.

CHAPTER: 04
UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (USART) – 5251A
The 8251 is a USART (Universal Synchronous Asynchronous Receiver Transmitter) for

serial data communication. As a peripheral device of a microcomputer system, the 8251
receives parallel data from the CPU and transmits serial data after conversion. This device
also receives serial data from the outside and transmits parallel data to the CPU after
conversion.

CHAPTER: 04
The functional block diagram of 825 1A consists five sections:
l Read/Write control logic
l Transmitter
l Receiver
l Data bus buffer
l Modem control.
√ Read/Write control logic:

l Consist of three registers:
- Control register (Mode instruction, Command)
- Status register
- Data buffer.
l RD ,WR ,CS and C/D - for Read/Write operations with these three registers.
C/D =1 => Control register is selected.
C/D =0 => Data buffer is selected.
l RST - For idle mode of chip.
l CLK - Clock input for communication with CPU.
CS C/D RD WR Input-Output Operation

1 x x x Data bus tri-state
0 x 1 1 Data bus tri-state
0 1 0 1 Status --> CPU
0 1 1 0 CPU --> Control word
0 0 0 1 Data bus --> CPU
0 0 1 0 CPU --> Data bus
√ Transmitter section:
l Parallel data from CPU --> Serial data.
l RxD - Receives serial data from peripheral and buffered.
l Double buffered:
- Buffer register: Holds 8-bit parallel data from CPU.
- Output register: Holds converted serial data for transmission.
l TxRDY: If buffer register is empty.
l TxEMPTY: If output register is empty.
l TxC: Gives clock refrence for reciever.

CHAPTER: 04
√ Receiver Section:
l Accepts serial data --> parallel data.
l RxD - Receives serial data from peripheral and buffered.
l Double buffered:
- Input register: Receives and holds serial data.
- Buffer register: Holds the converted parallel data.
l RxRDY: Indicates input register loads a parallel data to buffer register.
l RxC: Inputs clock refrence form transmitter.
l SYNDET/BRKDET: - (Asynchronous mode) Indicates break in data transmission.
- (Synchronous mode) Indicate the reception of SYNC.
√ MODEM Control:
l Allows to interface a MODEM over telephone lines.
l This unit takes care of handshake signals for MODEM interface.
l DTR (Data Terminal Ready) - Tells USART is ready for transmit data to MODEM.
l DSR (Data Set Ready) - Input signal for MODEM condition (ready or not).
l RTS (Request to Send): requests the MODEM prepare to transmit data.
l CTS (Clear to Send): MODEM is ready to accept data from the DTE.
l Bit Rate is how many data bits are transmitted per second.
l A baud Rate is the number of times per second a signal in a communications
channel changes.
RS 232
√ Standard interface to transmit digital information across long distances.
√ Standardize interface between and data
l Data terminal equipment (DTE) - Computer (PC)
l Data communication equipment (DCE) - MODEM
√ Uses 25 pins (DB – 25P) or 9 Pins (DE – 9P) standards.
√ DTE connector - male / DCE connector - female.
√ Transmission capacity: 20KBd
√ Transmission distance 50 ft.
√ The voltage level for RS-232 (Reciever side) are:
l A logic high or 1 , -3V to -15V
l A logic low or 0, +3v to +15
√ For Transmitter: [ 1 => (-5V to -15V ), 1 => (-5V to -15V)]
√ Normally ±12V voltage levels are used.

CHAPTER: 04
PIN SIGNAL DESCRIPTION
3 TxD Transmitted data
2 RxD Received data
7 RTS Request to send
8 CTS Clear to send
6 DSR Data set ready
5 GND Signal ground
1 DCD Data carrer detect
4 DTR Data terminal ready
√ DTE asserts DTR to tell the modem it is ready.

√ Then DCE asserts DSR signal to the terminal and dials up.
√ DTE asserts RTS signal to the modem.
√ Modem then asserts DCD signal to indicate that it has established connection
with the computer.
√ DCE asserts CTS signals, then DTE sends serial data.
√ When sending completed, DTE asserts RTS high, this causes modem to unassert
its DSR signal and stop transmitting similar handshake taken between DCE
and DTE other side.

CHAPTER: 04
RS 423A
√ Improved data transmission capacity with longer distances than RS 232.
√ Voltage levels:
l High : (-4V to -6V)
l Low : (4V to 6V)
√ Single ended variable slew rate.
√ Cable length with RS423 is 1200 meter.
√ Transmission rate:
l 100 Kbd over 40 ft
l 1 Kbd over 4000 ft
RS 422A
√ A newer improved standard for serial data transfer.
√ Signal will be send differentially over a ribbon cable or a twisted pair of wires.
√ Uses differential amplifier to reject noise.
√ −6V to +6V (maximum differential Voltage)
l High : ( [B-A] > 0.4V => Negative Voltages)
l Low : ( [B-A] < 0.4V => Positive voltages)
√ Balanced data transmission.
√ These lines produce complementary (opposite) output signals.
√ Maximum Distance: 1500 metres (4,900 ft)
√ Transmission rate:
l 10000 KBd for 40 ft.
l 100 KBd for 4000 ft.
USB
√ Universal Serial Bus
√ Generations of USB :
l USB 1,x (Earlier, -Low Speed: 1.5 Mbit/s -Full Speed: 12 Mbit/s)
l USB 2,0 (Mini-A and Mini-B Connector, -Full Speed: 480 Mbit/s, OTG)
l USB 3,x (-SuperSpeed: 5 Gbit/s, -SuperSpeed+: 10-20 Gbit/s)
l USB4 (impending release)
√ Voltage level: l 5v +0.25v
-0.60v
√ Pins:
l 1: V BUS (+5 V) l 2: Data−
l 3: Data+ l 4: GND

CHAPTER: 04
DIRECT MEMORY ACCESS (DMA)
√ One of the system components connected to the system bus is given control of
the bus to perform direct read/write operation over main memory while the
microprocessor is temporarily disabled called direct memory access.
√ The external DMA controller sends a signal on HOLD pin to the microprocessor.
√ After the current bus cycle is completed the CPU will return a bus grant signal
and the component sending the request will become the master.
√ A DMA controller temporarily borrows the system bus from the microprocessor
and transfers the data bytes directly with high speed between an I/O port
and a series of memory locations.
√ Data is transferred between two peripherals directly without the involvement of
the microprocessor.
√ Once the DMA controller is done, it turns off the HOLD signal and the
microprocessor takes back control of the buses.
√ Taking control of the bus for a bus cycle is called cycle stealing.
√ Cycle stealing technique: In this scheme the bytes are divided into several parts
and after transferring every part the control of buses is given back to MPU and
later stolen back when MPU does not need it.
PROGRAMMABLE DMA CONTROLLER - INTEL 8257

CHAPTER: 04
It is a device to transfer the data directly between IO device and memory without the
involvement of the CPU. So it performs a high-speed data transfer between memory and
I/O device.
√ Four channels: it can be used to provide DMA to four I/O devices.
l Each channel can be independently programmable to transfer up to 64kb
of data by DMA.
l Each channel can be independently perform read transfer, write transfer
and verify transfer.
√ The functional blocks:

l Data bus buffer
l Read/write logic
l Control logic
l Priority resolver
l Four numbers of DMA channels.
√ Operation of 8257 DMA Controller:

l Each channel of 8257 has two programmable 16-bit registers address
register and 14-bit count register.
l Address register is used to store the starting address of memory location
for DMA data transfer.
l The address in the address register is automatically incremented after
every read/write/verify transfer.
l The count register is used to count the number of byte or word transferred
by DMA.
l In read transfer the data is transferred from memory to I/O device.
l In write transfer the data is transferred from I/O device to memory.
l Verification operations generate the DMA addresses without generating
the DMA memory and I/O control signals.
l The 8257 has two eight bit registers called mode set register and status
register.


Micro CH 04

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Microprocessor System - Microprocessor

1 Frequency and power supply signals

2 Externally or peripheral initiated signals

3 Multiplexed address/data bus

4 Higher order address bus

5 Control and status signals

baikunth2a@gmail.com 1 Compiled by: Baikuntha Acharya

a Power Supply and Clock frequency:

a Externally Initiated signals:

q TRAP (input): This is a non-maskable interrupt with highest priority.

q RESET IN : MPU gets reset, PC->0000H, resets the Interrupt Enable

baikunth2a@gmail.com 2 Compiled by: Baikuntha Acharya

a Control and status signals:

q Three status signals:

baikunth2a@gmail.com 3 Compiled by: Baikuntha Acharya

PIN DIAGRAM OF 8086 MICROPROCESSORS

OPERATES IN TWO MODES:

baikunth2a@gmail.com 4 Compiled by: Baikuntha Acharya

q M/IO - Used to differentiate between I/O and memory .

l HIGH- Memory operation. l LOW-I/O operation.

q INTA – Interrupt Acknowledge - Responces to peripheral that interrupt

has been accepted.

q ALE – Address Latch Enable: Latches the address into BUS.

q DT/R – Data Transmit/Receive – Direction of data flow through the

trans-receivers (bidirectional buffers).

q DEN – Data Enable: It is used to enable the trans-receivers (bidirectional

buffers) to separate the data from the multiplexed address/data signal.

q HOLD, HLDA - Hold Hold/Acknowledge - For requesting the bus access.

TIMING DIAGRAM: MINIMUM MODE

WRITE CYCLE TIMING DIAGRAM READ CYCLE TIMING DIAGRAM

baikunth2a@gmail.com 5 Compiled by: Baikuntha Acharya

q RQ/GT0 , RQ1/GT1 – Request/Grant - used for bus requests by other

S0 S1 S2 Operation S3 and S4: Shows which segment

TIMING DIAGRAM: MAXIMUM MODE

baikunth2a@gmail.com 6 Compiled by: Baikuntha Acharya

q AD15-AD0 - Multiplexed memory I/O address and data lines.

q A19/S6,A18/S5,A17/S4,A16/S3 - multiplexed address and status lines.

q RD – Read - Low signal performs memory or I/O read operation.

q READY - Acknowledgement from the slow device for data ready.

q INTR-Interrupt Request - For sending interrupt request.

q TEST - Exaimed by WAIT instruction.

l If TEST pin goes low, execution will continue,

l Else the processor remains in an idle state.

4.2 BUS STRUCTURE

l System bus = Data Bus + Control Bus + Address Bus

baikunth2a@gmail.com 7 Compiled by: Baikuntha Acharya

l MSYNC-Master synchronous signal

l SSYNC-Slave synchronous signal

baikunth2a@gmail.com 8 Compiled by: Baikuntha Acharya

Operation of microprocessor are:

l Op- Code fetch

l Memory Read /Write

l I/O Read/ Write

- Reading effective address.

- T states starts at the falling edge of a clock pulse.

Clock Frequency of 8085: 3.125 MHz

- Opcode fetch & execute(4T states)

baikunth2a@gmail.com 9 Compiled by: Baikuntha Acharya

Explanation of above Timing Diagram:

STEP1: √ PC --> Address Bus

l 20H -> A8-A15 Higher Order Address bus.

l 00H --> AD0-AD7 bus by Activating ALE.