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Arria 10 Product Table
Arria 10 Product Table
Arria 10 Product Table
Regional clocks 8 8 8 8 8 8 16 16 16 16 16
Architectural Features
Package Options3 and I/O Pins4: General-Purpose I/O (GPIO) Count, High-Voltage I/O Count, LVDS Pairs5, and Transceiver Count
240, 48, 96, 12 240, 48, 96, 12 240, 48, 96, 12 240, 48, 96, 12 – – – – – – –
F27 F672 pin (27 mm)
288, 48, 120, 12 288, 48, 120, 12 360, 48, 156, 12 360, 48, 156, 12 360, 48, 156, 12 – – – – – –
F29 F780 pin (29 mm)
– – 384, 48, 168, 24 384, 48, 168, 24 492, 48, 222, 24 492, 48, 222, 24 492, 48, 222, 24 504, 0, 252, 24 504, 0, 252, 24 – –
F34 F1152 pin (35 mm)
– – 384, 48, 168, 24 384, 48, 168, 24 396, 48, 174, 36 396, 48, 174, 36 396, 48, 174, 36 – – – –
F35 F1152 pin (35 mm)
– – – – – 588, 48, 270, 48 588, 48, 270, 48 600, 0, 300, 48 600, 0, 300, 48 – –
NF40 F1517 pin (40 mm)
Notes:
1. Fixed-point performance assumes the use of pre-adder. Numbers indicate GPIO count, high-voltage I/O count, LVDS pairs, and
192, 48, 72, 6
2. Certain packages might not bond out all PCIe hard IP blocks. transceiver count.
3. All packages are ball grid arrays with 1.0 mm pitch, except for U19 (U484), which is 0.8 mm pitch. Indicates pin migration.
4. A subset of pins for each package are used for 3.3 V and 2.5 V interfaces.
5. Each LVDS pair can be configured as either a differential input or a differential output.
6. All data is correct at the time of printing, and may be subject to change without prior notice. For the latest information, please visit www.altera.com.
Stratix 10 Product
intel Arria Table
10 Product Table
PRODUCT LINE SX 160 SX 220 SX 270 SX 320 SX 480 SX 570 SX 660
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in the U.S. and/or other countries. See Trademarks on intel.com for full list of Intel trademarks. *Other marks and brands may be claimed as the property of others. Gen-1010-2.1