Logic and Computer Design Fundamentals

Chapter 3 – Combinational
Logic Design
Part 1 – Implementation Technology and Logic
Design
Charles Kime & Thomas Kaminski
© 2004 Pearson Education, Inc.
Terms of Use
(Hyperlinks are active in View Show mode)
Overview
• Design Procedure
▪ The major design steps: specification, formulation, optimization,
technology mapping, and verification
• Technology Mapping
▪ From AND, OR, and NOT to other gate types
• Verification
▪ Does the designed circuit meet the specifications?

Chapter 3 - Part 1 2
 Combinational Circuits
▪ A combinational logic circuit has:
• A set of m Boolean inputs,
• A set of n Boolean outputs, and
• n switching functions, each mapping the 2m input
combinations to an output such that the current output
depends only on the current input values
▪ A block diagram:
Combinatorial
Logic
Circuit

m Boolean Inputs n Boolean Outputs

Chapter 3 - Part 1 3
 Hierarchical Design
▪ To control the complexity of the function mapping inputs to
outputs:
• Decompose the function into smaller pieces called blocks
• Decompose each block’s function into smaller blocks, repeating as
necessary until all blocks are small enough
• Any block not decomposed is called a primitive block
• The collection of all blocks including the decomposed ones is a
hierarchy
▪ Example: 9-input parity tree (see next slide)
• Top Level: 9 inputs, one output
• 2nd Level: Four 3-bit odd parity trees in two levels
• 3rd Level: Two 2-bit exclusive-OR functions
• Primitives: Four 2-input NAND gates
• Design requires 4 X 2 X 4 = 32 2-input NAND gates

Chapter 3 - Part 1 4
Hierarchy for Parity Tree Example
X0
X1
X2
X3 9-Input
X4 odd ZO
X5 function
X6 X0 A0
X7 3-Input
X8 X1 A1 odd B O
function
(a) Symbol for circuit X2 A2

X3 A0 A0
3-Input 3-Input
X4 A 1 odd B O A1 odd B
O ZO
function function
X5 A2 A2

X6 A0
3-Input
X7 A1 odd B O
function
X8 A2

(b) Circuit as interconnected 3-input odd

function blocks
A0
A1 BO

A2

(c) 3-input odd function circuit as

interconnected exclusive-OR
blocks

(d) Exclusive-OR block as interconnected

NANDs
Chapter 3 - Part 1 5
Design Procedure
1. Specification
• Write a specification for the circuit if one is not
already available
2. Formulation
• Derive a truth table or initial Boolean equations
that define the required relationships between the
inputs and outputs, if not in the specification
3. Optimization
• Apply 2-level and multiple-level optimization
• Draw a logic diagram or provide a netlist for the
resulting circuit using ANDs, ORs, and inverters

Chapter 3 - Part 1 6
Design Procedure
4. Technology Mapping
• Map the logic diagram or netlist to the
implementation technology selected
5. Verification
• Verify the correctness of the final design

Chapter 3 - Part 1 7
 Design Example
1. Specification
• BCD to Excess-3 code converter
• Transforms BCD code for the decimal digits to
Excess-3 code for the decimal digits
• BCD code words for digits 0 through 9: 4-bit
patterns 0000 to 1001, respectively
• Excess-3 code words for digits 0 through 9: 4-bit
patterns consisting of 3 (binary 0011) added to
each BCD code word
• Implementation:
▪ multiple-level circuit
▪ NAND gates (including inverters)
Chapter 3 - Part 1 8
 Design Example (continued)
2. Formulation
• Conversion of 4-bit codes can be most easily
formulated by a truth table
• Variables Input BCD Output Excess-3
- BCD: ABCD WXYZ
A,B,C,D 0000 0011
• Variables 0001 0100
0010 0101
- Excess-3 0011 0110
W,X,Y,Z 0100 0111
• Don’t Cares 0101 1000
0110 1001
- BCD 1010
0111 1010
to 1111 1000 1011
1001 1011
Chapter 3 - Part 1 9
Design Example (continued)
C C
3. Optimization z 1 1
y
1 1
0 1 3 2 0 1 3 2

a. 2-level using 1
4 5 7
1
6
1
4 5
1
7 6

K-maps X X X X B X X X X B
12 13 15 14 12 13 15 14

W = A + BC + BD A 1 X X A 1 X X
8 9 11 10 8 9 11 10

X = B C + B D + BC D D D
Y = CD + C D
Z=D x C C
w
1 1 1
0 1 3 2 0 1 3 2

1 1 1 1
4 5 7 6 4 5 7 6

X X X X B X X X X B
12 13 15 14 12 13 15 14

A 1 X X A 1 1 X X
8 9 11 10 8 9 11 10

D Chapter 3 - D
Part 1 10
Design Example (continued)
3. Optimization (continued)
b. Multiple-level using transformations
W = A + BC + BD
X = B C + B D + BCD
Y = CD + C D
Z=D G = 7 + 10 + 6 + 0 = 23
• Perform extraction, finding factor:
T1 = C + D
W = A + BT1
X = B T1 + BCD
Y = CD + C D
Z= D G = 2 + 1 + 4 + 7 + 6 + 0 = 19
Chapter 3 - Part 1 11
 Design Example (continued)
3. Optimization (continued)
b. Multiple-level using transformations
T1 = C + D
W = A + BT1
X = B T1 + B C D
Y = CD + C D
Z =D G = 19
• An additional extraction not shown in the text since it
uses a Boolean transformation: ( C D = C + D = T1 ):
W = A + BT1
X = B T1 + B T1
Y = CD + T1
Z= D G = 2 +1 + 4 + 6 + 4 + 0 = 16!
Chapter 3 - Part 1 12
 Design Example (continued)
4. Technology Mapping
• Mapping with a library containing inverters and 2-input
NAND, 2-input NOR, and 2-2 AOI gates
A A
W
W

B X
B

X
C

C Y
D D Y
Z

Z
Chapter 3 - Part 1 13
Technology Mapping
▪ Mapping Techniques
• NAND gates
• NOR gates

Chapter 3 - Part 1 14
 Example Cell Library
Typical
Typical Input-to- Basic
Cell Cell Normalized Input Output Function
Name Schematic Area Load Delay Templates

0.04
Inverter 1.00 1.00
1 0.012 3 SL

0.05
2NAND 1.25 1.00
1 0.014 3 SL

0.06
2NOR 1.25 1.00
1 0.018 3 SL

0.07
2-2 AOI 2.25 0.95
1 0.019 3 SL

Chapter 3 - Part 1 15
Mapping to NAND gates
▪ Assumptions:
• Cell library contains an inverter and n-input NAND
gates, n = 2, 3, …
• An AND, OR, inverter schematic for the circuit is
available
▪ The mapping is accomplished by:
• Replacing AND and OR symbols,
• Pushing inverters through circuit fan-out points,
and
• Canceling inverter pairs

Chapter 3 - Part 1 16
NAND Mapping Algorithm
1. Replace ANDs and ORs:
. .
. .
. .

. .
. .
. .

2.

. .
. .
. .

Chapter 3 - Part 1 17
NAND Mapping Example

Chapter 3 - Part 1 18
Mapping to NOR gates
▪ Assumptions:
• Cell library contains an inverter and n-input NOR
gates, n = 2, 3, …
• An AND, OR, inverter schematic for the circuit is
available
▪ The mapping is accomplished by:
• Replacing AND and OR symbols,
• Pushing inverters through circuit fan-out points,
and
• Canceling inverter pairs

Chapter 3 - Part 1 19
NOR Mapping Algorithm
1. Replace ANDs and ORs:
. .
. .
. .

. .
. .
. .

2.

. .
. .
. .

Chapter 3 - Part 1 20
 NOR Mapping Example

A A
B
B
2
X
F 1
C F
C
3
D
D
E
(a) A E
(b)
B

C
F

D
E
(c)

Chapter 3 - Part 1 21
Mapping Multiple Gate Types
▪ Algorithm is available in the Advanced Technology
Mapping reading supplement
▪ Cell library contains gates of more than one “type”
▪ Concept Set 1
• Steps
▪ Replace all AND and OR gates with optimum equivalent circuits
consisting only of 2-input NAND gates and inverters.
▪ Place two inverters in series in each line in the circuit containing
NO inverters
• Justification
▪ Breaks up the circuit into small standardize pieces to permit
maximum flexibility in the mapping process
▪ For the equivalent circuits, could use any simple gate set that can
implement AND, OR and NOT and all of the cells in the cell
library
Chapter 3 - Part 1 22
Mapping Multiple Gate Types
▪ Concept Set 2
• Fan-out free subcircuit - a circuit in which a single output cell
drives only one other cell
• Steps
▪ Use an algorithm that guarantees an optimum solution for
“fan-out free” subcircuits by replacing interconnected
inverters and 2-input NAND gates with cells from the library
▪ Perform inverter “canceling” and “pushing” as for the NAND
and NOR
• Justification
▪ Steps given optimize the total cost of the cells used within “fan-
out free” subcircuits of the circuit
▪ End result: An optimum mapping solution within the “fan-
out free subcircuits”
Chapter 3 - Part 1 23
Example: Mapping Multiple Cell Types
▪ Uses same example circuit as NAND mapping
and NOR mapping
▪ Cell library: 2-input and 3-input NAND gates,
2-input NOR gate, and inverter
▪ Circuits on next slide
(a) Optimized multiple-level circuit
(b) Circuit with AND and OR gates replaced with
circuits of 2-input NAND gates and inverters (Outlines
show 2-input NANDs and inverter sets mapped to
library cells in next step)
(c) Mapped circuit with inverter pairs cancelled
(d) Circuit with remaining inverters minimized
Chapter 3 - Part 1 24
Example: Mapping Multiple Gate Types
A A
B B

C F C F

D D
E E
(a) (b)

A
B
A
B

C C F
F

D D
E E
(c) (d)

Chapter 3 - Part 1 25
Verification
▪ Verification - show that the final circuit
designed implements the original specification
▪ Simple specifications are:
• truth tables
• Boolean equations
• HDL code
▪ If the above result from formulation and are
not the original specification, it is critical that
the formulation process be flawless for the
verification to be valid!

Chapter 3 - Part 1 26
Basic Verification Methods
▪ Manual Logic Analysis
• Find the truth table or Boolean equations for the final circuit
• Compare the final circuit truth table with the specified truth
table, or
• Show that the Boolean equations for the final circuit are equal
to the specified Boolean equations
▪ Simulation
• Simulate the final circuit (or its netlist, possibly written as an
HDL) and the specified truth table, equations, or HDL
description using test input values that fully validate
correctness.
• The obvious test for a combinational circuit is application of all
possible “care” input combinations from the specification

Chapter 3 - Part 1 27
Verification Example: Manual Analysis
▪ BCD-to-Excess 3 Code Converter
• Find the SOP Boolean equations from the final
circuit.
• Find the truth table from these equations
• Compare to the formulation truth table
▪ Finding the Boolean Equations:
T1 = C + D = C + D
W = A (T1 B) = A + B T1
X = (T1 B) (B C D) = B T1 + B C D
Y = C D + C D = CD + CD

Chapter 3 - Part 1 28
Verification Example: Manual Analysis
▪ Find the circuit truth table from the equations and compare
to specification truth table:
Input BCD Output Excess-3
AB C D WXYZ
0000 0011
0001 0100
0010 0101
0011 0110
0100 0111
0101 1000
0110 1001
0111 1010
1000 1011
1001 1011
The tables match! Chapter 3 - Part 1 29
Assignment # 3
Submission is due on Saturday till 00:00 AM through email

▪ Optimization:
▪ Find the optimized Boolean equation of BCD to 7-
segment decoder by using K-maps.
▪ Technology mapping:
▪ First design the circuit of BCD to 7-segment decoder
according to the optimized Boolean equations and then
design another circuit through NAND mapping

▪ Note: save your assignment file with your roll number and in email
subject write only Assignment #3 and your class with section

Chapter 3 - Part 1 30