Generic Array Logic (GAL)

 An innovation of the PAL was the generic array logic

device, or GAL, invented by Lattice Semiconductor Inc.

 This device has the same logical properties as the PAL

but can be erased and reprogrammed.

 The GAL is very useful in the prototyping stage of a

design, when any bugs in the logic can be corrected by
reprogramming.

 GALs are programmed and reprogrammed using a PAL

programmer.
 Summary
PALs and GALs
All PLDs contain arrays. Two important SPLDs are PALs
(Programmable Array Logic) and GALs (Generic Array
Logic). A typical array consists of a matrix of conductors
connected in rows and columns to AND gates.
A A B B
PALs have a one time
programmable (OTP)
array, in which fuses are
X
permanently blown,
creating the product
terms in an AND array.

Simplified AND-OR array

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
PALs and GALs
PALs are programmed with a specialized programmer that
blows selected internal fuse links. After blowing the fuses,
the array represents the Boolean logic expression for the
desired circuit. A A B B

What function is X

represented by the array?

X = AB + AB
The function represents an XOR gate.

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
PALs and GALs
The GAL (Generic Array Logic) is similar to a PAL but can
be reprogrammed. For this reason, they are useful for new
product development (prototyping) and for training purposes.
A A B B

GALs were developed by

Lattice Semiconductor.
They are high speed,
X
extremely fast devices
and can interface with
both 3.3 V or 5 V logic
signals.

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
PALs and GALs
PALs and GALs can be represented with a simplified
diagram. A single line can represent multiple gate inputs. The
logic shown is for the XOR gate, given previously.
Input buffer A A B B
Single line with slash
indicating multiple AND
gate inputs

Fuse blown

2 AB
X X
Fuse intact AB + AB

X X 2
AB

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
PALs and GALs
PALs and GALs have large array logic and include output
logic that varies in complexity. The output logic is connected
to each OR gate and together is referred to as a macrocell.
Two types of PAL/GAL macrocells are shown. For these
particular macrocells, the I/O pins can serve as an input or an
output. Tristate control

From From
AND I/O AND I/O
array array
To AND To AND
array array
Programmable fuse link to
control output polarity

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
PALs and GALs I1
7
Macrocell O1

The PAL16V8 is a typical I2 7

Macrocell I/O1
SPLD. There are 16 pins that I3
7
can be used as inputs and 8 Macrocell I/O2
I4
pins that can be used as 7
Macrocell I/O3
outputs. I/O pins are counted I5
Programmable
as both inputs and outputs. I6
AND array
7
Macrocell I/O4

I7 7
Macrocell I/O5
I8
7
Macrocell I/O6
I9
PLCC Package 7
I/O10
Macrocell O2

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 GAL CPLD

OLMC (Output Logic

MacroCell) has OR, FF,
output multiplexer and
I/O control logic.

Note that OLMC output is

fed back to input matrix
for use in other OLMCs.

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 GAL16V8 OLMC Structure
OE

CLK

11 T
10 S
01 M
00 U
vcc X

AC0

AC1(n)

P
O T
M O O
U M
1 X U I/O(n)
Q 1 X
FROM
AND
ARRAY D Q

XOR(n)

F 10-
M 11-
FEEDBACK U 0-1
X 0-0

FROM
ACO AC1(m) ADJ. STAGE
OUTPUT(m)
CLK AC1(n) OE

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved