Memory and Programmable Logic

Classifying Three Basic PLDs

Programmable
Connections
Fixed AND plane Programmable
INPUT (decoder) OR plane
OUTPUT

(Programmable) Read-Only Memory (ROM)

Programmable
Connections
Programmable Programmable
AND plane OR plane
INPUT OUTPUT

Programmable Logic Array (PLA)

Programmable Fixed F/F

INPUT AND plane OR plane
OUTPUT

Programmable Array Logic (PAL) Devices

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Memory

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 Some Basic Memory Definitions
• RAM = Random Access Memory
– SRAM (Static Random Access Memory)
• Dc powered – maintains data as long as power is ON
• Volatile
• High performance
• Expense
• Used for cache (L1 and L2) design
– DRAM (Dynamic Random Access Memory)
• Must be regenerated periodically (e.g. every 128 ms) or loses data
• Volatile
• Medium performance
• Cheap
• Used for main memory design
• Magnetic Storage (also called Virtual Memory)
• Partially serial access
• Non-volatile – maintains data when power is OFF
• Low performance
• Very cheap
• Used for disk drive and mass store devices
• There are two types of memories that are used in digital systems:

• Random-access memory(RAM): perform both the write and read

operations.

Read-only memory(ROM): perform only the read operation.

• The read-only memory is a programmable logic device. Other

such units are the programmable logic array(PLA), the
programmable array logic(PAL), and the field-programmable
gate array(FPGA).

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 Random-Access Memory
• A memory unit stores binary information in groups of bits called words.
1 byte = 8 bits
1 word = 2 bytes
• The communication between a memory and its environment is achieved
through data input and output lines, address selection lines, and control lines
that specify the direction of transfer.

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 Content of a memory
• Each word in memory is
assigned an identification
number, called an address,
starting from 0 up to 2k-1, where
k is the number of address lines.
• The number of words in a
memory with one of the letters
K=210, M=220, or G=230.
64K = 216 2M = 221
4G = 232

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 Write and Read operations
• Transferring a new word to be stored into
memory:
1. Apply the binary address of the desired word to
the address lines.
2. Apply the data bits that must be stored in
memory to the data input lines.
3. Activate the write input.
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 Write and Read operations
• Transferring a stored word out of memory:
1. Apply the binary address of the desired word to the address
lines.
2. Activate the read input.
• Commercial memory sometimes provide the two control inputs
for reading and writing in a somewhat different configuration in
table 7-1.

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 Types of memories
• In random-access memory, the word locations may
be thought of as being separated in space, with each
word occupying one particular location.
• In sequential-access memory, the information stored
in some medium is not immediately accessible, but is
available only certain intervals of time. A magnetic
disk or tape unit is of this type.

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• In a random-access memory, the access time is
always the same regardless of the particular
location of the word.
• In a sequential-access memory, the time it takes
to access a word depends on the position of the
word with respect to the reading head position;
therefore, the access time is variable.

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 Static RAM
• SRAM consists essentially of internal latches that store
the binary information.
• The stored information remains valid as long as power
is applied to the unit.
• SRAM is easier to use and has shorter read and write
cycles.
• Low density, low capacity, high cost, high speed, high
power consumption.
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 Dynamic RAM
• DRAM stores the binary information in the form of electric
charges on capacitors.
• The capacitors are provided inside the chip by MOS
transistors.
• The capacitors tends to discharge with time and must be
periodically recharged by refreshing the dynamic memory.

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 Dynamic RAM
• DRAM offers reduced power consumption and larger storage
capacity in a single memory chip.
• High density, high capacity, low cost, low speed, low power
consumption.

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 Types of memories
• Memory units that lose stored information when
power is turned off are said to be volatile.
• Both static and dynamic, are of this category since
the binary cells need external power to maintain
the stored information.
• Nonvolatile memory, such as magnetic disk, ROM,
retains its stored information after removal of
power.
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 Memory decoding
• The equivalent logic of a binary cell that stores one bit of
information is shown below.
Read/Write = 0, select = 1, input data to S-R latch
Read/Write = 1, select = 1, output data from S-R latch

SR latch with NOR gates

Ref. Figure 5-3 17
 4X4 RAM
• There is a need for decoding circuits
to select the memory word specified
by the input address.
• During the read operation, the four
bits of the selected word go through
OR gates to the output terminals.
• During the write operation, the data
available in the input lines are
transferred into the four binary cells
of the selected word.

A memory with 2k words of n bits per word requires k address lines that go into•
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kx2k decoder.
 Coincident decoding
address
• A decoder with k inputs and
2k outputs requires 2k AND
gates with k inputs per gate.
• Two decoding in a two-
dimensional selection scheme
can reduce the number of
inputs per gate.
• 1K-word memory, instead of
using a single 10X1024
decoder, we use two 5X32
decoders.
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 Address multiplexing

• DRAMs typically have four times the density of SRAM.

• The cost per bit of DRAM storage is three to four times less than
SRAM. Another factor is lower power requirement.

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 Block Diagram of Memory
N-bit Data Input
N (for Write)
K-bit address
lines Memory Unit
K
Read/Write 2k words
N-bit per word
Chip Enable
N N-bit Data Output
(for Read)
• Example: 2MB memory, byte-addressable
– N = 8 (because of byte-addressability)
– K = 21 (1 word = 8-bit)
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 Static Random Access Memory (SRAM)

Wordline (WL)

BitLine BitLine

• Typically each bit is implemented with 6 transistors (6T SRAM Cell)

• During read, the bitline and its inverse are precharged to Vdd (1) before
set WL=1
• During write, put the value on Bitline and its inverse on Bitline_bar before
set WL=1

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 Dynamic Random Access Memory (DRAM)

Wordline (WL)

Bitline

• 1-transistor DRAM cell

• During a write, put value on bitline and then set WL=1
• During a read, precharge bitline to Vdd (1) before assert WL to 1
• Storage decays, thus requires periodic refreshing (read-sense-write)

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 Memory Description
• Capacity of a memory is described as
– # addresses x Word size
– Examples:

Memory # of addr # of data lines # of addr lines # of total bytes

1M x 8 1,048,576 8 20 1 MB

2M x 4 2,097,152 4 21 1 MB

1K x 4 1024 4 10 512 B

4M x 32 4,194,304 32 22 16 MB

16K x 64 16,384 64 14 128 KB

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 How to Address Memory
4x8 Memory
2-to-4
0
Decoder 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit

A0 1
1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit

2
1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit
A1
3
1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit
CS

Chip D7 D6 D5 D4 D3 D2 D1 D0
Select

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 How to Address Memory
4x8 Memory
2-to-4
0
Decoder 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit
A0=1
1
1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit

2
1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit
A1=0
3
1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit
CS

Chip D7 D6 D5 D4 D3 D2 D1 D0
Select=1

Access address = 0x1

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 Use 2 Decoders
8x4 Memory
2-to-4
0
Decoder 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit

A1 1
Row
1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit
Decoder
2
1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit
A2
3
1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit
CS
Tristate
Buffer
(read)
D0
D1
D2
D3
Chip 0 1
Select CS 1-to-2 Decoder Column Decoder

A0 27
 Tristate Buffer
En

Input Output
Input Output

En

Vdd
• Similar to Transmission Gate

En • Could amplify signal (in

Input Output
contrast to a TG)
En
• Typically used for signal
traveling, e.g. bus
CMOS circuit
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Bi-directional Bus using Tri-state Buffer

Direction
(control data flow for read/write)

A Input/Output

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 Read/Write Memory
8x4 Memory
0
1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit

A1 2-to-4 1
Row 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit

Decoder 2
1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit
A2
3
1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit
CS
Rd/Wr = 0

D0
D1
D2
D3
0 1
Chip CS 1-to-2 Column Decoder
Select = 0
A0 30
 Read/Write Memory
8x4 Memory
0
1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit

A1 2-to-4 1
Row 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit

Decoder 2
1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit
A2
3
1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit
CS
Rd/Wr = 1

D0
D1
D2
D3
0 1
Chip CS 1-to-2 Column Decoder
Select = 1
A0 31
 Building Memory in Hierarchy
• Design a 1Mx8 using 1Mx4 memory chips
D7

D6
1Mx4
D5

D4
CS R/W

A19 A19 D3
A18 A18
A17 A17 D2
1Mx4
D1

A0 A0 D0
CS CS R/W

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 Building Memory in Hierarchy
• Design a 2Mx4 using 1Mx4 memory chips
A19 D3
Note that 1-to-2 A18
decoder is the wire A17 D2
itself (or use 1Mx4
an inverter) D1

D0
A0 CS R/W
1
A20 1-to-2
Decoder
0
A19
A18
CS A17
1Mx4

A0 CS R/W

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 Building Memory in Hierarchy
• Design a 2Mx8 using 1Mx4 memory chips
A19 A19 D7
A18 A18
A17 D6
A17 1Mx4
D5
A0 CS R/W D4
A0
A19 D3
1 A18
A20 1-to-2 A17 D2
Decoder 1Mx4
D1
0
A0 CS R/W D0

CS A19
A18
A17
1Mx4

A0 CS R/W

A19
A18
A17
1Mx4

A0 CS R/W
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 Memory Model
• 32-bit address space can address up to 4GB (232)
different memory locations

0x00000000 0x0A Lower

Memory
0x00000001 0xB6 Address

0x00000002 0x41

0x00000003 0xFC

Higher
Memory
0xFFFFFFFF 0x0D Address
Flat Memory Model
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 Read Only Memory (ROM)
• “Permanent” binary information is stored
• Non-volatile memory
– Power off does not erase information stored

K-bit address ROM

N-bit Data Output
lines 2k words
K N
N-bit per work

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 32x8 ROM

32x8 ROM
5 8
Each
represents
A4
0 32 wires
1
2
A3
5-to-32 3
A2
Decoder
A1
28
29
A0
30
31

Fuse can be
implemented as
a diode or a D7 D6 D5 D4 D3 D2 D1 D0
pass transistor
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Programming the 32x8 ROM
A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 0 1 1 0 0 0 1 0 1
0 0 0 0 1 1 0 0 0 1 0 1 1
0 0 0 1 0 1 0 1 1 0 0 0 0
… … … … … … … … … … … … …
1 1 1 0 1 0 0 0 1 0 0 0 0
1 1 1 1 0 0 1 0 1 0 1 1 0
1 1 1 1 1 1 1 1 0 0 0 0 1

0
A4 1
2
A3 5-to-32
A2
A1 Decoder
29
A0 30
31

D7 D6 D5 D4 D3 D2 D1 D0 38
 Example: Lookup Table
Design a square lookup table for F(X) = X2 using ROM •

X F(X)=X2 X (x2, x1, x0) F(X)=X2 (x5,x4,x3,x2, x1, x0)

0 0
1 1 000 000000
001 000001
2 4
010 000100
3 9
011 001001
4 16
100 010000
5 25
101 011001
6 36
110 100100
7 49
111 110001

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 Square Lookup Table using ROM

X F(X)=X2 1
X2 3-to-8 2
000 000000
3
001 000001 X1
Decoder 4
010 000100
X0 5
011 001001 6
100 010000 7
101 011001
110 100100
111 110001
F5 F4 F3 F2 F1 F0

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 Square Lookup Table using ROM

X F(X)=X2 1
X2 3-to-8 2
000 000000
3
001 000001 X1
Decoder 4
010 000100
X0 5
011 001001 6
100 010000 7
101 011001
110 100100
111 110001
F5 F4 F3 F2 F1 F0
Not Used = X0

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 Square Lookup Table using ROM

0
1
X F(X)=X2
X2 3-to-8 2
000 000000
3
001 000001
X1
Decoder 4
010 000100 X0 5
011 001001 6
100 010000 7

101 011001
110 100100
111 110001
F5 F4 F3 F2 F1 F0

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 Address multiplexing
• Address multiplexing will reduce the number of pins
in the IC package.
• In a two-dimensional array, the address is applied in
two parts at different times, with the row address
first and the column address second. Since the same
set of pins is used for both parts of the address, so
can decrease the size of package significantly.

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 Address multiplexing for 64K DRAM
• After a time equivalent to
the settling time of the row
selection, RAS goes back
to the 1 level.
• Registers are used to store
the addresses of the row
and column.
• CAS must go back to the 1
level before initialing
another memory operation.

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 Read-Only Memory
• A block diagram of a ROM is shown below. It consists of k
address inputs and n data outputs.
• The number of words in a ROM is determined from the fact
that k address input lines are needed to specify 2k words.

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 Construction of ROM
• Each output of the decoder represents a memory address.
• Each OR gate must be considered as having 32 inputs.
• A 2k X n ROM will have an internal k X 2k decoder and n OR
gates.

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 Truth table of ROM
• A programmable connection between to lines is logically
equivalent to a switch that can be altered to either be close
or open.
• Intersection between two lines is sometimes called a cross-
point.

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 Programming the ROM
In Table 7-3,0  no connection
1  connection
Address 3 = 10110010 is permanent storage using fuse link

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X : means connection
 Combinational circuit implementation

• The internal operation of a ROM can be interpreted in

two way: First, a memory unit that contains a fixed
pattern of stored words. Second, implements a
combinational circuit.
• Fig. 7-11 may be considered as a combinational circuit
with eight outputs, each being a function of the five input
variables.

A7(I4, I3, I2, I1, I0) = Σ(0,2,3…,29)

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 Example
Design a combinational circuit using a ROM. The circuit accepts a 3-bit •
number and generates an output binary number equal to the square of
the input number.
Derive truth table first

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 Example

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 Types of ROMs
The required paths in a ROM may be programmed in •
four different ways.
Mask programming: fabrication process .1
Read-only memory or PROM: blown fuse /fuse intact .2
Erasable PROM or EPROM: placed under a special .3
ultraviolet light for a given period of time will erase the
pattern in ROM.
Electrically-erasable PROM(EEPROM): erased with an .4
electrical signal instead of ultraviolet light.

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