Lecture 2: PLDs

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 Outline

 Introduction
 Multiplexers
 Three-State Buffers
 Decoders and Encoders
 Read-Only Memories
 Programmable Logic Devices
– Programmable Logic Arrays
– Programmable Array Logic
 Complex Programmable Logic Devices
 Field Programmable Gate Arrays
– Decomposition of Switching Functions
 VHDL Description of Combinational Circuits
 VHDL Models for Multiplexers
 VHDL Modules
 Signals and Constants
 Arrays
 VHDL Operators
 Packages and Libraries
 IEEE Standard Logic
 Compilation and Simulation of VHDL Code
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 Introduction

 We will transition from basic logic design to more complex

integrated circuits (ICs) in logic design.

 ICs are classified into:

– Small-scale integration (SSI): 1 - 4 gates, inverters and F/Fs
– Medium-scale integration (MSI): such as adders, multiplexers,
decoders, registers, and counters. Typically 12 – 100 gates
– Large-scale integration (LSI): typically contains 100 to few thousands
gates.
– Very-large-scale integration VLSI): typically contains several
thousands gates or more.

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 Multiplexers

 Multiplexers (MUX) has group of data inputs and a group of control

inputs. The control inputs select one of the data inputs and
connect it to the output.

Z = A’I0 + AI1 2n - 1

Z = A’B’I0 + A’BI1 + AB’I2 + ABI3 Z = Σ m k Ik

K=0

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 Three-State Buffers (1)

 Typically a gate is connected to a limited number of other gate

inputs unless using a buffer in between to increase the driving
capability of the gate output.
 3-state buffer permits the outputs of 2 or more gates to be
connected together:

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 Three-State Buffers (2)

 The following shows a three-state buffer and its logical

equivalent:
– B=1C=A
– B = 0  Hi-Z (open circuit)

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 Three-State Buffers (3)

 Truth table for 4-types of three-state buffers:

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 Three-State Buffers (4)

 Two three-state buffers can be tied together to function as a 2:1

multiplexer

D = B’A + BC

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 Decoders and Encoders (1)

 Decoder generates all minterms for all possible n-inputs.

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 Decoders and Encoders (2)

 Decoder logic diagram:

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 Decoders and Encoders (3)

 Encoder performs the inverse of a decoder. Example is the 8-3

priority encoder. (y0  y7  abc). If more than one input (y1, y4) is 1,
only the highest number will be encoded (y4). X in table means don’t
care. Output d is 1 if any input is 1, otherwise d is 0.

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 Read-Only Memories (1)

 ROM is an array of semiconductor devices that stores an array of

binary data.

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 Read-Only Memories (2)

 ROM is basically a decoder and a memory array. When a pattern of 0s

and 1s is applied as input, exactly one of the 2n decoder outputs is 1. This
active output will select one word from the memory array of words, and the
bit pattern in that word is made available to the memory output lines.

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 Programmable Logic Devices

 PLD is an IC that is programmable to provide a variety of

different logic functions. Several types of combinational PLDs
in additional to sequential PLDs.
 Simple combinational PLD is capable of realizing from 2 – 10
functions of 4 – 16 variables within one IC.
 More complex PLDs may contain thousands of F/Fs, gates, etc.
 PLDs facilitate easy way of changing digital circuit design with
lower cost.

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 Programmable Logic Organization

• Pre-fabricated building block of many AND/OR gates (or NOR,

NAND)
• "Personalized" by making or breaking connections among the
gates

Inputs

Dense array of Dense array of

AND gates Product OR gates
terms

Outputs

Programmable Array Block Diagram for Sum of Products Form

 Basic Programmable Logic Organizations

Depending on which of the AND/OR logic arrays is

programmable, there are three basic organizations

ORGANIZATION AND ARRAY OR ARRAY

PAL PROG. FIXED

PROM FIXED PROG.

PLA PROG. PROG.

 Array logic

 A typical programmable logic device may have hundreds to millions of

gates interconnected through hundreds to thousands of internal paths.
 In order to show the internal logic diagram in a concise form, it is
necessary to employ a special gate symbology applicable to array logic.

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 Programmable Logic Arrays (PLA)

 PLA is similar to ROM. PLA can have n-inputs (variables) and

m-outputs (functions).
 Internals of PLA is different from that of ROMs.

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 Programmable Logic Arrays (PLA)

 PLA with 3-inputs, 5 product terms, and 4 outputs (Equivalent AND-OR circuit)

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 Programmable Logic Arrays (PLA)

 Equivalent AND-OR circuit to the previous PLA:

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 PLA Logic Implementation
Key to Success: Shared Product Terms

Equations
F0 = A + B C
Example: F1 = A C + A B
F2 = B C + A B
F3 = B C + A

Personality Matrix
Input Side:
Product Inputs Outputs
term
1 = asserted in term
A B C F0 F 1 F 2 F 3 0 = negated in term
AB 1 1 - 0 1 1 0 - = does not participate
BC - 0 1 0 0 0 1 Reuse
0 1 0 0 of Output Side:
AC 1 - 0
tterms
BC - 0 0 1 0 1 0 1 = term connected to output
A 1 - - 1 0 0 1 0 = no connection to output
 PLA Logic Implementation
Example Continued - Unprogrammed device
A B C
All possible connections are available
before programming

F0 F1 F2 F3
 PLA Logic Implementation
Example Continued - A B C
Programmed part Unwanted connections are "blown"

AB

BC

AC

BC

Note: some array structures

work by making connections
rather than breaking them
F0 F1 F2 F3
 Programmable Logic Array (PLA)

A Programmable
OR Plane
B

Programmable
AND Plane

C C B B A A

F1 F2
 Example using PLA
F1(A, B, C)   m(0,1,2,4)
F2(A, B, C)   m(0,5,6,7)

F1  A B  AC  BC
F1  AB  AC  BC

F2  AB  AC  A BC
 Example using PLA
A F1  AB  AC  BC
B F2  AB  AC  A BC
C
AB

AC

BC

ABC

C C B B A A

F1
F2
 PLA Logic Implementation
Alternative representation Unprogrammed device

Short-hand notation
so we don't have to
draw all the wires!

X at junction indicates A B C D
a connection
AB

AB

CD
Notation for implementing
CD
F0 = A B + A B
Programmed device
F1 = C D + C D

AB+AB CD+CD
 PLA Logic Implementation
A B C
Design Example
ABC

Multiple functions of A, B, C A

B
F1 = A B C C

A
F2 = A + B + C
B
F3 = A B C C
ABC
F4 = A + B + C
ABC

F5 = A  B  C ABC

ABC
F6 = A  B  C ABC

ABC

ABC

F1 F2 F3 F4 F5 F6
 PALs and PLAs
What is difference between Programmable Array Logic (PAL) and
Programmable Logic Array (PLA)?

PAL concept — implemented by Monolithic Memories

AND array is programmable, OR array is fixed at fabrication

A given column of the OR array

has access to only a subset of
the possible product terms

PLA concept — Both AND and OR arrays are programmable

• Programmable logic array (PLA)
– has an array of inverters, AND gates and OR
gates
– can implement any logic function (given limits
on numbers of inputs and outputs)
Example: consider a system with four inputs
A, B, C and D and three output X, Y and Z,
where
X  A B C D+A B CD
Y  A B CD  ABCD
Z  A B C D  A B CD  ABCD
The structure of a simple PLA
The PLA programmed to give the required
output functions
 Digital Logic

Digital Logic Function Product AND (&)

Sum OR (|)

3 Inputs

SUM of PRODUCTS
Black Box Truth Table
(Look Up Table LUT)

The Design Warrior’s Guide to FPGAs

21/04/1438 PLDs: Lecture2 34
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
 Digital Logic

Digital Logic Function Product AND (&)

Sum OR (|)

3 Inputs

SUM of PRODUCTS
Black Box Truth Table
(Look Up Table LUT)

The Design Warrior’s Guide to FPGAs

21/04/1438 PLDs: Lecture2 35
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
 Digital Logic

Digital Logic Function Product AND (&)

Sum OR (|)

3 Inputs

SUM of PRODUCTS
Black Box Truth Table
(Look Up Table LUT)

The Design Warrior’s Guide to FPGAs

21/04/1438 PLDs: Lecture2 36
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
 Programmable Logic Devices
PLDs Inputs

ANDs Un-programmed State

 SUM of PRODUCTS Planes of

ANDs, ORs
 (Re-)Programmble Links
ORs
 Reconfigurable
Outputs
 GLUE LOGIC
Logic Functions

The Design Warrior’s Guide to FPGAs

21/04/1438 PLDs: Lecture2 37
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
 Programmable Logic Devices
PLDs Inputs

ANDs Un-programmed State

 SUM of PRODUCTS Planes of

ANDs, ORs
 (Re-)Programmble Links
ORs
 Reconfigurable
Outputs
 GLUE LOGIC
Logic Functions

The Design Warrior’s Guide to FPGAs

21/04/1438 PLDs: Lecture2 38
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
 Programmable Logic Devices
PLDs Inputs

ANDs Un-programmed State

 SUM of PRODUCTS Planes of

ANDs, ORs
 (Re-)Programmble Links
ORs
 Reconfigurable
Outputs
 GLUE LOGIC
Logic Functions

The Design Warrior’s Guide to FPGAs

21/04/1438 PLDs: Lecture2 39
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
 Programmable Logic Devices
PLDs Inputs

ANDs Un-programmed State

 SUM of PRODUCTS Planes of

ANDs, ORs
 (Re-)Programmble Links
ORs
 Reconfigurable
Outputs
 GLUE LOGIC
Logic Functions

Sums

Programmed PLD
Product Terms

The Design Warrior’s Guide to FPGAs

21/04/1438 PLDs: Lecture2 40
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
 Programmable Logic Devices
PLDs
Logic Functions

Programmed PLD

Sums

Product Terms

The Design Warrior’s Guide to FPGAs

21/04/1438 PLDs: Lecture2 41
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
 Programmable Logic Devices
PLDs
Logic Functions

x x x
Programmed PLD

x x
Sums

Product Terms

The Design Warrior’s Guide to FPGAs

21/04/1438 PLDs: Lecture2 42
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
 Programmable Logic Devices
PLDs
Logic Functions

 GLUE LOGIC

x x x x
Programmed PLD

x x x
Sums

Product Terms

The Design Warrior’s Guide to FPGAs

21/04/1438 PLDs: Lecture2 43
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
 PALs and PLAs
• Of the two organizations the PLA is the most flexible
– One PLA can implement a huge range of logic functions

– BUT many pins; large package, higher cost

• PALs are more restricted / you trade number of OR

terms versus number of outputs
– Many device variations needed

– Each device is cheaper than a PLA

 Programmable Array Logic (PAL)
• PAL is a special kind of PLA in which the AND array is
programmable and the OR array is fixed.
• PAL is less expensive than the general purpose PLA, and PAL is
easier to program as well.

Unprogrammed Segment in PAL

Programmed Segment in PAL

 Programmable Array Logic (PAL)
• Realize the function: F = I1I2’ + I1’I2
 PAL Logic Implementation
Design Example: BCD to Gray Code Converter K-maps
Truth Table AB
A
AB
A

A B C D W X Y Z CD 00 01 11 10 CD 00 01 11 10
0 0 0 0 0 0 0 0 00 0 0 X 1 00 0 1 X 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1 01 0 1 X 1 01 0 1 X 0
0 0 1 1 0 0 1 0 D D
0 1 0 0 0 1 1 0 11 0 1 X X 11 0 0 X X
0 1 0 1 1 1 1 0 C C
0 1 1 0 1 0 1 0 10 0 1 X X 10 0 0 X X
0 1 1 1 1 0 1 1
1 0 0 0 1 0 0 1 B B
1 0 0 1 1 0 0 0 K-map for W K-map for X
1 0 1 0 X X X X
1 0 1 1 X X X X
A A
1 1 0 0 X X X X AB AB
1 1 0 1 X X X X CD 00 01 11 10 CD 00 01 11 10
1 1 1 0 X X X X 00 0 1 X 0 00 0 0 X 1
1 1 1 1 X X X X
01 0 1 X 0 01 1 0 X 0
Minimized Functions: D D
11 1 1 X X 11 0 1 X X
C C
W=A+BD+BC 10 1 1 X X 10 1 0 X X
X=BC
Y=B+C B B
Z=ABCD+BCD+AD+BCD K-map for Y K-map for Z
 PAL Device Design Example
A A B B C C D D IO1 IO1

IO1

Not programmed
A

IO2

B
IO1  ABC  A BC D

IO2  ABC  A BC D  A C D  A BCD

 AND gates inputs
Programmable Array Logic 0 1 2 3 4 5 6 7 8 9
X
Product 1

Example term

2
X X
F1

I 1= A
• 4-input, 3-output PAL with 4
X X X

fixed, 3-input OR terms 5

X X
F2

• What are the equations for 6

X X

F1 through F4? I2 = B
F1 = C’ + A’B’ 7
X X

F2 = A’BC’ + AC + AB’ X X F3
8
F3 = AD + BD + F1 X
9
F4 = AB + CD + F1’ I3 = C
X X
10

X X
11 F4

X
12

I4 = D
0 1 2 3 4 5 6 7 8 9
PAL - Programmable Array Logic

PLA have higher programmability than PAL, however they have

lower speed than PAL

Solution  PAL for higher speed.

Programmable AND, Fixed OR

PAL - Simpler to manufacture, cheaper than PLA and have better

performance

50
Flip-flops store the value produced by the OR gate output at a particular
point and can hold it indefinitely.

Flip-flop output is controlled by the clock signal. On 0-1 transition of

clock, flip-flop stores the value at its D input and latches the value at Q
output.

2-to-1 multiplexer selects an output from the OR gate output or the flip-flop
output. Tri-state buffers are placed between multiplexer and the PAL output.

Multiplexer’s output is fed back to the AND plane in PAL, which allows the
multiplexer signal to be used internally in the PAL. This facilitates the
implementation of circuits that have multiple stages (levels or logic gates).
51
 Select Enable

f1
Flip-flop
D Q

Clock

To AND plane

For additional flexibility, extra circuitry is added at the output of each OR gate.
This is also referred to macrocell.

52
 Example: FSM Implementation

S2 = P’ Q y1, R2 = y2,
S1 = P’ Q’ , R1 = Q + P
Z= y2 y1’ P Q’ ,

P & Q – are inputs

y2 & y1 are the states
Z is the output

53
Internal Structures of PLD
A B
2-to-4 decoder

AND array
A A B B AB
AB

AB AB

Product
AB lines
AB

AB AB

If blown, OR
Fuse input is logic 0.
Input lines OR
array

O1 O2 O3 O4

Sum of product outputs

Example of a programmable logic device
Programmable Array Logic (PAL)
D C B A
OR array
(hard-wired)

0
1

2
3
4
5

6
7
8
9

10
11

12
13
14

15

AND array O1 O2 O3 O4
(programmable)
 PAL
• Programmable Array Logic (PAL)
– The input lines to the AND array are programmable
and the output lines to the OR array are hard-wired
– Simplify the logic function (e.g. using K-map) before
putting design into PLA.
K-maps
 PLA Logic Implementation
Another Example: Magnitude Comparator A B C D

A A ABCD
AB AB
CD 00 01 11 10 CD 00 01 11 10
ABCD
00 1 0 0 0 00 0 1 1 1
ABCD
01 0 1 0 0 01 1 0 1 1
D D ABCD
11 0 0 1 0 11 1 1 0 1
C C AC
10 0 0 0 1 10 1 1 1 0
AC
B B
BD
K-map for EQ K-map for NE
BD
A A
AB AB
00 01 11 10 00 01 11 10
ABD
CD CD
00 0 0 0 0 00 0 1 1 1 BCD

01 1 0 0 0 01 0 0 1 1 ABC
D D
BCD
11 1 1 0 1 11 0 0 0 0
C C
10 1 1 0 0 10 0 0 1 0

B B
EQ NE LT GT
K-map for LT K-map for GT
 PAL
D C B A
OR array
(hard-wired)

0 AB

1 CD

2 0

3 ABC
4 0
5 0

6 0

7 ABCD

8 ABCD
9 0

10 0
11 A
12 BD

13 CD

14 0

15 0

AND array
(programmable) O1 O2 O3 O4
 PAL Logic Implementation
Programmed PAL: A B C D

A
BD
BC
Minimized Functions:
0
W=A+BD+BC BC
X=BC 0
Y=B+C 0
Z=ABCD+BCD+AD+BCD 0
B
C
0
0
ABCD
BCD
AD
BCD

4 product terms per each OR gate

W X Y Z
 PAL Logic Implementation
Code Converter Discrete Gate Implementation
A A
A 1
B 4
C
B D
2 3 W
D
B
C 3
B 2
C D
D 4 Z
D 1
5
A
B
2 1 X B
C 1
C 3
D
C
1: 7404 hex inverters
B 2 Y 2,5: 7400 quad 2-input NAND
B 1 3: 7410 tri 3-input NAND
4: 7420 dual 4-input NAND

4 SSI Packages vs. 1 PLA/PAL Package!

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