DEPARTMENT OF ELECTRICAL & ELECTRONIC ENGINEERING

BANGLADESH UNIVERSITY OF ENGINEERING & TECHNOLOGY

COURSE NO.: EEE 208
EXPT. NO. 05

Name of the Experiment: DC Characteristics of an Enhancement MOSFET

Objective

1. To measure some of the important characteristics of the MOSFET

2. Construct a set of characteristic curves for the MOSFET

Equipments Required

1. N-channel enhancement MOSFET 1 piece

2. DC ammeter I unit
3. DC voltmeter 1 unit
5. Regulated power supply 1 unit
6. Resistor lOOk, lOOk Pot, 5600 1 piece each
7. Bread Board One

Theory

The n-channel MOSFET Metal-Oxide consists of a Field Effect Transistor p-type

substrate into which two n+ regions are diffused, as shown in Fig. 1. These n+ sections
act as the source and the drain.

G
S ate D
ource Met I am

n+ eee
e
8 8 88 •
~eeeeEfj3 P-substrate eeeeee
Fig. I
B(Body)

, The metal area of the gate, in conjunction with the insulating dielectric oxide layer and
the semiconductor channel, forms a parallel-plate capacitor. The insulating layer of
silicon dioxide is the reason why this device is called the Metal Oxide-field effect
Transistor. The in layer results in an extremely high input resistance( I 010 to 10150)
for the MOSFET.

When V GS?..Y T, the transistor is ON. Now dependent on the value of drain voltage V DS,
MOSFET either operates in triode or saturation region.

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For triode region
(V GS-V DS)~V T and
_ W
1)) = V"C"(-)[(VGS -VT)Vvs
I
--V 2
f)s]
L 2
Saturation region (VGS-V DS):::::VT
W 2
If) = V"C" (-)(VGS
L
- VT) (I + AVOS)

where ,,-=_1_ and VA is the Early voltage, Un is the electron mobility (cm2/V.s),
VA
Co is the oxide capacitance per unit, W is the width of the gate andL is the Channel
length.
The Enhancement MOSFET

If we ground the substrate for the structure of Fig. 1 and apply a positive voltage at the
gate, an electric field will be directed perpendicularly through the oxide. This field will
end on "induced" negative charges on the semiconductor site, as shown in Fig. I.First
the negative charge of electrons which are minority carriers in the p-type substrate
forms an "inversion layer". As the positive voltage on the gate increases, the induced
negative charge voltage, electrons will pile up in a thin region beneath the Si02- Si
inter face and electron density will be exceed than droping density NA.when the
electron density at the inter face, ns, is equal to NA, the corresponding gate voltage is
known as threshold voltage VT• A depletion region consisting of immobile acceptor
ions will be formed. At relatively large gate voltage Va an inversion layer will be
created near the SiorSi inter face.

Circuit Diagram
RG1
lOOK Ro
560n

Rm
lOOK
Pot +
Voo

VGS S

GND

Fig. 2
Procedures

1. Connect the circuit as shown in Fig. 2. Set VGGto 15V. Regulate the
potentiometer so that the gate to source voltage VGSis OV.

2. For different values ofVoo measure the drain to source voltage Vos and the
drain current ID. Also measure the voltage across 560n resistor. Take the
readings upto for VDs=5V.

3. Set the gate voltage VGs=3V. Repeat step 2 for this setup.

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 4. Similarly for VGs=5V. Repeat step 2 for each case and take the readings.

-Reports

1.(a) Plot the drain characteristics curves i.e. 10, Vs, Vos for VGs=O,3 and 5V

(b) Determine V A for the plot.

2. Determine thr~shold voltage using experimental data, AssumeA,=O.

Reference: Microelectronic Circuits, Sedra/Smith

Updated by: Yeasir Ararat on 7'h February, 2006

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