DLD Lab Handouts

Safety Measures
PREVENT ACCIDENTS: FOLLOW THIS ADVICE

1. Never hurry. Work deliberately and carefully.
2. Connect to the power source LAST.
3. If you are working with a lab kit that has internal power supplies, turn the main
power switch OFF before you begin work on the circuits. Wait a few seconds for
power supply capacitors to discharge. These steps will also help prevent damage to
circuits.
4. If you are working with a circuit that is connected to an external power supply, turn
the power switch of the external supply OFF before you begin work on the circuit.
5. Check the circuit, power supply voltages for proper value and for type (DC, AC,
frequency) before energizing the circuit.
6. Do not run wires over moving or rotating equipment, or on the floor, or string them
across walkways from bench-to-bench.
7. When using large electrolytic capacitors be sure to wait long enough (approximately
five-time constants) for the capacitors to discharge before working on the circuit.
8. All conducting surfaces intended to be at ground potential should be connected

together.
BASIC ELECTRICAL SAFETY PRACTICES

The Institute requires everyone who uses electrical equipment to understand these
safety precautions.
Safe Work Practices
9. Do not remove the protective cover of an equipment to replace a part, adjust or
troubleshoot. Ask a qualified person to do the work
10. Do not use an electrical outlet or switch if the protective cover is ajar, cracked or
missing.
11. Only use DRY hands and tools and stand on a DRY surface when using electrical
equipment, plugging in an electric cord, etc.
12. Never put conductive metal objects into energized equipment.
13. Always pick up and carry portable equipment by the handle and/or base. Carrying
equipment by the cord damages the cord's insulation.
14. Unplug cords from electrical outlets by pulling on the plug instead of pulling on the
cord.
15. Use extension cords temporarily. The cord should be appropriately rated for the job.
16. Use extension cords with 3 prong plugs to ensure that equipment is grounded.
17. Never remove the grounding post from a 3 prong plug so you can plug it into a 2
prong, wall outlet or extension cord.
18. Re-route electrical cords or extension cords so they are not run across the floor,
under rugs or through doorways, etc. Stepping on, pinching or rolling over a cord will
break down the insulation and will create shock and fire hazards.
19. Do not overload extension cords, multi-outlet strips and wall outlets.
20. Heed the warning signs, barricades and/or guards that are posted when equipment
or wiring is being repaired or installed or if electrical components are exposed.
2
Check for Unsafe Conditions (either before or while you're using equipment)
21. Is the cord's insulation frayed, cracked or damaged, exposing the internal wiring?
22. Are the plug's prongs bent, broken or missing, especially the third prong?
23. Is the plug or outlet blackened by arcing?
24. Was liquid spilled on or around the equipment?
25. Are any protective parts (or covers) broken, cracked or missing?
26. Do you feel a slight shock when you use the equipment?
27. Does the equipment or the cord overheat when it is running?
28. Does the equipment spark when it is plugged in or when switches or controls are
used?
If you observe any of these unsafe conditions:

29. Do not use (or stop using) the equipment.
30. Immediately report the problem to the Lab Instructor or person In-charge of the lab.
I have read and understood the safety practices. I will observe and follow the safety
practices and perform lab experiments without compromising my or others safety.
Name: __________________________________________
Signature: __________________ Date: ______________
3
LAB 1
Introduction to ePAL trainer, Logic Works Software and basic
logic ICs
Group Number
Student Name Registration Number
Submitted by
EEE241 Digital Logic Design Lab Manual

By Engr. Shahab Yousafzai
Rubrics for CLO#1 (PLO#1: Basic Engineering Knowledge) Marks
Mathematical and Scientific

Terms:
Knowledge Base for
Engineering
Mathematical Models:
Obtained Marks
4
INTRODUCTION
Binary logic consists of binary variables and logical operations. The variables are
designated by letters of the alphabet such as A, B, C, x, y, z, etc., with each variable
having two and only two distinct possible values: 1 and 0. There are three basic logical
operations: AND, OR, and NOT.
1. AND: This operation is represented by a dot or by the absence of an operator. For

example, x.y= z or xy = z is read "x AND y is equal to z." The logical operation AND is
interpreted to, mean that z = 1 if and only if x = 1 and y = 1; otherwise z = 0.
(Remember thatx, y, and z are binary variables and can be equal either to 1 or 0, and
nothing else.)
31.OR: This operation is represented by a plus sign. For example, x + y = z is read "x OR
y” is equal to z," meaning that z = 1 if x = 1 or if y = 1 or if both x = 1 and y = 1. If both
x and y = 0,then z = 0.
32.NOT: This operation is represented by a prime (sometimes by a bar). For example, x'
= z meaning that z is what x is not. In other words, if x = 1, then z = 0; but if x = 0,
then z = 1. Similarly x’ = 1(is read "not x is equal to 1") implies that x=0.
Binary logic resembles binary arithmetic, and the operations AND and OR have some
similarities to multiplication and addition, respectively. In fact, the symbols used for
AND and OR are the same as those used for multiplication and addition. However,
binary logic should not be confused with binary arithmetic. One should realize that an
arithmetic variable designates a number that may consist of many digits. A logic variable
is always either a ONE or a ZERO. For example, in binary arithmetic, we have 1 + 1 = 10
(read: "one plus one is equal to2"), whereas in binary logic, we have 1 + 1= 1 (read: “one
OR one is equal to one”).
For each combination of the values of x and y, there a value of z specified by the
definition of the logical operation. This definition may be listed in a compact form using
5
truth tables. A truth table is a table of all possible combinations of the variables showing
relation between the values that the variables may take and the result of the operation.
6
Objective:
1. To become familiar with the components of the trainer board used in the digital
experiments
33.To become familiar with the different types of Integrated Circuits (ICs), their use and
pin number reading.
34.To become familiar with logic works software for simulation of digital circuits.
Equipment Required:
1. EPAL 27
35.Logic works software
36.Digital ICs
Introduction to EPAL:
Safety and Handling Issues
It is utmost recommended that you must clean and dry up your hands before you start
working on ePAL. This can avoid depositing, hand carrier materials between contacts
and therefore avoid short circuiting. Although ePAL has been fused properly for all
power supply levels and easily replaceable but you must avoid falling naked patching
wires or conducting materials on ePAL.
Before you power up the ePAL

All the slide switches on ePAL are in OFF state when they are pushed down and ON
otherwise. Turn the power supply slide switches to OFF position and insert the external
power supply male jack in the female power jack on ePAL. Then turns the power supply
switches in ON state.
7
Key Functional Blocks of EPAL:
I. Power Supply
The power supply specifications are
- PIN3 +5V ---- 5A
- PIN5 +15V ---- 2A
- PIN4 -15V ---- 0.8A
- PIN1, 2 COMMON GND
The power supply voltages are available on the left half of ePAL on headers as shown in
figure 8 from where it can be extended through jumper wire to any desired circuit. We
will be using +5V in most of our experiments.
ePAL is provided with a variable power supply ranging from 0 to ±15V. The output for
the variable power supply is provided both on interface header and Molex connector.
Figure 1.2 shows the location of variable supply knobs and interface headers.
II. Fuses
ePAL is protected with fuses for +15V, -15V and +5V which are easily replaceable. None
of the fuses allows passing more than 250mA of current.
III. Function Generator

The function generator consists of a function generator IC (XR2206CP), slide switches,
knobs and RVs. All the knobs on the function generator panel increments the value in
clock wise direction and the slide switches activate when they are pushed up.
8
The fine frequency tuning is the only knob in the function generator which increments in
anti-clockwise direction and vice versa. Sinusoidal, square and triangular waveforms
within variable frequency range of 0.1 Hz to 300 kHz variable.
IV. Seven Segment Display

Two 7-segment displays with BCD input sockets are provided on the trainer board.
When binary inputs are provided at the input sockets below each display, the decimal
equivalent of the BCD input is displayed.
V. Logic Probe
Logic probe, with two LEDs, has been made available to monitor logic levels in any
circuit. The probe can be connected to any point on the circuit under test and either one
of the two LEDs will glow to indicate the status. If Red LED glow, the point under test is
at high logic and if Green LED glows, the point is at low logic.
VI. Breadboard
Breadboard for patching digital circuits is provided on the trainer board. As each circuit
has to be implemented on the breadboard, so a detail description of the breadboard
structure is given below.
VII. Breadboard Structure

In general, the breadboard consists of two terminal strips and two bus strips (often
broken in the center). Each bus strip has two rows of contacts. Each of the two rows of
contacts is a node. That is, each contact along a row on a bus strip is connected together
(inside the breadboard). Bus strips are used primarily for power supply connections, but
are also used for any node requiring a large number of connections. Each terminal strip
9
has 60 rows and 5 columns of contacts on each side of the centre gap. Each row of 5
contacts is a node.
You will build your circuits on the terminal strips by inserting the leads of circuit
components into the contact receptacles and making connections with wire. It is a good
practice to wire +5V and 0V power supply connections to separate bus strips.
Figure 1-1 Breadboards
The shaded lines indicate connected holes.
Key Functional Blocks of EPAL

The functional blocks on ePAL directly or indirectly support experiments related to
analog and digital electronics.
10
Fig-1.2 ePAL Board
11
I. Integrated Circuit
An integrated circuit (IC) is a group of components which may include resistors, low
value capacitors and transistors printed on a silicon chip. The individual components of
the I.C make up a commonly used circuit. The circuits can range from simple voltage
regulatorsto audio chips for a head unit to a microprocessor for a computer. The chip is
packaged in a plastic holder with pins spaced on a 0.1" (2.54mm) grid, which will fit the
holes on breadboards. Very fine wires inside the package link the chip to the pins.
Figure 1-3 74LS04 Inverter
Pin Numbers
The pins are numbered anti-clockwise around the IC (chip) starting near the notch or
dot. The diagram shows the numbering for 14-pin ICs, but the principle is the same for
all sizes. Sometimes the chip manufacturer may denote the first pin by a small indented
circle above the first pin of the chip. Remember that you must connect power to the
chips to get them to work.
12
Datasheets
Datasheets are available for most ICs giving detailed information about their ratings and
functions. In some cases, example circuits are shown.
Logic ICs types

Logic chips process digital signals and there are many devices, including logic gates, flip-
flops, shift registers, counters and display drivers. They can be split into two groups
according to their pin arrangements: the 4000 series and the 74 series, which consists of
various families such as the 74HC, 74HCT and 74LS.
The table below summarizes the important properties of the most popular logic
families:
Table 1-1
74 Series 74 Series 74 Series

Property 4000 Series
74HC 74HCT 74LS
High-speed CMO High-speed CMOS TTL Low-power

Technology CMOS
S TTL compatible Schottky
Power Supply 3 to 15V 2 to 6V 5V ±0.5V 5V ±0.25V
Very high impedance.

Very high impedance. Unused inputs must 'Float' high to logic 1
Unused inputs must be
be connected to +Vs or 0V. Inputs cannot if unconnected. 1mA
Inputs be reliably driven by 74LS outputs unless
connected to +Vs or
must be drawn out to
0V. Compatible with
a 'pull-up' resistor is used (see below). hold them at logic 0.
74LS (TTL) outputs.
Can give about Can give up to

Can give about
5mA (10mA with 9V Can give about 20mA, 16mA (enough to
20mA, enough to
supply), enough to enough to light an light an LED), but
light an LED. To
Outputs light an LED. To
switch larger
LED. To switch larger source only about
switch larger currents use a 2mA. To switch
currents use a
currents use a transistor. larger currents use a
transistor.
transistor. transistor.
13
One output can
drive up to 50
One output can drive
CMOS, 74HC or One output can drive up to 50 CMOS, 74HC
Fan-out up to 10 74LS inputs
74HCT inputs, but or 74HCT inputs, but only 10 74LS inputs.
or 50 74HCT inputs.
only one 74LS
input.
Maximum
about 1MHz about 25MHz about 25MHz about 35MHz
Frequency
Power
consumption A few µW. A few µW. A few µW. A few mW
of the chip itself
Removing a chip from its holder

If you need to remove a chip it can be gently ejected out of the holder with a
small flat-blade Screw driver. Now carefully lever up each end by inserting the
screwdriver blade, between the Chip and its holder, and gently twisting the screwdriver.
Take care to start lifting at both ends. Before you attempt to remove the chip, otherwise
you will bend and possibly break the pins.
VIII. Building the Circuit

Throughout these experiments, we will use TTL chips to build circuits. The steps for
wiring a circuit should be completed in the order described below:
1. Turn the power off before you build anything!
37.Connect the +5V and ground (GND) leads of the power supply to the power and
ground bus strips on your breadboard respectively.
38.Plug the chips you will be using into the breadboard. Point all the chips in the same
direction with pin 1 at the left corner. (Pin 1 is often identified by a dot or a notch
next to it on the chip package).
14
39.Connect +5V and GND pins of each chip to the power and ground bus strips on the
breadboard.
40.Select a connection on your schematic and place a piece of hook-up wire between
corresponding pins of the chips on your breadboard. It is better to make the short
connections before the longer ones. Mark each connection on your schematic as you
go, so as not to try to make the same connection again at a later stage.
41.Get one of your group members to check the connections, before you turn the
power on.
42.If an error is made and is not spotted before you turn the power on. Turn the power
off immediately before you begin to rewire the circuit.
43.At the end of the laboratory session, collect hook-up wires, chips and all equipment
and return them.
44.Tidy the area that you were working in and leave it in the same condition as it was
before you started return them.
Logic Works:
In this section, you will learn how to use logic works software for digital circuits.
To start, Double click on the logic works icon. Once the program has started, you will see
a screen like this.
I. Tools:
Design Window
The Design Window, also called the Drawing Window, contain the circuits you design. It
is your main interface with the software.
15
Parts Palette:
The Parts Palette, or the Library, contains all of the parts that you will use to design
circuits. Parts palette has Filter box, which is used to search desired component .
Fig: 1-4: Logic Works Front End
16
Fig 1-6: Drawing Toolbar
Timing Window
This is the other important window. When simulation starts, the Timing Window will
display the waveforms associated with your circuit.
Drawing Toolbar
The Drawing Toolbar is used to control the Cursor and modify the status of the Drawing
Window. The options of the Drawing Toolbar can turn the Cursor into a magnifying
glass, a logic probe, a precision deletion tool, a labeling tool, and a wiring tool. It can
also be used to cut, copy, paste, and obtain information about selected parts.
Fig 1-5: Part Palette
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Simulation Toolbar
The Simulation Toolbar is used to simulate the digital circuit. Simulation can be start
And stop. It can be used to control the rate at which simulations are generated, or we
can increment simulation in steps.
IX. Design:
Part Placement
To place a part in the Design Window, double-click on the desired part name in the
library. A shadowed version of the part will appear at the cursor. Place the part at the
desired location and click. The part selected will remain active for placement until it is
deactivated. If you want to select a new part, double-click on that part name and repeat
the previous steps. If you just want to deactivate the part without selecting a new one,
press the space bar or the Escape key.
Wiring
There are two methods of wiring in logic works.
1. Use Draw tool to join two pins
45.Click and hold on the one end of the pin and move the cursor where you want to end
the wire.
Editing
To move a part or a wire, click on it and drag it to the desired location. Selected parts
will appear highlighted in black, and wires will appear highlighted in yellow. Be careful
when moving parts, because wires attached to moving parts will “stretch,” and
unwanted nodes may be created.
Magnify
The Magnification cursor will present a centered and magnified view of the location that
is clicked. Magnification can also be done using the Magnify command under the View
18
menu. There is no Reduce cursor, but reduction can be done using the Reduce to Fit
command under the View menu, or through various zooming techniques.
Probe
The Probe tool has two uses. First, when the cursor is touched to a pin and held (click
and hold), that pin’s logic level is displayed.
Second, if you enter a logic value while probing a pin, the pin will take on that value.
Pointer
This is the default cursor selection.
Zap
In several cases, you will want to delete one part of a wire without deleting the whole
mesh, or you may want to delete one object in a particularly tight space. The Zap cursor
allows you more flexibility in deleting objects. When enabled, clicking on an object with
the zap cursor will delete only the part of an object that appears at the tip of the cursor.
This is very useful for removing errant parts of wires.
Text
Using the Text cursor, you can insert text into schematics, i.e. titles, chip descriptions or
wire and pin labels. Clicking on the text button changes the cursor into a pencil. When
the pencil tip is inserted in a random location, a text window appears at that location,
and miscellaneous text can be inserted. Type in the desired text, and click the text
cursor elsewhere once you are finished. To edit text, click the text cursor in the vicinity
of existing text.
19
Post Lab Assignment:
Q1: Draw and simulate the circuit given below. Obtain truth table of ‘Y’ and show timing
diagram of all signals.
Fig 1-7: Post Lab Question 1
Q2: Draw and simulate the circuit given below. Obtain truth table of ‘Y’ & ‘Z’ and show
timing diagram of all signals.
Fig 1-8: Post Lab Question 2
Q3: Draw and simulate the circuit given below. Obtain truth table of ‘F’ and show the
timing diagram of all signals.
20
Fig: 1-9: Post Lab Question 3
Review Question:
Q1: What does the Fan Out means?
Q1: What are the ASCII, Access-3 and BCD codes?
Q1: Differentiate between Analog and Digital.
21
22
LAB 2
To Verifying basic gates truth table using logic ICs
Group Number
Submitted by

Mathematical and Scientific Terms:

Knowledge Base for Engineering
Rubrics for CLO#2 (PLO#2: Problem Analysis) Marks
Identify/Define Lab Objectives

Problem Analysis
Hardware and software

Components:
Obtained Marks
23
Objectives:
1. To become familiar with the operation of Basic Gates (AND, OR, NOT, NAND, NOR,
XOR, XNOR) using ICs.
46.To become familiar with how to determine the truth tables for logic gates.
Background Theory
Logic deals with only two normal conditions: logic TURE or logic FALSE. In Boolean logic,
TRUE is often represented by the term HIGH or the number 1 and FALSE is represented
by the term LOW or the number 0. HIGH and LOW (1 or 0) are logic terms; they do not
indicate whether the voltage is higher or lower. In positive logic the more positive
voltage is TRUE and the less positive voltage is FALSE i.e +2.5V = HIGH and +0.5V = LOW.
With the negative logic this definition is reversed.
The basic logic gates and their symbols are summarized in the following pages. The truth
table with all possible input combination is given and the output is left empty to you as
an exercise. All possible combination of inputs involve counting in binary from 0 to 2 n – 1
where n is the number of inputs.
Fig 2-1: Positive Logic
24
In this experiment you will look at the truth tables for several arrangements of simple
gates.
Equipment Required:
1. EPAL 27
47. Cutter
48. Single Core Wire
49. Pair of Strippers
X. To check the operation of OR gate according to the OR’s truth

table, using the IC 74LS32
Theory
The electronic symbol for a two- input OR gate is shown in fig.1. The two inputs have
been marked as A and B and the output as C. The OR gate has an output of 1when
either A or Bor both are 1.
In other words, it is any or all gate because an output occurs when any or all the inputs
are present. Obviously, the output would be 0 if and only if both its inputs are 0. The OR
gate represents the Boolean equation.
A+B = C
The above logic operation of the OR gate can be summarized with the help of the truth
table. A truth table may be defined as a table, which gives the output state for all
possible input combinations.
25
Equipment Required:
1. 74LS32
Symbolic diagram:
Truth Table:
Input Output
A B C
Pin Configuration:
26
XI. To check the operation of AND gate according to the AND’s
truth table, using the IC 74LS08
Theory
A Logic AND Gate is a type of digital logic gate that has an output which is normally at
logic level "0" and only goes "HIGH" to a logic level "1" when ALL of its inputs are at logic
level "1". The output of a Logic AND Gate only returns "LOW" again when ANY of its
inputs are at a logic level "0". The logic or Boolean expression given for a logic AND gate
is that for Logical Multiplication which is denoted by a single dot or full stop symbol, (.)
giving us the Boolean expression of:
A.B = Q.
Equipment Required:
50.74LS08
Symbolic diagram:
Truth Table:
Input Output
A B Q
27
Pin Configuration:
Vcc 14 13 12 11 10 9 8
XII. To check the

operation of NOT 1 2 3 4 5 6 7
gate
GND
according to the Quad 2-input AND gate 7408
NOT’s truth table, using

the IC 74LS04
Theory:
The output of NOT gate is opposite to its inputs. It is also called an inverter because it
inverts the input signal. It has one input and one output. All it does to invert (or
complement) the inputs.
Equipment Required:
51.74LS04
Symbolic diagram:
Truth Table:
Input Output
A Y
28
Pin Configuration:
XIII. To check the operation of NOR gate according to the NOR’s

Theory:
It is a NOT-OR gate. It can be obtained by connecting a NOT gate in the output of an OR

gate as shown in fig. Its output is given by the Boolean equation.
C’ = (A+B)’
It gives an output when it’s both inputs are 0.
Equipment Required:
52.74LS02
Symbolic diagram:
29
Truth Table:
Input Output
A B C`
Pin Configuration:
XIV. To check the operation of NAND gate according to the

NAND’s truth table, using the IC 74LS00
30
Theory:
It is in fact a NOT-AND gate .It can be obtained by connecting a NOT gate in the output
of an AND gate as shown in fig. Its output is given by the Boolean equation.
Q’= (A.B)’
This gate gives an output high if either A or B or both are 0.
Equipment Required:
53.74LS00
Symbolic diagram:
Truth Table:
Input Output
A B Q`
Pin Configuration:
Vcc 14 13 12 11 10 9 8
31
1 2 3 4 5 6 7
GND
Quad 2-input NAND gate 7400
XV. To check the operation of XOR gate according to the XOR’s
Theory:
It is the gate which gives an output 1when its inputs are not same (or exclusive) and
anoutput0 when its inputs are same. Its symbol is shown in fig.
Equipment Required:
54.74LS86
Symbolic diagram:
Truth Table:
Input Output
A B X
32
Pin Configuration:
Vcc 14 13 12 11 10 9 8
1 2 3 4 5 6 7 GND
Quad 2-input XOR gate 7486
Procedure
1. Connect the trainer board with the power supply
55.Mount the corresponding 74LSXX IC on the board.
56.Connect pin 14 to +5 V and pin 7 to GND.
57.Wire the circuit according to the diagram by consulting the corresponding gate ICs
data sheet.
58.Apply all the combinations of inputs and observe the output on the LED to verify the
truth tables of the gates.
33
Post Lab Assignment
Q1: Simulate the following logic gates with three inputs in Logic Works, verify the truth
table and show Timing Diagram.
a. AND gate b. OR Gate c. NAND Gate d. XOR Gate e. XNOR
Q2: Given the following three 4-bit strings, Simulate and evaluate the 4-bit result after
the following logical Operations.
A = 1010 B = 1101 C = 1001
a. AND b. OR c. NAND d. XOR e. NOT A
34
LAB 3
Implementation of Boolean functions and combinational logic
using logic gate
Group Number
Submitted by



Problem Analysis

Components:
Obtained Marks
35
Objectives:
1. To become familiar with Boolean function implementation using logic gates
2. To evaluate logic operation of a circuit from the Boolean expression
3. To understand the Boolean equation reduction and its effect on logic circuit.
4. To become familiar with combinational circuit design
Background Theory
Boolean algebra is an Algebra that deals with binary variables and logic operations.
When a Boolean expression is implemented with logic gates, each term requires a gate,
and each variable within the term designates an input to the gate. We define a literal as
a single variable within the term that may or may not be complemented.
By reducing the number of terms, the number of literals, or both in a Boolean

expression, it is often possible to obtain a simpler circuit. Boolean algebra or K-map is
applied to reduce an expression for the purpose of obtaining a simpler circuit
For a given value of the binary variable, the function can be equal to either 1 or 0. As an
example, consider the Boolean function
F 1=X + Ý Z
The function F1 is equal to 1 if x is equal to 1 or if both ȳ and z are equal to 1. F1 is equal

to 0 otherwise. The complement operation dictates that when ȳ = 1, y = 0.
Therefore F1 = 1 if x= 1 or if y = 0 and z = 1. A Boolean function expresses the logical

relationship between binary variables and is evaluated by determining the binary value
of the expression for all possible values of the variables.
36
A Boolean function can be represented in a truth table. The number of rows in a truth
table is 2n where n is the number of the variables in the function. The binary
combination for the truth table is obtained from the binary numbers by counting from 0
through 2n-1.
Boolean function can be transformed from an algebraic expression into a circuit diagram
composed of logic gates connected in a particular structure.
A ( B +CD )
CD term in function is product term that is represented by an AND gate. Similarly OR

gate is used for B+CD term. A detail logic diagram shown below with signal naming.
A B C D A(B+CD)
Fig 3-1: Gate diagram of 0 0 0 0 function F1
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
37 1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
Procedure
2. Mount the corresponding 74LSXX IC on the board.
3. Wire the circuit according to the diagram by consulting the corresponding gate ICs
data sheet.
4. Apply all the combinations of inputs and observe the output on the LED
5. Fill the truth table according to your observation.
Boolean function minimization and analysis of logic diagram

using logic works
Boolean Function
AB + A (B + C) + B (B + C)
Minimization:
AB+ AB+AC+BB+BC Rule AB+AB = AB
AB + AC + B+ BC Rule BB = B
AB+AC+B Rule B+BC = B
B+AC Rule AB+B = Bs
Fig 3-2: Gate Implementation after minnimization
38
Fig 3-2: Gate Implementation before
minimization
Procedure
1. Draw Circuit 1 in Logic works and obtain its Truth table for all possible combination.
59.Draw second reduced circuit in logic works and obtain its truth table
60.Compare both truth table to verify both circuits
Combinational circuits
Logic circuits for digital systems may be combinational or sequential. A combinational
circuit consists of logic gates whose outputs are determined from only the present
combination of inputs. A combinational circuit performs an operation that can be
specified by a set of Boolean functions.
Design Procedure
The design of combinational circuits starts from the specification of the design objective
and culminates in a logic circuit diagram or a set of Boolean function from which the
logic diagram can be obtained. The procedure involves the following steps.
1. From the specification of the circuit, determined the required number of inputs and
outputs.
2. Drive the truth table that defines the required relationship between inputs and
outputs
3. Obtain a simplified Boolean function for each output as a function of the input
variable.
39
4. Draw the logic and verify the correctness of the design by simulation or by hardware
implementation.
Design Example
In a certain chemical processing plant, a liquid chemical is used in a manufacturing
process. The chemical is stored in three different tanks. A level sensor in each tank
produces a HIGH voltage when the level of chemical in the tank drops below a specified
point. Design a circuit that monitors the chemical level in each tank and indicates when
the level in any two of the tank drops below the specified point.
Truth table
A B C OUTPUT
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1
Fig 3-4: Gate implementation of combination circuit
40
Equipment Required
1. IC 7408
61.IC 7432
Procedure:
63.Connect pin 14 to +5 V and pin 7 to GND.
data sheet.
65.Apply all the combinations of inputs and observe the output on the LED to verify the
truth tables of the gates.
Post Lab Assignment

Q1. Draw logic diagram and construct a truth table for each of the following Boolean
Expressions.
a. A B́+ Á B b. ( A+ B)( Á+ B) c. A+ B[C+ D ( B́+C ) ]
Q2. In a certain processing plant, a liquid is used in manufacturing plant. The liquid is
stored in four tanks. A level sensor in each tank produces high when the level of liquid
drops below a specified point. Two motors are installed with tanks to fill liquid. Motor A
41
turns on only when the level of tank A and tank C drops below a specified point. Motor
B Turns on when the level of tank B and Tank D drops. If the level of all tanks drops
below, both motors turns on otherwise stay, off.
Design logic circuit and construct a truth table.
42
LAB 4
Gate level minimization of Boolean Function
Group Number
Submitted by



Problem Analysis

Components:
Obtained Marks
43
Objectives:
1. The need of gate level minimization
5. Understand the K-Map method
Background Theory
Gate-level minimization refers to the design task of finding an optimal gate-level
implementation of the Boolean functions describing a digital circuit. The K-map method
provides a simple, straight forward procedure for minimizing Boolean functions. A K-
map is a diagram made up of squares, with each square representing one minterm of
the function. By recognizing various pattern, the user can derive alternative simple
algebraic expression for the same function.
Equipment required
1. 74LS32
2. 74LS08
3. EPAL 27
4. Cutter
5. Single Core Wire
IN-Lab Task
Simplify the following Boolean Expression using K-Map
F=X ' Y ' Z' + X ' Y Z ' + XY Z ' + XYZ
44
The gate implementation of the above expression is given below.
Fig4-1: Gate Implementation of In-lab task
Fig 4-2: K-map for in-lab task
The simplified expression from the above K-Map is
F=XY + X ' Z '
The minimized gate implementation of the expression is
45
Fig 4-3: Minimized gate implementation of in-lab task
Post-Lab Task:
Q1. Simplify the following Boolean Expression and develop the truth table. Also draw
circuit diagram for the simplified expression.
F=∑( 1,3,5,7)
46
LAB 5
Gate Level Minimization of Boolean Function using K-Map
Group Number
Submitted by



Problem Analysis

Components:
Obtained Marks
47
Objectives:
1. To optimize the number of gates in 4 and 5 variables Boolean functions
2. Cross verify the result with Boolean function and minimized Boolean function
Background Theory
We must ensure that (1) all the mintem of the function are covered when we combine
the squares. 2) The number of terms in the expression is minimized, and (3) there are no
redundant.
I. Four Variable K-Map

The map for Boolean functions of four binary variables can list the 16 min-tem and the
squares assigned to each. The rows and columns are numbered in a Gray code
sequence, with only one digit changing value between two adjacent rows or columns.
Fig 5-1: Four Variable K-Map Structure
48
The combination of adjacent square that is useful during the simplification process is
easily determined from inspection of the four-variable map:
1. One square represents one mintem, giving a term with four literals
2. Two adjacent squares represent a term with three Literals
3. Four adjacent squares represents a term with two literals
4. Eight adjacent squares represents a term with one literal
5. Sixteen adjacent squares produce a function that is always equal to 1
XVI. Five Variable K-Map

Maps for more than four variables are not as simple to use as maps for four or fewer
variables. A five-variable map needs 32 squares and a six-variable 64-needs squares.
When the number of variables become large number of square becomes excessive and
the geometry of combining adjacent squares become more involved.
Fig 5-2: Five Variable K-Map structure
49
In-Lab task
1. Simplify the following Boolean function using K-Map and then cross check with
original function.
F ( A , B ,C , D ) =∑(4,6,7,15)
Fig 5-3: K-map for In-Lab task
F=BCD+ A' B D '
Post-Lab Task
1. Minimize the number of gates in the following Boolean function.
F ( A , B ,C , D ) =∑(3,7,11,13,14,15)
50
LAB 5
Implementation with NAND gates using NAND universal gate
Group Number
Submitted by



Problem Analysis

Components:
Obtained Marks
51
Objectives:
1. To become familiar with universal gates and implementation of basic gates using
NAND
6. To understand logic function implementation using NAND gate
Background Theory
Combinational circuits are more frequently constructed with NAND or NOR gates rather
than AND and OR gates. NAND and NOR gates are more common from the hardware
point of view because they are readily available in integrated-circuit form. The NAND
gate is said to be a universal gate because any digital system can be implement with it.
Combinational circuits and sequential circuits as well can be constructed with this gate
because the flip-flop circuit (the memory element most frequently used in sequential
circuits) can be constructed from two NAND gates.
Equipment required
7. 74LS00
8. EPAL 27
9. Cutter
10.Single Core Wire
11.Pair of Strippers
Truth Table:
A truth table of NAND gate is give below for reference.
52
Input Output
A B Q`
0 0 1
0 1 1
1 0 1
1 1 0
I. To check the operation of XOR gate, using NAND gate IC
With the help of 4 NAND gate we can construct XOR gate.
Truth table
Truth table of XOR gate is given bellow
Input Output
A B AB
0 0 0
0 1 1
1 0 1
1 1 0
Boolean Expression
F=
Circuit Diagram
53
Procedure
1. Write the truth table for the function given above.
66.Fill the k-map cells from the truth table.
67.Simplify and minimize the function with k-map.
68.Write the simplified function from k-map.
69.Draw the circuit diagram and construct the circuit on the Trainer Boar
XVII. To check the operation of OR gate, using NAND gate IC
The OR operation is achieved through NAND gate with additional inverters in each
input.
With the help of 3 NAND gates we can construct OR gate.
Truth table
Truth table of OR gate is given bellow
Input Output
A B A+B
0 0 0
0 1 1
1 0 1
1 1 1
Boolean Expression
F=
54
Circuit Diagram
Procedure
73.Draw the circuit diagram and construct the circuit on the Trainer Board.
XVIII. To check the operation of AND gate, using NAND gate IC
The AND operation requires two NAND gates. The first produces the inverted AND and
the second acts as an inverter to produce the normal output.
55
Truth table
Input Output
A B A.B
0 0 0
0 1 0
1 0 0
1 1 1
Boolean Expression
F=
Circuit Diagram
XIX. To check the operation of NOT gate, using NAND gate IC
56
The NOT operation is obtained from a one-input NAND gate, actually another symbol or an inverter
circuit. A single NAND also works as a NOT gate.
Truth table
Input Output
A A`
0 1
1 0
Boolean Expression
F=
Circuit Diagram
57
Procedure
77.Draw the circuit diagram and construct the circuit on the Trainer Board.
IN-Lab Task
Boolean functions can be implemented using NAND gate only. Consider the following
function
´´ ´
F 1= Á B+CD F 1= Á B+CD F 1= Á´B . CD
´
Draw logic diagram using logic gates and using NAND gate and compare truth table.
Implement both circuits in logic works.

Q1: implement basic gates (AND, OR, NOT, XOR ) using NOR gate and verify truth table
Q2: Implement the following function.
o Using basic gates (AND, OR, NOT)
o Using NAND gate
58
Compare truth table of both circuits.
F 1= X́ Ý Z + X́ Y Ź + X Ý Ź + XYZ
12.
59
LAB 6
Half Adder and Full Adder operation
Group Number
Submitted by



Problem Analysis

Components:
Obtained Marks
60
Objectives:
1. To understand operation of half and full adder
7. Implement Four-bit adder
Background Theory
I. ADDERS
Digital computers perform a variety of information-processing tasks. Among the basic

functions encountered are the various arithmetic operations. The most basic arithmetic
operation, no doubt, is the addition of two binary digits. This simple addition consists of
four possible elementary operations, namely, 0 + 0 = 0, 0 + 1 = 1, 1 + 0 = 1, and 1 + 1 =
10. The first three operations produce a sum whose length is one digit, but when both
augends and addend bits are equal to 1, the binary sum consists of two digits. The
higher significant bit of this result is called a carry. When the augends and addend
numbers contain more significant digits, the carry obtained for the addition of two bits
is added to the-next higher orders pair of significant bit.
XX. HALF ADDER
A combinational circuit that performs the addition of two bits is called a half-adder.
From the verbal explanation of a half-adder, we find that this circuit needs two binary
inputs and two binary outputs. The input variables designate the augends and addend
bits; the output variables produce the sum and carry. It is necessary to specify two
output variables because the result may consist of two binary digits. We arbitrarily
assign symbols x and y to the two inputs and S (for sum) and C (for carry) to the outputs.
61
Equipment Required:
1. 74LS08 (AND)
2. 74LS83 (Four-bit Adder)
3. 74LS32 (OR)
4. 74LS86 (XOR)
5. EPAL 27
6. Cutter
7. Single Core Wire
Truth table
In the light of the specifications of Half-adder give above, fill in a truth table containing
all the possible combinations of two 1-bit inputs and the resultant values of sum and
carry.
Inputs Outputs
B A Sum Carry
0 0
0 1
1 0
1 1
∑ , S=A ⊕ BCarry ,C= A . B
62
Circuit Diagram
Fig 6-1: Half Adder circuit diagram
XXI. FULL ADDER:

A full-adder is a combinational circuit that forms the arithmetic sum of three input bits.
It consists of three inputs and two outputs. Two of the input variables, denoted by x and
y represent the two significant bits to be added. The third input, z, represents the carry
from the previous lower significant position. Two outputs are necessary because the
arithmetic sum of three binary digits’ ranges in value from 0 to 3, and binary 2 or 3
needs two digits. The two outputs are designated by the symbols S for sum and C for
carry. The binary variable S gives the value of the least significant bit of the sum.
Equipment Required:
1. 74LS08 (AND)
78.74LS86 (XOR)
79.74LS32 (OR)
Truth table
In the light of the specifications of Full-adder give above, fill in a truth table containing
all the possible combinations of two 1-bit inputs, a carry in (or a third input) and the
resultant values of sum and carry.
63
Inputs Outputs
Cin B A Sum Carry
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Circuit Diagram
Fig 6-2: Full adder circuit diagram
XXII. Parallel Adder

A single full adder is capable adding two 1-bit numbers and an input carry. To add binary
numbers with more than one bit, additional full adder must be used. To add two binary
numbers, a full adder is required for each bit in the numbers. So for 2-bit numbers, two
64
adders are needed, for 4-bit numbers, four adders are used and so on. The carry output
of each adder is connected to the carry input of the next higher order adder.
Fig 6-3: Four-bit adder block diagram
Four bit adders that are available in IC form are the 74LS83A and 74LS283. Both ICs are
identical in functionality but not pin compatible.
Adder Expansion
The 4-bit parallel adder can be expanded to handle the addition of two 8-bit numbers by
using two 4-bit adders. The carry input of the low order adder (co) is connected to
ground because there is no carry into the LSB position. The carry output of the lower
order adder is connected to the carry input of the next adder. This process is known as
cascading.
Fig 6-4: Eight-bit adder block diagram
65
Procedure:
80.Mount the corresponding IC on the board.
81.Wire the half adder circuit according to the diagram and verify its operation.
82.Wire the full adder circuit according to diagram and verify its operation.
83.Construct a 4-bit adder circuit using 4 Full Adders in logic works and add the
following data A = 1100 B = 1100
84.Use 74LS83 IC to add both numbers given above.
85.Consult data sheet of 74LS83 for proper wiring.

Q1: Construct a circuit using IC74LS83 to add two 10-bit number.
66
LAB 7
Half-subtractor and full-subtractor operations
Group Number
Submitted by


Problem Analysis

Components:
Rubrics for CLO#2 (PLO#3: Engineering Design)
Engineering Implementing Design Strategy

Design
Evaluating Final Design
Obtained Marks
67
Introduction to substrator:
The subtraction of two binary numbers may be accomplished by taking the complement
of the subtrahend adding. By this method, the subtraction operation becomes an
addition operation requiring full-adders for its machine implementation. It is possible to
implement subtraction with logic circuits in a direct manner. By this method, each
subtrahend bit number is subtracted from its corresponding significant minuend bit to
form a difference bit. If the minuend-bit is smaller than the subtrahend bit, a 1 is
borrowed from the next significant position. The fact that a 1 has been borrowed must
be conveyed to the next higher pair of bits by means of a binary signal coming out
(output) of a given stage and going into (input) the next higher stage. Just as there are -
half- and full-adders, there are half- and full subtractions.
I. HALF SUBTRACTOR:
A half sub tractor is a combinational circuit that subtracts two bits and produces their
difference. It also has an output to specify if a 1 has been borrowed. Designate the
minuend bit by x and the subtrahend bit by y. To perform x - y, we have to check the
relative magnitudes of x and y. If x ~ y, we have three possibilities: 0 - 0 = 0, 1 - 0 = 1,
and 1 - 1 = O.
The result is called the difference bit. If x < y, we have 0 - 1, and 'it is necessary to
borrow a 1from the next higher stage. The 1 borrowed from the next higher stage adds
2 to the minuend bit, just as in the decimal system a borrow adds, 10 to a minuend digit.
With the minuend equal to 2, the difference becomes 2 - 1 = 1. The half-sub tractor
needs two outputs. One output generates the difference and will be designated by the
68
symbol D. The second output, designated B for borrow, generates the binary signal that
informs the next stage that a 1 has been borrowed.
Equipment Required:
1.74LS08
2.74LS86
3.74LS04
Tools:
1. EPAL 27
2. Cutter
3. Single Core Wire
Truth table
A truth table containing all the possible combinations of two 1-bit inputs and the
resultant values of borrow and difference is given bellow.
Inputs Outputs
A B D B
0 0 0 0
0 1 1 1
1 0 1 0
69
1 1 0 0
Boolean Expression
Difference = A B+A B
Borrow = A B
Circuit Diagram
Fig 7-1: Half substrator logic diagram
XXIII. FULL SUBTRACTOR

A full-sub tractor is a combinational circuit that performs a subtraction between two
bits, taking into account that a 1 may have been borrowed by a lower significant stage.
The circuit has three inputs and two outputs. The three inputs, x, y, and z, denote the
minuend, subtrahend, and previous borrow, respectively. The two outputs, D and B,
represent the difference and output borrows respectively.
Equipment Required:
1. 74LS86 x 1
2. 74LS08 x 1
70
3. 74LS04 x 1
4. 74LS32 x 1
Truth table
In the light of the specifications of Full-subtractor give above a truth table containing all
the possible combinations of two 1-bit inputs A and B, a borrow in and the resultant
values of Difference and borrow out are given.
Inputs Outputs
A B Bin D Bout
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
Boolean Expression
Difference =
Borrow out =
Circuit Diagram
71
Fig 7-2: Full Substractor Logical diagram
Procedure:
1. Connect the trainer with the power supply
86.Install the ICs on the trainer board.
87.Wire according to the diagram.
88.Use the logic switches for input and connect output of the circuit to the LEDs of
trainer board.
89.Supply the VCC and GND to the circuit
90.Test all the possible combination of inputs and fill out the table
Post lab Assignment:
Q1: Draw 4-bit Subtractor circuit using four full-Subtractor. Get results of A-B where
A = 1000 B = 0001
72
LAB 8
Magnitude comparator
Group Number
Submitted by


Problem Analysis

Components:

Design
Obtained Marks
73
Objective:
1. To design and implement 1-bit magnitude comparator using basic gates
91.To design and implement 2-bit magnitude comparator using basic gates
92.To implement 4-bit magnitude comparator using IC 7485
Equipment required:
1. IC 74LS266
93. IC 74LS08
94. IC 74LS04
95.IC 74ls85
96.ePal Trainer board
Theory:
The comparison of the two numbers is an operator that determines one number is
greater than, less than or equal to the other. A magnitude comparator is a
combinational circuit that compares two numbers A and B and determines their relative
magnitude. The outcome of the comparator is specified by the binary variables that
indicate whether A>B, A=B, A<B.
1-bit Comparator:
The truth table for the single bit comparator is given below.
When A B = 00 & 11, both inputs are equal, therefore A=B output will be high. When AB
= 01, B is more than A and hence AB) = AB’
Circuit diagram:
2-bit Comparator:
A 2-bit comparator compares two binary numbers, each of two bits and produces their
relation such as one number is equal or greater than or less than the other. The truth
table below shows the all possible combination. The first number A is designated as A =
A1A0 and the second number is designated as B = B1B0. This comparator produces three
outputs as A>B, A = B and A<B.
Truth Table:
A B A=B AB
0 0 1 0 0
A1 A0 0 B11 B0
0 1AB
0 0 1 00 0 00 1 1 0
0 0 1 01 1 01 0 0 0
0 0 1 0 1 0 0
0 0 1 1 1 0 0
0 1 0 0 0 0 1
0 1 0 1 0 1 0
0 1 1 0 1 0 0
0 1 1 1 1 0 0
1 0 0 0 0 0 1
1 0 0 1 0 0 1
1 0 1 0 0 1 0
1 0 1 1 1 0 0
75
1 1 0 0 0 0 1
1 1 0 1 0 0 1
1 1 1 0 0 0 1
1 1 1 1 0 1 0
K-map
AB
00 01 11 10
B1B0
A1A0
00
01 1
76
11 1 1 1
10 1 1
Boolean Expression:
AB =
Circuit diagram:
4- bit comparator:
it can be used to compare two four-bit words. The two 4-bit numbers are A = A3 A2 A1
A0 and B3 B2 B1 B0 where A3 and B3 are the most significant bits. It compares each of
77
these bits in one number with bits in that of other number and produces one of the
following outputs as A = B, A B.
The 4-bit comparator is mostly available in IC form and common type of this IC is 7485.
This IC can be used to compare two 4-bit binary words by grounding I (A>B), I (A<B) and
I (A=B) connector inputs to Vcc terminal. The figure below shows the pin diagram of
IC7485 comparator.
in addition to the normal comparator, this IC is provided with cascading inputs in order
to facilitate the cascading several comparators. Any number of bits can be compared by
cascading several of these comparator ICs.
8-Bit Comparator
An 8-bit comparator compares the two 8-bit numbers by cascading of two 4-bit
comparators. The circuit connection of this comparator is shown below in which the
lower order comparator A<B, A=B and A>B outputs are connected to the respective
cascade inputs of the higher order comparator.
For the lower order comparator, the A=B cascade input must be connected High, while
the other two cascading inputs must be connected to LOW. The outputs of the higher
order comparator become the outputs of this eight-bit comparator.
78
Procedure:
data sheet.
99.Apply different combinations of inputs and observe the output on the LED to verify
the operation of comparator.
100. Implement 2-bit comparator in logic works
Post Lab Assignment

Q1: An office door is equipped with electronic code lock system. This system needs 4-bit
code to open the door. One 4-bit code is already stored in code lock system. When user
enters the same correct code, and it matches with the code that is stored in the code
lock circuit, door opens. Devise a logic circuit to implement simple 4-bit code lock.
79
LAB 9
The Operation of Decoder
Group Number
Submitted by


Problem Analysis

Components:

Design
Obtained Marks
80
Objectives:
1. To understand the functioning and properties of decoder circuits
101. Designing and implementation of 2-to-4 line decoder
102. Implementing BCD to Decimal decoder using IC 7442
103. Use of seven segment display driver IC
Equipment Required:
1. 74LS04
2. 74LS08
3. 74HC42
4. 74LC47/48
Tools:
1. EPAL 27
2. Cutter
3. Single Core Wire
Theory:
A decoder is a combinational circuit that converts binary information from n inputs to
2noutputs. Decoder is a multiple input, multiple output logic circuit that converts coded
input into coded output, where the input and output codes are different. The input code
generally has fewer bits than the output code, and there is one-to-one mapping, each
input code word produces a different output code word. The most commonly used
81
input code is an n-bit binary code, where an n-bit word represents one of 2 n different
coded values, i.e. n-to-2n decoder or binary decoder.
1-to- 2 line decoder:
The simplest decoder is the 1-to-2 line decoder.
A D0 D1
0 1 0
1 0 1
2-to-4 line decoder:
The circuit diagram below represents the logic for a 2-bit decoder. When a low voltage
(represented by 0) is placed on both inputs, then a high voltage appears on Output D0
while the remaining outputs show a low voltage. The truth table below describes the
behavior of the two-bit decoder when a low voltage is placed on both inputs.
Truth Table:
Inputs Outputs Decoder Function

A1 A0 D0 D1 D2 D3
0 0 1 0 0 0 A1A0
0 1 0 1 0 0 A1A0
1 0 0 0 1 0 A1A0
1 1 0 0 0 1 A1A0
Circuit diagram:
82
BCD-to-Decimal Decoder:
The BCD-to-Decimal decoder converts each BCD code (8421 code) into one of ten
possible digit indications. It is frequently referred as a 4-line-to-10-line decoder or 1-of-
10 decoder. In order to implement all possible combinations, ten decoding gates are
required.
If an active low output is required for each decoded number, the entire decoder can be
implemented with NAND gates and NOT. AND gates can be used to produce active HIGH
outputs. The 74HC42 is an integrated circuit BCD-to-decimal decoder. The pin diagram
is shown below.
BCD-to-7-Segment decoder:
83
The BCD to seven-segment decoder accepts the BCD code on its inputs and provides
output to drive 7-sement display devices. The 74ls47 is common anode and 74ls48 is
common cathode IC that decodes a BCD input to 7 segment displays. The pin diagram of
decoder ic and seven segment display is shown below.
Decoder IC 7-segment display
In addition to its decoding capabilities, these IC’s have some additional features as
indicated by the LT,RBI and BI/RBO functions. All of the outputs are active low as are the
LT( lamp test), RBI (Ripple Blanking Input) and BI/RBO (Blanking Input/Ripple Blanking
Output)
Lamp Test (LT): when a low is applied to the LT input and BI/RBO is HIGH, All of the
segments in the display are turned on. Lam test is used to verify that no segments are
burned out.
Zero Suppression: This feature is used for multi-digit displays to blank out unnecessary
zeros. This is accomplished using RBI and BI/RBO pins. RBI should be connected to the
RBO of the previous digit (the digit to the left). In this way, you may avoid showing
trailing "0" if not needed as you do in manual number writing. In this way, for example,
the multidigit number "00123" will show as "123" while "02034" will show as " 2034" .
84
Truth Table:
In-Lab Task:
1. Implement 2-to-4 line decoder using basic gates and verify truth table.
104. Implement BCD-to-decimal decoder using IC 74HC42.
105. Use seven segment drivers IC to drive seven segment displays.
Note: Use ePAL trainer to implement all three tasks.
Post Lab Task:

Q1: construct truth table for 3-to-8-line decoder and draw its circuit diagram using AOI
gates.
85
LAB 10
The Operation of Encoder
Group Number
Submitted by


Problem Analysis

Components:

Design
Obtained Marks
86
Objectives:
 To understand the functioning and properties of encoder circuits
 Designing and implementation of 4-to-2 line decoder using logic gates
 Implementing Octal and Decimal Encoder using digital IC
Equipment Required:
1. 74LS04
2. 74LS08
3. 74LS32
4. 74HC147
5. 74F148
Tools:
1. EPAL 27
2. Cutter
3. Single Core Wire
Theory:
An encoder is a combinational logic circuit that essentially performs a reverse decoder
function. An encoder accepts an active high level on one of its inputs representing a
87
digit, such as octal or decimal digit and converts it to a coded output. Encoders can also
be devised to encode various symbols or number to a coded format is called encoding.
4-to-2 line Encoder:
One of the main disadvantages of standard digital encoders is that they can generate
the wrong output code when there is more than one input present at logic level “1”. For
example, if we make inputs D1 and D2 HIGH at logic “1” both at the same time, the
resulting output is neither at “01” or at “10” but will be at “11” which is an output
binary number that is different to the actual input present. Also, an output code of all
logic “0”s can be generated when all of its inputs are at “0” OR when input D0 is equal to
one.
One simple way to overcome this problem is to “Priorities” the level of each input pin
and if there was more than one input at logic level “1” the actual output code would
only correspond to the input with the highest designated priority. Then this type of
digital encoder is known commonly as a Priority Encoder.
Priority Encoder:
This Priority encoder consists of 4 inputs and three outputs. Although an encoder has
2n inputs and n outputs, it has a third output ‘V’ which is a valid bit indicator and is set to
one when one or more inputs are active or equal to 1. This valid bit is zero when all the
88
inputs are zero which indicates that there is no valid input. On this condition, other
outputs are considered as don’t care conditions and are not inspected when V is zero.
The highest will be the priority of the input with a higher subscript number according to
the truth table that is most significant bit will have highest priority while the least
significant bit will have low priority .
In the truth table, D3 has the highest priority and D0 has lowest priority. When D3 is
active or 1, then regardless of other inputs, the output is 11. The next higher priority is
D2 after D3.The next higher priority is D2 after that D1. Thus, when D3 is 0 and D2 is 1
then regardless of other two inputs (which has lower priority), the output is 10. When
higher priority inputs are zero then the output for D1 is generated and so on down the
priority levels.
Truth Table:
Inputs Outputs
D3 D2 D1 D0 Y1 Y0 V
0 0 0 0 x x 0
0 0 0 1 0 0 1
0 0 1 x 0 1 1
0 1 x x 1 0 1
1 x x x 1 1 1
Boolean Expression:
Y0 = D3 D2 D1+ D3 = D2 D1+ D3 A+AB = A+B
Y1 = D3 D2+ D3 = D2+ D3
V = D3 +D2 + D1 + D0
Circuit Diagram:
89
8-to-3- Line Encoder:
The 74F148 is a priority encoder that has eight active LOW inputs and three active HIGH
binary outputs. This device can be used for converting octal inputs to a 3-bit binary
code. To Enable this device, EI (enable Input) pin must be LOW. It also has the EO
(enable Output) and GS Output for expansion purpose. The EO is LOW, When the EI is
LOW and none of the Input is active. GS is LOW when EI is LOW and any of the inputs is
active. The 74F148 can be expanded to a 16-line-to-4-line encoder by connecting the EO
of the higher order encoder to the EI of the lower encoder and negative-ORing the
corresponding binary outputs. The EO is used as the fourth and most significant bit. This
particular configuration produces active-HIGH outputs for the 4-bit binary numbers.
74F148
Decimal to BCD Encoder:

The 74HC147 is a priority encoder with active LOW inputs for decimal digits 1 through 9
and active- LOW BCD outputs. A BCD zero output is represented when none of the
inputs is active.
90
In-Lab Task:
1. Implement 4x2 line Encoder using logic gates
106. Implement octal Encoder using 74F148
107. Implement decimal Encoder using 74HC147
Post Lab Task:
Q1. Design 16x4 line Encoder using 74F148. Simulate and show results.
91
LAB 11
The Operation of Multiplexer
Group Number
Submitted by


Problem Analysis

Components:

Design
Obtained Marks
92
Objectives:
 To understand the functioning of multiplexer circuits.
 Designing and implementation of 4x1 Multiplexer using logic gates
 Implementing 8x1 multiplexer using digital IC 74LS151
Equipment Required:
1. 74LS04
2. 74LS08
3. 74LS32
4. 74LS151
Tools:
1. EPAL 27
2. Cutter
3. Single Core Wire
Theory:
A multiplexer is a device that has multiple inputs and one output. It also has data select
inputs, which permit digital data on any one of the inputs to be switched to the output
line. The multiplexer, shortened to “MUX” or “MPX”, is a combinational logic circuit
designed to switch one of several input lines through to a single common output line by
93
the application of a control signal. Multiplexers operate like very fast acting multiple
position rotary switches connecting or controlling multiple input lines called “channels”
one at a time to the output. A diagram below shows the basic working of multiplexer.
The multiplexers are also known as data selectors because they can “select” each input
line, are constructed from individual Analogue Switches encased in a single IC package
as opposed to the “mechanical” type selectors such as normal conventional switches
and relays.
Generally, the selection of each input line in a multiplexer is controlled by an additional

set of inputs called control lines and according to the binary condition of these control
inputs, either “HIGH” or “LOW” the appropriate data input is connected directly to the
output. Normally, a multiplexer has an even number of 2n data input lines and a
number of “control” inputs that correspond with the number of data inputs.
Note that multiplexers are different in operation to Encoders. Encoders are able to
switch an n-bit input pattern to multiple output lines that represent the binary coded
(BCD) output equivalent of the active input.
Multiplexer Symbol:
94
Logic Symbol:
4x1 Multiplexer:
4x1 Multiplexer has four data inputs I3, I2, I1 & I0, two selection lines s1 & s0and one
output Y.
Truth table:
Select lines Output

S1 S0 Y
0 0 I0
0 1 I1
1 0 I2
1 1 I3
Circuit diagram:
95
8x1 Multiplexer:
The 74LS151 has eight data inputs (D0-D7) and therefore three data select lines (S0-S2).
Three bits are required to select any one of the data inputs. A LOW on the Enable input
allows the selected data input data to pass through to the output. The pin diagram is
shown below.
Cascading Multiplexer:
The 74LS151 is 8x1 Mux. We can cascade two ic’s to design 16x1 Mux. To design 16x1
mux, the Enable pin is used the 4th select line (MSB bit). When the MSB select line is
Low, the IC1 is enabled and D0-D7 is selected at the output. When the select line is
HIGH, the IC2 is enabled and one of the data inputs D8-D15 is selected. The selected
input data are then passed through the OR gate to get single output
In Lab Task:
1. Implement 4x1 Mux in logic works/Proteus using logic gates
108. Implement 8x1 Mux using IC 74LS151
96
Q1. Design a 16x1 multiplexer using IC 74LS151
97

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Safety Measures

PREVENT ACCIDENTS: FOLLOW THIS ADVICE

2. Connect to the power source LAST.

8. All conducting surfaces intended to be at ground potential should be connected

BASIC ELECTRICAL SAFETY PRACTICES

12. Never put conductive metal objects into energized equipment.

23. Is the plug or outlet blackened by arcing?

24. Was liquid spilled on or around the equipment?

27. Does the equipment or the cord overheat when it is running?

If you observe any of these unsafe conditions:

Signature: __________________ Date: ______________

Student Name Registration Number

EEE241 Digital Logic Design Lab Manual

Rubrics for CLO#1 (PLO#1: Basic Engineering Knowledge) Marks

Mathematical and Scientific

1. AND: This operation is represented by a dot or by the absence of an operator. For

35.Logic works software

Before you power up the ePAL

- PIN3 +5V ---- 5A

- PIN5 +15V ---- 2A

- PIN4 -15V ---- 0.8A

- PIN1, 2 COMMON GND

III. Function Generator

IV. Seven Segment Display

VII. Breadboard Structure

Figure 1-1 Breadboards

The shaded lines indicate connected holes.

Key Functional Blocks of EPAL

Figure 1-3 74LS04 Inverter

Logic ICs types

74 Series 74 Series 74 Series

High-speed CMO High-speed CMOS TTL Low-power

Power Supply 3 to 15V 2 to 6V 5V ±0.5V 5V ±0.25V

Very high impedance.

Can give about Can give up to

Removing a chip from its holder

VIII. Building the Circuit

1. Turn the power off before you build anything!

Fig: 1-4: Logic Works Front End

Fig 1-5: Part Palette

1. Use Draw tool to join two pins

Fig 1-7: Post Lab Question 1

Fig 1-8: Post Lab Question 2

Q1: What are the ASCII, Access-3 and BCD codes?

Q1: Differentiate between Analog and Digital.

Student Name Registration Number

EEE241 Digital Logic Design Lab Manual

Rubrics for CLO#1 (PLO#1: Basic Engineering Knowledge) Marks

Mathematical and Scientific Terms:

Rubrics for CLO#2 (PLO#2: Problem Analysis) Marks

Identify/Define Lab Objectives

Hardware and software

Fig 2-1: Positive Logic

48. Single Core Wire

49. Pair of Strippers

X. To check the operation of OR gate according to the OR’s truth

XII. To check the

NOT’s truth table, using

XIII. To check the operation of NOR gate according to the NOR’s

It is a NOT-OR gate. It can be obtained by connecting a NOT gate in the output of an OR

It gives an output when it’s both inputs are 0.

XIV. To check the operation of NAND gate according to the

This gate gives an output high if either A or B or both are 0.

Signature: ____ Date: