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ABSTRACT

PCI Express is the third generation high performance I/O bus used to interconnect
peripheral devices in applications such as computing and communication platforms. PCI
Express is an all encompassing I/O device interconnect bus that has applications in the
mobile, desktop, workstation, server, embedded computing and communication platforms.

PCI Express on the other hand implements a serial, point-to-point type interconnect for
communication between two devices. Multiple PCI Express devices are interconnected via
the use of switches which means one can practically connect a large number of devices
together in a system. PCI Express transmission and reception data rate is 2.5 Gbits/sec.

A serial interconnect between two devices results in fewer pins per device package which
reduces PCI Express chip and board design cost and reduces board design complexity.
Communication over serial interconnect is accomplished using a packet based
communication protocol. Physical layer could be configured varying from 1- 32 lanes,
with each lane carrying a maximum Data rate of 2.5 Gbits/sec.

PCI Express protocol follows a layered structure similar to OSI model and contains
following four layers: Software layer, Transaction layer, Data link layer and Physical layer.
The project deals with design of Physical layer transmit lane controller which connects to
the link on one side and connects to the Data link on the other side. It essentially process
packets arriving from the Data link layer then converts them into serial bit stream.The bit
stream is clocked out at 2.5 Gbits/sec per lane.

Design, coding and synthesis is using Xilinx Software.

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CHAPTER 1. INTRODUCTION

1.1 INTRODUCTION TO PCI EXPRESS

PCI Express is the third generation high performance I/O bus used to interconnect
peripheral devices in applications such as computing and communication platforms. The
first generation buses include the ISA, EISA, VESA, and Micro Channel buses, while the
second generation buses include PCI, AGP, and PCI-X. PCI Express is an all
encompassing I/O device interconnect bus that has applications in the mobile, desktop,
workstation, server, embedded computing and communication platforms.

PCI Express supports chip-to-chip interconnect and board-to-board interconnect via cards
and connectors. PCI Express on the other hand implements a serial, point-to-point type
interconnect for communication between two devices. Multiple PCI Express devices are
interconnected via the use of switches which means one can practically connect a large
number of devices together in a system. A point-to-point interconnect implies limited
electrical load on the link allowing transmission and reception frequencies to scale to much
higher numbers. Currently PCI Express transmission and reception data rate is 2.5
Gbits/sec. A serial interconnect between two devices results in fewer pins per device
package which reduces PCI Express chip and board design cost and reduces board design
complexity. PCI Express performance is also highly scalable. This is achieved by
implementing scalable numbers for pins and signal Lanes per interconnect based on
communication performance requirements for that interconnect.

1.2 PURPOSE OF PROJECT

To improve bus performance, reduce overall system cost and take advantage of new
developments in computer design, the PCI Express architecture had to be significantly re-
designed from its predecessor buses. PCI and PCI-X buses are multi-drop parallel
interconnect buses in which many devices share one bus.

PCI Express on the other hand implements a serial, point-to-point type interconnect for
communication between two devices. Multiple PCI Express devices are interconnected via
the use of switches which means one can practically connect a large number of devices
together in a system. A point-to-point interconnect implies limited electrical load on the
link allowing transmission and reception frequencies to scale to much higher numbers.
Currently PCI Express transmission and reception data rate is 2.5 Gbits/sec. A serial
interconnect between two devices results in fewer pins per device package which reduces
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PCI Express chip and board design cost and reduces board design complexity. PCI Express
performance is also highly scalable. This is achieved by implementing scalable numbers
for pins and signal Lanes per interconnect based on communication performance
requirements for that interconnect.

SOME FEATURES OF PCI EXPRESS:

 Switches can be used to connect large number of PCI Express devices in a system.

 Serial communication over the interconnect uses packet based transactions, and
the PCI XP split transaction protocol.

 Quality Of Service (QoS) features provide differentiated transmission performance

for different applications. Hot Plug/Hot Swap support enables "always-on" systems.

 Advanced power management features allow one to design for low power mobile
applications. RAS (Reliable, Available, Serviceable) error handling features make
PCI Express suitable for robust high-end server applications.

 Hot plug, power management, error handling and interrupt signaling can all be sent.

 The configuration address space available per function is extended to 4KB,

allowing designers to define additional registers. However, new software is
required to access this extended configuration register space.

 In-band using packet based messaging rather than side-band signals, help in reduce
pin count and system cost.

 PCI – like card and connectors of various sizes are defined for PCI Express.

1.3 INTRODUCTION TO FUNCTIONING OF PCI EXPRESS

PCI Express interconnect consists of either a x1, x2, x4, x8, x12, x16 or x32 point-to-point Link. A
PCI Express Link is the physical connection between two devices. A Lane consists of signal pairs in
each direction. A x1 Link consists of 1 Lane or 1 differential signal pair in each direction for a total
of 4 signals. A x32 Link consists of 32 Lanes or 32 signal pairs for each direction for a total of 128
signals. The Link supports a symmetric number of Lanes in each direction. During hardware
initialization, the Link is initialized for Link width and frequency of operation automatically by the
devices on opposite ends of the Link. No OS or firmware is involved during Link level initialization.
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