EE-527:

EE 527: MicroFabrication

Photomask Design

R. B. Darling / EE-527 / Winter 2013

 Photomask Physical Construction Considerations
• Cost
• R l i
Resolution
• Critical dimension accuracy
• Wear / lifespan
• Illumination wavelength
• Plate-to-plate
p tolerances for multi-mask sets
• Printing method
• Thickness of the plate
• Flatness
• Temperature stability (thermal expansion coefficient)
• Mask polarity
R. B. Darling / EE-527 / Winter 2013
 Photomask Geometrical Design Considerations - 1
• Wafer size
• Di size
Die i
• Die array on wafer
• Device minimum feature size
• Layout grid size
• Manufacturingg ggrid size
• Floor planning
– Active device core and standard cell arrays
– Interconnect channels
– Bus ring for power distribution
– Pad frame and wire bonding scheme
– Thermal allowances & ESD/EOS protection
R. B. Darling / EE-527 / Winter 2013
 Photomask Geometrical Design Considerations - 2
• Physical layout design rules
• Alignment
Ali markers
k
– Layer-to-layer and cumulative
– Visual, coarse, fine, vernier
– Marker placement
• Proximity and density effects
• Process shrinks
h i k andd bloats
bl
• Corner compensation
• Process test patterns
• Diagnostic devices and probe pads
• Dicing and packaging fiducial marks
R. B. Darling / EE-527 / Winter 2013
 Photomask Materials
• Substrates:
– Soda lime glass: poor transmission, >8.9 ppm/C, n = 1.515
– B
Borosilicate
ili t glass
l (Pyrex):
(P ) 350 – 2000 nm, 3.25
3 25 ppm/C,
/C n = 1.474
1 474
– Quartz (fused silica, SiO2): 220 – 2000 nm, 0.55 ppm/C, n = 1.458
– Sapphire (Al2O3): 190 – 5000 nm, 5.3 ppm/C, n = 1.780
• Blocking layer: generally need an optical density (OD) > 4.0
40
– Fe2O3 (least expensive)
– Cr (best finish and uniformity)
• Standard mask plate thicknesses for the Oriel aligners:
– 4-inch square mask plate: 0.062 inches
– 5-inch square mask plate: 0.093 inches
• Pellicles: used only for projection systems
• Master versus daughter plates, polarity reversals, mirror reversals
• Transparency films:
– Overhead xerox transparencies using toner: forget it – they don
don’tt work!
– Professional phototransparencies: need emulsion coatings for OD > 3.0
R. B. Darling / EE-527 / Winter 2013
 Photomask Fabrication
• Photoplotter
– Least expensive: ~$250/plate
$250/plate
– Aperture wheel (Gerber style) with vectored flashes
– Used most commonly in the PCB industry
– Resolution down to ~25 microns = 1 mil
• Direct-write laser
– Intermediate cost: ~$350 to $650/plate
– Vector pattern generation
– Resolution down to ~2.5 microns
• Direct-write e-beam
– Most expensive:
M i ~$2500/plate
$2500/ l (entry
( level)
l l) + beam
b time
i charge
h
– The Etec MEBES system was the original, MEBES-IV is current
– Raster scan with vectored subfields; field stitching requirements
– R l i down
Resolution d to ~20
20 nm
R. B. Darling / EE-527 / Winter 2013
 Example: EE-527
EE 527 Mask Set M3 (5
(5-mask
mask set)

(3-inch wafer)
R. B. Darling / EE-527 / Winter 2013
 Example: EE-527
EE 527 Mask Set M4 (6
(6-mask
mask set)

(100 mm wafer)
R. B. Darling / EE-527 / Winter 2013
 Photomask Design Fundamentals
• Always laid out on a grid:
– usually 1 nm for ICs,
ll 1 m for
– usually f PCBs;
PCB
– sometimes 1 mil for PCBs (English units)!
• Always created in a layer-based hierarchy
• Fundamental shapes:
– Boxes (rectangles)
– Polygons: orthogonal, 45-degree, all-angle
– Wires (lines of fixed width): orthogonal, 45-degree, all-angle
– Curved lines must be synthesized from straight line segments!
• Standard output file formats in use:
– CIF: Caltech Intermediate Format (not used much any more)
– GDS-II: Graphical Database System – II (IC industry standard)
– DXF: Drawingg Exchangeg Format (AutoCAD)
( )
– NOTE: Visio, PowerPoint, Corel Draw, etc. are not suitable formats…
R. B. Darling / EE-527 / Winter 2013
 Photomask Layers
• Drawn layers
– Contain
C t i the
th native
ti physical
h i l layout
l t information:
i f ti
• Physical process features: metals, vias, poly, contacts, n+, p+, etc.
• Device and area identifications: resistors, capacitors, diodes, etc.
• Utility layers
– Contain constructions used to assist in the layout:
• ggrid points,
p , origins,
g , rulers,, labels,, not-exists,, keep-ins,
p , keep-outs
p
• Derived layers
– Are computed from other layers using image morphology
operations: AND
AND, OROR, NOT
NOT, GROW,
GROW SHRINK
– Used for creating and adjusting layers for photomask fabrication
– Used for design validation tools: design rule checks, circuit and
parasitic
i i extraction,
i connectivity
i i checks,
h k etc.
R. B. Darling / EE-527 / Winter 2013
 Photomask Design Layer Setup
• Example for the EE-527 M3 mask set:

Mask Layer Layout Process Polarity Alignment

Number Name Color Type
1 Contact etch dark field

2 Metal1 deposit + dark field

liftoff
3 Via etch dark field

4 Metal2 deposit + dark field

liftoff
5 Overglass etch dark field

R. B. Darling / EE-527 / Winter 2013

 Photomask Design Layer Setup
• Example for the EE-527 M4 mask set:
Mask Layer Layout Process Polarity Alignment
Number Name Color Type
1 Align etch dark field

2 PDiff etch + dark field

diffuse
3 NDiff etch
t h+ d k fi
dark field
ld
diffuse
4 Active etch dark field

5 Contact etch dark field

6 Metal1 deposit + dark field

liftoff R. B. Darling / EE-527 / Winter 2013
 Mask Polarity
• Bright field: drawn features are opaque – easy to align
– Make the alignment cross hairs are smaller than the wafer targets.
• Dark field: drawn features are transparent – requires building in
windows for alignment
– Make the alignment cross hairs are larger than the wafer targets.
Bright field mask cross hairs Dark field mask cross hairs

Alignment target on wafer

R. B. Darling / EE-527 / Winter 2013
 Misalignment

• Different views for bright field versus dark field:

– In both cases, the mask (in yellow) is shifted up and to the right:

Bright field mask cross hairs Dark field mask cross hairs

Alignment target on wafer

R. B. Darling / EE-527 / Winter 2013
 Wafer Alignment Mark Targets and Cross Hairs
• Coarse: 50 m targets with 100 m cross hairs
• Fine: 10 m targets with 20 m cross hairs
• Usually adequate for contact alignment to within ±1 µm.

R. B. Darling / EE-527 / Winter 2013

 Verniers to Measure Alignment Accuracy
Pitch of vernier ticks is increased by 5 µm (coarse) and 2 µm (fine) from mating ticks on the prior mask.
By finding the pair of mating ticks which matches best, the alignment error can be determined to ±0.5 µm.

R. B. Darling / EE-527 / Winter 2013

 EE-527
EE 527 M4 Mask Set: Visual Alignment Keys
North
NE
marker
The NE marker
guarantees that the mask
and wafer are not
accidentally rotated by 90
degrees.

West East

Visual alignment keys are

usually the largest open
feature in a dark-field mask
and very useful for making
sure the wafer is roughly
aligned to the mask before
using the microscope for South
the finer adjustments.
R. B. Darling / EE-527 / Winter 2013
 Process Diagnostics
• Each mask set should provide test structures by which to troubleshoot
problems and monitor the fabrication process.
• Process diagnostics:
– photoresist tuning: prebake / exposure / development
– doping levels: sheet resistance
– metal conductivity: sheet resistance and tempco
– MOS oxide: field-effect, threshold voltage, trapping: MOS capacitors
– interlevel dielectric breakdown strength and capacitance: MIM capacitors
– via reliability and resistance: via chains
– contact reliability and resistance: contact chains
• Device diagnostics:
– test
t t transistors,
t it diodes,
di d or sub-circuits
b i it
• variable gate widths
• variable gate lengths
• ring oscillator
• pn-junction diode I-V and leakage
• Schottky diode I-V and leakage R. B. Darling / EE-527 / Winter 2013
Process Diagnostic: Photoresist Line/Space Patterns

Proper
p p prebake,, exposure,
p , and
development should produce a
50:50 line and space pattern.

This pattern is usually easy to

tune with an optical
microscope and avoids the
need for using an SEM.

R. B. Darling / EE-527 / Winter 2013

 Process Diagnostic: 44-Point
Point Resistivity (Substrate)
• 100 m dia. contacts, 1000 m and 500 m spacings:

Diagnostic Probe Pads :

800 m x 800 m square,
1250 
m p
pitch,,
approx. = 0.050 in pitch,
designed for use with a
standard 4-point probe
head.
head
The photolithographically
defined contacts provide a
much higher accuracy 4-
point probe measurement
than most commercial 4-
point probe heads!

R. B. Darling / EE-527 / Winter 2013

 Process Diagnostic: 44-Point
Point Resistivity (Diffusions)
• Test bars of different doped regions, 200 µm wide.

Diagnostic Probe Pads :

1000 m x 1000 m
square,
2000 m pitch.
It is designed for use with
a standard 5-point pogo
pin test head:
4-wire Kelvin resistance
measurement with a
separate substrate
ground connection.
Bar contacts are 40 µm
square, 1 x 2 array
Substrate contacts are
50 µm round.
round

R. B. Darling / EE-527 / Winter 2013

 Process Diagnostic: Metal Sheet Resistance
• 2751 squares in M1; same pattern also for M2:

R. B. Darling / EE-527 / Winter 2013

Process Diagnostic: Interlevel Dielectric Capacitors
• radius = 1175 m, overlap area = 4.3374 mm2:

R. B. Darling / EE-527 / Winter 2013

 Process Diagnostic: M1
M1-Via-M2
Via M2 Chains
• 1080 (30 x 36) vias (20 m sq.) in series, 2 instances:

This is also a stringent test of via yield!

R. B. Darling / EE-527 / Winter 2013
Process Diagnostic: Interconnect Resistances
Upper three test structures
provide a 4-wire Kelvin
resistance measurement of
2 contacts (20 µm sq. ea.)
plus three different lengths
of n-type diffusion.

These three
Th th resistance
i t
measurements can be used
to extract the resistance of
each contact and the sheet
resistance of the n-type
yp
diffusion.

The lower structure

provides a measurement of
the sheet resistance of
Metal1 using 3690 squares.

R. B. Darling / EE-527 / Winter 2013

Process Diagnostics: Example SOS-CMOS
SOS CMOS Development
• Developed at Stanford University over 1997-1998
• High voltage process for charge pumps , HV actuators
actuators, and photodiodes
• 20.0 x 7.6 mm die; about half of the die is process diagnostics

R. B. Darling / EE-527 / Winter 2013

 Bonding Pads
• Note: Bonding pads do not scale with Moore’s Law!
– A bond wire is still the same diameter as it has always been.
• Size is dictated by the bonding technology:
– 100 m sq. is large and generous, and allows at least 2 tries with either
gold ball or aluminum wedge bonders.
– 50 m sq. is about the smallest practical for commercial ICs.
– 200 m sq. is used in the EE-527 masks.
• Probe pads may also be used:
– Size depends upon the probe station.
– 50 m is good for general research.
– 25 m is reasonable with high end probes.
• Pogo pin pads: (huge!)
– 200 to 1000 µm for wafer contact points.
– Not common, but useful for R&D.
– Good for very fast, low cost wafer testing.
R. B. Darling / EE-527 / Winter 2013
 Bonding Pad Construction
• Generally want as much metal as possible underneath a bond pad.
– Use all available metal layers.
– Use
U single
i l large
l vias
i between
b metall layers.
l
– This may violate some design rules (e.g. exact via size).
• Make vias generously smaller than the metal pads to hem the edges.

A hemmed edge helps keep the metal from

lifting during bond wire attachment. R. B. Darling / EE-527 / Winter 2013
EE-527
EE 527 M3 Mask Set Die Layout and Pad Frame
4.00 mm sq. die
2.40 mm sq. core area
32-pad frame (8 x 8 quad)
200 m sq. pads
300 m pad pitch
di i fid
dicing fiducial
i l marks
k on edges
d
50 m dicing streets
alignment validation markers
l
logos iin corners

R. B. Darling / EE-527 / Winter 2013

 Pad Frame: Example Active Cilia Array Chip
• Developed at Stanford University over 1996-1997
• Standford Quick-MOS process + 5 thermal bimorph MEMS layers

R. B. Darling / EE-527 / Winter 2013

 Design Rules
• Design rules are geometrical rules that can be applied to
the layers of a physical layout to insure manufacturability
of the design and function of the devices.
g rule dimensions:
• Design
– Absolute: e.g. microns or mils
– Scalable: e.g. lambdas which change with the technology node
• Each design rule is applied to either:
– Within a single layer, or
– Between two layers.
• Exception cases can be prescribed:
– intersections
– coincidences
– acute angles R. B. Darling / EE-527 / Winter 2013
 Automatic Design Rule Checking
• Software suites for IC and PCB layout include
subprograms for checking design rules,
rules either in a batch
mode or interactively.
• These are known as DRC tools, and theyy reportp back any y
violations of a rule within the specified test region.
• Examples:
– Cadence
C d Virtuoso
Vi t / Assura
A DRC
– Mentor Graphics Layout DRC
– Tanner L-Edit DRC
– Cadence OrCAD PCB Editor
– Altium Designer PCB Editor

R. B. Darling / EE-527 / Winter 2013

 Design Rule Types
• DRC rules: can be checked automatically through layers
– Minimum Width
– Exact Width
– Spacing
– Surround
– Overlap
– Extension
– Density
– Not Exist
• Other design rules:
– Off grid objects
– Pad frame allowances and restrictions
– ESD/EOS
/ device
d i allowances
ll andd restrictions
i i
R. B. Darling / EE-527 / Winter 2013
 Example: Minimum Width Rule

• Rule 2.1: Metal1 minimum width = 5.0 m

5 0 m,
5.0 m minimum

R. B. Darling / EE-527 / Winter 2013

 Example: Exact Width Rule

• Rule 3.1: Via exact width = 5.0 m

5.0 m, exactly

R. B. Darling / EE-527 / Winter 2013

 Example: Spacing Rule

• Rule 2.2: Metal1 to Metal1 spacing = 5.0 m

• Rule
R l 4.2:
4 2 Metal2
M l2 to Metal2
M l2 spacing 5 0 m
i = 5.0
• Rule 4.3: Metal2 to Metal1 spacing = 5.0 m
– Exceptions: coincident or intersection

5.0 m, minimum

5.0 m, minimum

5.0 
m, minimum

R. B. Darling / EE-527 / Winter 2013

 Example: Surround Rule

• Rule 3.3: Via surrounded by Metal1 by 5.0 m

5.0 
m, minimum

R. B. Darling / EE-527 / Winter 2013

 Mask Alignment Errors
• The average alignment error between the target and the crosshair is
Δxalign. This is a function of the aligner and the operator.
• E
Even with
ith perfect
f t alignment
li t in
i one place
l on the
th wafer,
f other
th places
l
may run out and be misaligned if the mask features do not register
properly to the existing features across the entire wafer.
• Th mask-to-mask
The kt k run outt is
i Δx
Δ runout and
d thi
this is
i proportional
ti l tot the
th
distance between the two points being examined: Δxrunout = k·L.
– For step-and-repeat systems, L is the die or reticle size.
– For
F contact
t t aligners,
li L is
i the
th size
i off the
th wafer.
f
• The greatest contributor to Δxrunout is thermal expansion mismatches
between the mask plate and the wafer:
– k = (CTE
(C wafer – CTE
C mask)(T)( exposure1 – Texposure2)
– CTE = coefficient of thermal expansion: ΔL/L = CTE·ΔT [ppm/C].
• The temperature of an exposure system must be very closely controlled
to avoid
id this.
hi Typical
T i l optical
i l steppers operate within
i hi environments
i
that are controlled to better than ±0.2C. R. B. Darling / EE-527 / Winter 2013
 Critical Dimension Errors
• A critical dimension (CD) is a specified distance between two points
on a mask which is used to guarantee mask-to-mask
mask to mask registration.
• The simplest CD is the distance between the two primary alignment
marks on opposite sides of the mask.
• Specifying a CD will add cost to a mask set,
set but all professional
quality masks will have these, and the will place an upper bound on the
mask-to-mask registration errors, ΔxCD.
• Note that exposing through a mask at a temperature different from
what it was manufactured will change the CD value.
• CD values are always specified at a given temperature, usually 25C.
• O l extension
Overlap, t i andd surroundd design
d i rules
l mustt generallyll be
b greater
t
than or equal to the sum of the alignment errors to insure electrical
integrity (no shorts or opens):
• Δ rule > Δx
Δx Δ align + Δx
Δ runout + Δx
Δ CD.
R. B. Darling / EE-527 / Winter 2013
 Using Mask Sets Effectively for R&D
• Mask sets are generally more effective when
professionally produced, but this adds more cost.
• The investment in design and layout time should be offset
by a mask set which covers as much ground as possible.
• Approaches:
A h
– Splits: Use different subsets of the same mask set to support
several slightly different, but largely common process flows.
– Options: Add a few additional masks for optional process steps to
increase the overall versatility of the mask set.
– Cells: Fabricate standard cells that are already tested and
interconnect them differently using only the last metal mask.
– Multiproject: (MPW) Include several different project die within
the same mask set if the process flow can support them
simultaneously.
R. B. Darling / EE-527 / Winter 2013
EE-527
EE 527 M3 Mask Set: Fuse Die

R. B. Darling / EE-527 / Winter 2013

EE-527
EE 527 M3 Mask Set: MSM Die

R. B. Darling / EE-527 / Winter 2013

EE-527
EE 527 M3 Mask Set: Inductor Die

R. B. Darling / EE-527 / Winter 2013

EE-527
EE 527 M3 Mask Set: Circular Capacitor Die

R. B. Darling / EE-527 / Winter 2013

EE-527
EE 527 M3 Mask Set: Square Capacitor Die

R. B. Darling / EE-527 / Winter 2013

EE-527
EE 527 M3 Mask Set: Circular Diode Die

R. B. Darling / EE-527 / Winter 2013

EE-527
EE 527 M3 Mask Set: Square Diode Die

R. B. Darling / EE-527 / Winter 2013

EE-527
EE 527 M4 Mask Set: Hall Effect / Van der Pauw

R. B. Darling / EE-527 / Winter 2013

EE-527
EE 527 M4 Mask Set: Hall Effect / Van der Pauw

R. B. Darling / EE-527 / Winter 2013

EE-527
EE 527 M4 Mask Set: Lateral pin Diode

n+ exterior:
e terior 100 µmm sq
square
are
p+ interior: 160 µm square
R. B. Darling / EE-527 / Winter 2013
 EE-527
EE 527 M4 Mask Set: npn BJT
C (sub)

E B

AE = 40 µm x 40 µm

R. B. Darling / EE-527 / Winter 2013

EE-527
EE 527 M4 Mask Set: MOS C-V
C V Test Capacitors

R. B. Darling / EE-527 / Winter 2013

 EE-527
EE 527 M4 Mask Set: pp-channel
channel MOSFET
G B
W = 10 µm
L = 10 µm

D S

R. B. Darling / EE-527 / Winter 2013

EE-527
EE 527 M4 Mask Set: Large Area Photodiode

R. B. Darling / EE-527 / Winter 2013

EE-527
EE 527 M4 Mask Set: Quad Photodiode

R. B. Darling / EE-527 / Winter 2013

EE-527
EE 527 M4 Mask Set: 10
10-Element
Element Photodiode Array

R. B. Darling / EE-527 / Winter 2013