Approximate 8-point FFT using Radix-2 Booth

multiplier

Avinash.Y
EDM16B038
Project Guide: Noor Mahammad Sk

IIITDM KANCHEEPURAM

C.S. Ramalingam
Avinash.Y (EE Dept., IIT) Madras)
(IIITDM KANCHEEPURAM Intro to FFT 24 May. 2020 1 /16 1 / 30
 The Discrete Fourier Transform (DFT)

• DFT of an N-point sequence xn, n = 0, 1, 2, . . . , N − 1 is defined

as

• As N-point sequence yields an N- point transform

•Xk can be expressed as an inner product:

C.S.
Avinash.Y
Ramalingam
Avinash.Y (IIITDM
(IIITDM (EEKANCHEEPURAM
Dept., IIT) Madras)
KANCHEEPURAM ) Intro
Intrototo
FFTFF
FFT 24 May 2020 16th2 /Mar.
16 20202/ 212 / 30
 The Discrete Fourier Transform (DFT)
Notation: WN = e−j 2∏/N . Hence,

By varying k from 0 to N − 1 and combining the N inner

products, we get the following:

X = Wx

W is an N × N matrix, called as the “DFT Matrix”

C.S.
Avinash.Y
Ramalingam
(IIITDM(EE
KANCHEEPURAM
Dept., IIT Madras)
) Intro to FFT 24 May. 2020 3 /16 3 / 30
 The DFT Matrix

W=

The notation WN is used if we want to make the size of the

DFT matrix explicit
Hence, the number of complex multiplications is N2 − 2N + 1,
i.e.,( N − 1)2
Each inner product requires N − 1complex additions
There are N inner products
Hence we require N(N − 1)complex additions
C.S.
Avinash.Y
Ramalingam
(IIITDM(EE
KANCHEEPURAM
Dept., IIT Madras)
) Intro to FFT 24 May. 2020 4 /16 4 / 30
 The Divide and Conquer Approach

Suppose N is even and we split the sequence into two halves.

Each sequence has N/2 points
N
Suppose we compute the point DFTof each sequence
2
Multiplications : 2×(N/2)2 = N2 /2

Let N = 8
Straight forward implementation requires, approximately,64
multiplications

The “divide and conquer” approach requires, approximately,

2 × (8/2)2 + overhead, i.e.,32 + overhead multiplications

C.S.
Avinash.Y
Ramalingam
(IIITDM(EE
KANCHEEPURAM
Dept., IIT Madras)
) Intro to FFT 24 May. 2020 5/16 5 / 30
 The Decimation in Time (DIT) Algorithm
From {xn} form two sequences as follows:

{gn} = {x2n} {hn} = {x2n+1}

{gn} contains the even-indexed samples, while {hn} contains
theodd-indexed samples
The DFT of {xn} is

Xk =

C.S.
Avinash.Y
Ramalingam
(IIITDM(EE
KANCHEEPURAM
Dept., IIT Madras)
) Intro to FFT 24 May. 2020 6/16 6 / 30
 The Decimation in Time (DIT) Algorithm

But,
2π 2π
−j (rk)
W N2rk = e −j N
(2rk)
=e N/2 rk
= W N/2
and hence

N N
2 −1 rk k 2 −1 rk
Xk = Σ gr W N/2 +W N Σ hr W N/2
r=0 r=0
= Gk + W Nk Hk k = 0, 1, . . . , N − 1

N
{Gk} and { H k} are 2 point DFTs

Theoverheadfor combining the two N2 point DFTs is the

multiplicative factor WNk for k = 0, 1, . . . , N − 1

W Nk is called “twiddle factor”

C.S.
Avinash.Y
Ramalingam
(IIITDM(EE
KANCHEEPURAM
Dept., IIT Madras)
) Intro to FFT 24 May. 2020 7/16 7 / 30
 Butterfly Diagram

Gk Xk

Hk X k +N
−W k 2
N

Xk = Gk WNk Hk
k+ N
Xk+N = Gk+ N + WN 2 Hk+N
2 2 2
= G k− Wk H k
N

C.S.
Avinash.Y
Ramalingam
(IIITDM(EE
KANCHEEPURAM
Dept., IIT Madras)
) Intro to FFT 24 May. 2020 8/16 8 / 30
 DIT Flowgraph for N = 8

C.S.
Avinash.Y
Ramalingam
(IIITDM(EE
KANCHEEPURAM
Dept., IIT Madras)
) Intro to FFT 24 May. 2020 9/16 9 / 30
 Input Sequence Order

Recall that, for N = 8, the first split requires the data to be

arranged as follows:
x0, x2, x4, x6, x 1 , x 3 , x 5 , x7
In the second and final split, the data appear in the following
order:
x0, x4, x2, x6, x1, x5, x 3 , x7
The final order is said to be in “bit reversed” form:
Original Binary Form Reversed Form Final
0 000 000 0
1 001 100 4
2 010 010 2
3 011 110 6
4 100 001 1
5 101 101 5
6 110 011 3
7 111 111 7

C.S.
Avinash.Y
Ramalingam
(IIITDM(EE
KANCHEEPURAM
Dept., IIT Madras)
) Intro to FFT
FF 24 May. 2020 10 /16 10 / 30
 In FFT butterfly unit is the basic unit which contains components like
multipliers and adders.
Implementing these components plays a very tough role in designing of
butterfly structure.

•What is a Booth multiplier ?

•What made Booth multiplier so special when compared to normal
multiplication ?
Booth's algorithm is a multiplication algorithm that multiplies two signed
binary numbers in 2's compliment notation.

Radix-2 Booth multiplier:-.

To explain what is a Radix 2 Booth multiplier that best way to explain

through consider an example.
A Radix-2 Booth multiplier is used for reduce the number of multiplication
by making the multiplicand containing more number of Zeroes.

C.S.
Avinash.Y
Ramalingam
(IIITDM(EE
KANCHEEPURAM
Dept., IIT Madras)
) 24 May. 2020 11/16 11 / 30
 Example for Radix-2 multiplication:-

Partial Products

C.S.
Avinash.Y
Ramalingam
(IIITDM(EE
KANCHEEPURAM
Dept., IIT Madras)
) 24 May. 2020 12 /16 12 / 30
 RTL schematic view in Xlink software
Here the total number
of cell usage and
number of inputs and
outputs and number
of LUT’s are obtained
from the Xlink
software

C.S.
Avinash.Y
Ramalingam
(IIITDM(EE
KANCHEEPURAM
Dept., IIT Madras)
) Intro to FFT 24 May. 2020 13/16 13 / 30
 8-point schematic view in Cadence software:-

The required area , power and delay are obtained from cadence software.

Further, Wallace tree is used to reduce the delay in design and to compute the partial
products (PP). These computed values are added by using Kogge stone adder which
carry and sum are generated in after some delay.
C.S.
Avinash.Y
Ramalingam
(IIITDM(EE
KANCHEEPURAM
Dept., IIT Madras)
) Intro to FFT 24 May. 2020 14 /16 14 / 30
 Results:-
The required results for proposed architecture:-
For the gate level behaviour the obtained area, power and delay are

AREA :- 4.176(µm^2)
POWER :- 1310.09(µw)
DELAY:- 2300.40(ps)
Device = spartan-5

The required number of LUT’s = 752

Total cell usage are = 1297
Total number of inputs and outputs are = 264

These results are from the existing research paper:-

C.S.
Avinash.Y
Ramalingam
(IIITDM(EE
KANCHEEPURAM
Dept., IIT Madras)
) Intro to FFT 24 May. 2020 15/16 15 / 30
 References.

[1] H. Jiang, J. Han, F. Qiao, and F. Lombardi, “Approximate radix-8 booth

multipliers for low-power and high-performance operation,”IEEE Transactions on
Computers,vol. 65, no. 8, pp. 2638–2644, 2015

[2] J.-P. Wang, S.-R. Kuang, and S.-C. Liang, “High-accuracy fixed-width modified
booth multipliers for lossy applications,”IEEE transactions on very large scale
integration(VLSI) systems, vol. 19, no. 1, pp. 52–60, 2009
[3] C.-Y. Li, Y.-H. Chen, T.-Y. Chang, and J.-N. Chen, “A probabilistic estimation
biascircuit for fixed-width booth multiplier and its dct applications,”IEEE
Transactionson Circuits and Systems II: Express Briefs, vol. 58, no. 4, pp. 215–219,
2011
[4] Y.-H. Chen, C.-Y. Li, and T.-Y. Chang, “Area-effective and power-efficient fixed-
widthbooth multipliers using generalized probabilistic estimation bias,”IEEE
Journal onEmerging and Selected Topics in Circuits and Systems, vol. 1, no. 3, pp.
277–288,2011.

C.S.
Avinash.Y
Ramalingam
(IIITDM(EE
KANCHEEPURAM
Dept., IIT Madras)
) Intro to FFT 24 May. 2020 16 /16 16 / 30