Professional Documents
Culture Documents
Embedded Microprocessor System Design Using Fpgas
Embedded Microprocessor System Design Using Fpgas
FPGAs
Uwe Meyer-Baese
Embedded Microprocessor
System Design using FPGAs
Uwe Meyer-Baese
Tallahassee, FL, USA
This Springer imprint is published by the registered company Springer Nature Switzerland AG
The registered company address is: Gewerbestrasse 11, 6330 Cham, Switzerland
To
Anke, Lisa, and my Parents
Preface
Embedded microprocessor systems are everywhere, just look around you. You will
find them in your cellular phones, digital clocks, GPS, video recorder, and internet
router as well as in household electronic entertainment devices. A modern car typi-
cally uses 50–100 microprocessors. Embedded systems are often resource-limited
by price, power dissipation, memory, or storage. A general-purpose computer typi-
cally uses up hundreds of watts, while a clock or remote control only consumes in
microwatts to be able to run for a year on a single AAA battery. Although many
embedded systems require low-power dissipation, the implemented algorithms,
like the error turbo correction coding used in UMTS phones, are computational
demanding. Nevertheless, today, embedded processors perform sophisticated task
and run these complex algorithms. The microprocessors in a car use an estimated
100 million lines of code, the GPS and radio alone account for 20 million lines
of code.
FPGAs are the best choice to start with embedded system design space explora-
tion since these are fine grain logic programmable COTS devices with much lower
NRE costs than cell-based systems available today. The newest generation of
FPGA boards and devices allow to design microprocessor systems using soft,
parameterized, or hardcore microprocessor all with the same board. These boards
are great starting points for many designs since they also have a substantial number
of peripheral components such as Audio CODEC, Video HDMI connector, or SD
cards. It would be very time consuming to include these components in your proj-
ect if using a non-FPGA, standard COTS microprocessor system.
At the beginning of the second decade of the twenty-first century, we find that
the two programmable logic device (PLD) market leaders (Altera/Intel and Xilinx)
both report revenues greater than US$2 billion. FPGAs have enjoyed steady growth
of more than 20% in the last decade, outperforming ASICs and PDSPs by 10%.
This comes from the fact that FPGAs have many features in common with ASICs,
such as reduction in size, weight, and power dissipation; higher throughput; better
security against unauthorized copies; reduced device and inventory cost and
reduced board test costs; and claim advantages over ASICs, such as a reduction in
development time (rapid prototyping), in-circuit (re)programmability, and lower
vii
viii Preface
NRE costs, resulting in more economical designs for solutions requiring less than
1000 units. Another trend in the hardware design world is the migration from
graphical design entries to hardware description language (HDL). It has been
found that “code reuse” is much higher with HDL-based entries than with graphi-
cal design entries. There is a high demand for HDL design engineers and we
already find undergraduate classes teaching logic design with HDLs. Unfortunately,
only two HDL languages are popular today. The US West Coast and Asia area
prefer Verilog, while US East Coast and Europe more frequently use VHDL. For
embedded microprocessor design with FPGAs both languages seem to be well
suited, although some VHDL examples are a little easier to read because of the
supported fixed and floating-point data type in VHDL-2008. Other constraints may
include personal preferences, EDA library and tool availability, readability, capa-
bility, and language extensions using PLIs as well as commercial, business, and
marketing issues, to name just a few. Tool providers acknowledge today that both
languages must be supported, and this book covers examples in both design lan-
guages. We are now fortunate that “baseline” FPGA tools are available from dif-
ferent sources at essentially no cost for educational use. We take advantage of this
fact in this book. It includes code for Altera/Intel Quartus 15.1 Lite Edition as well
as Xilinx Vivado 2016.4 tools, which provides a complete set of design tools, from
a content-sensitive editor, microprocessor configurator, compiler, and simulator to
a bitstream generator. All examples presented are written in VHDL and Verilog
and should be easily adapted to other propriety design-entry systems.
The book is structured as follows. The first chapter starts with a snapshot of
today’s microprocessors and basic microprocessor principles in general and
FPGA-based microprocessors in particular. It also includes an overview on design
with IP blocks and a PLL IP core design example. The second chapter discusses
devices, boards, and tools used to design state-of-the-art FPGA systems. It dis-
cusses a detailed case study of the ultimate RISC (URISC) microprocessor,
including model discussion, compilation steps, simulation, performance evalua-
tion, power estimation, and floor planning using Quartus and Vivado. This case
study is the basis for many other design examples in subsequent chapters. Chapters
3 and 4 deal with VHDL and Verilog language elements that are used in the
microprocessor design. Chapter 5 reviews the ANSI C language and also dis-
cusses debug methods and differences to C++. In Chap. 6, software tool develop-
ment for microprocessors is presented. We will cover lexical analysis using GNU
Flex and parser implementation with GNU Bison. We will design an assembler
for PicoBlaze microprocessor and a basic and full featured C compiler for a
3-address machine. Instruction set simulator and SW debugger are discussed too.
In Chap. 7, the softcore PicoBlaze is developed in a step-by-step fashion adding
more and more architecture features. Loop control and data memory design are
studied and implemented in HDL. The whole instruction set of the most popular
8-bit FPGA-based microprocessor is then fully discussed in Chap. 8. The Chaps.
9 and 10 discuss the two most popular parameterized core for Altera/Intel and
Xilinx devices called Nios II and MicroBlaze, respectively. We will develop a
top-down and a bottom-up system design approach. Adding custom IP to the
Preface ix
Acknowledgments
publisher (Springer-Verlag) I would like to thank Charles Glaser and Dr. Merkle
for their continuous support and help over recent years.
If you find any errata or have any suggestions to improve this book, please con-
tact me at Uwe.Meyer-Baese@ieee.org or through my publisher.
April 2020
Contents
xi
xii Contents
Index������������������������������������������������������������������������������������������������������������������ 505