 

 Johnson Counter (/verilog/verilog-johnson-counter)

  Mod-N Counter (/verilog/verilog-modn-counter)

  Gray Counter (/verilog/verilog-gray-counter)

  Misc

  n-bit Shift Register (/verilog/verilog-n-bit-shift-register)

  Priority Encoder (/verilog/verilog-priority-encoder)

  4x1 multiplexer (/verilog/verilog-4to1-mux)

  Full adder (/verilog/verilog-full-adder)

  Single Port RAM (/verilog/verilog-single-port-ram)

D Flip-Flop Async Reset

A D flip-flop is a sequential element that follows the input pin

d at the given edge of a clock.

Design #1: With async active-low reset

1 module dff ( input d,

2 input rstn,

3 input clk,

4 output reg q);

6 always @ (posedge clk or negedge rstn)

7 if (!rstn)

8 q <= 0;
9 else

10 q <= d;

11 endmodule

Hardware Schematic
(/images/verilog/schematic/dff_async_reset_schematic.png)

Testbench

1 module tb_dff;

2 reg clk;

3 reg d;

4 reg rstn;

5 reg [2:0] delay;

7 dff dff0 ( .d(d),

8 .rsnt (rstn),

9 .clk (clk),

10 .q (q));

11

12 // Generate clock

13 always #10 clk = ~clk;

14

15 // Testcase

16 initial begin

17 clk <= 0;
18 d <= 0;

19 rstn <= 0;

20

21 #15 d <= 1;

22 #10 rstn <= 1;

23 for (int i = 0; i < 5; i=i+1) begin

24 delay = $random;

25 #(delay) d <= i;

26 end

27 end

28 endmodule
Design #1: With sync active-low reset

1 module dff ( input d,

2 input rstn,

3 input clk,

4 output reg q);

6 always @ (posedge clk)

7 if (!rstn)

8 q <= 0;
9 else

10 q <= d;

11 endmodule

Hardware Schematic

(/images/verilog/schematic/dff_sync_reset_schematic.png)

Testbench
1 module tb_dff;

2 reg clk;

3 reg d;

4 reg rstn;

5 reg [2:0] delay;

7 dff dff0 ( .d(d),

8 .rsnt (rstn),

9 .clk (clk),

10 .q (q));

11

12 // Generate clock

13 always #10 clk = ~clk;

14

15 // Testcase

16 initial begin

17 clk <= 0;
18 d <= 0;

19 rstn <= 0;

20

21 #15 d <= 1;

22 #10 rstn <= 1;

23 for (int i = 0; i < 5; i=i+1) begin

24 delay = $random;

25 #(delay) d <= i;

26 end

27 end

28 endmodule