Department of Electrical Engineering

Faculty Member: DR. REHAN AHMED Dated: 18 – 03 – 2021

Semester: 6th Section: BEE-10A,B

EE-421: DIGITAL SYSEM DESIGN

Lab 2: Switches, Lights and Multiplexers
Name Reg. No Viva / Analysis Modern Ethics Individual
Quiz / Lab of data Tool and and Team
Performa in Lab Usage Safety Work
nce Report

5 Marks 5 Marks 5 Marks 5 Marks 5 Marks

MAHAD WASIQUE 243375

AHMED ALI 245965

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Objectives:

The purpose of this exercise is to learn how to connect simple input and output devices
to an FPGA chip and implement a circuit that uses these devices. We will use the
switches on the DE-series boards as inputs to the circuit. We will use light emitting
diodes (LEDs) and 7-segment displays as output devices.

Introduction:

Verilog (HDL) - Standardized as IEEE 1364, is a hardware description language (HDL)

used to model electronic systems. It is most commonly used in the design and
verification of digital circuits at the register-transfer level of abstraction. It is also used in
the verification of analog circuits and mixed-signal circuits, as well as in the design
of genetic circuits.

Quartus Prime (Software) - The Intel® Quartus® Prime software GUI supports easy
design entry, fast design processing, straightforward device programming, and
integration with other industry-standard EDA tools.

The Intel® Quartus® Prime Standard Edition software offers a full range of
features some of which are following:

• Design Planning Tools — plan for initial I/O pin layout, power consumption, and
area utilization in the Early Power Estimator, the Power Analyzer Tool, and the
Pin Planner. Refer to Design Planning for more information.
• Design Constraint Entry — specify timing, placement, and other constraints
with the Settings dialog box, Assignment Editor, Pin Planner, and Timing
Analyzer. Visualize and modify logic placement within a view of the device
floorplan in the Chip Planner and Timing Closure Floorplan. Refer to Intel
Quartus Prime Standard Edition User Guide: Design Constraints for more
information.
• Integrated Synthesis — provides efficient synthesis support for VHDL (1987,
1993, 2008), Verilog HDL (1995, 2001), and SystemVerilog (2005) design entry
languages. Refer to Intel Quartus Prime Standard Edition User Guide:
Compiler for more information.
• Incremental Compilation — preserve the results and performance for
unchanged logic in your design as you make changes elsewhere, facilitating top-
down or bottom-up team-based design methodologies. Refer to Intel Quartus
Prime Standard Edition User Guide: Compiler for more information.
• Design Debugging — The Signal Tap logic analyzer captures and displays real-
time signal behavior in an FPGA design, allowing to examine the behavior of
internal signals during normal device operation without the need for extra I/O pins
or external lab equipment. The Transceiver Toolkit provides real-time control,

EE421: DIGITAL SYSTEM DESIGN Page 2

 monitoring, and debugging of the transceiver links running on your board. Refer
to Intel Quartus Prime Standard Edition User Guide: Debug Tools for more
information.
• System and IP Integration — define and generate a complete system in much
less time than using traditional, manual integration methods with Platform
Designer (Standard). Refer to Introduction to Intel FPGA IP Cores and Intel
Quartus Prime Standard Edition User Guide: Platform Designer for more
information.

LAB TASKS:

Part I
The objective of this part is to display a character on a 7-segment display. The specific character displayed
depends on a two-bit input. Figure 1 shows a 7-segment decoder module that has the two-bit input c1c0. This
decoder produces seven outputs that are used to display a character on a 7-segment display. Table 1 lists the
characters that should be displayed for each valuation of c1c0 for your DE-series board. Note that in some
cases the ‘blank’ character is selected for code 11.

The seven segments in the display are identified by the indices 0 to 6 shown in the figure. Each segment is
illuminated by driving it to the logic value 0. You are to write a Verilog module that implements logic functions to
activate each of the seven segments. Use only simple Verilog assign statements in your code to specify each
logic function using a Boolean expression.

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CODE:

module lab2task1(input [1:0] SW, output [6:0] HEX0); // for DE1-SoC

assign HEX0[6] = ~SW[0]&~SW[1] | SW[0]&~SW[1]| SW[0]&SW[1] ;
assign HEX0[5] = ~SW[0]&SW[1] | SW[0]&SW[1];
assign HEX0[4] = ~SW[0]&SW[1] | SW[0]&SW[1];
assign HEX0[3] = SW[0]&~SW[1] | SW[0]&SW[1];
assign HEX0[2] = SW[0]&~SW[1] | SW[0]&SW[1];
assign HEX0[1] = ~SW[0]&~SW[1] | SW[0]&~SW[1]| SW[0]&SW[1] ;
assign HEX0[0] = SW[0]&~SW[1] | SW[0]&SW[1];

endmodule

RTL view:

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TESTBENCH:
module testbench_l2t1 ();

reg [1:0]SW;
wire [6:0] HEX0;

lab2task1 dut( SW, HEX0);

initial
begin
SW=2'b00;
#10;
SW=2'b01;
#10;
SW=2'b10;
#10;
SW=2'b11;
#10;

end

endmodule

SIMULATION:

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Part II
Consider the circuit shown in Figure 2. It uses a two-bit wide 4-to-1 multiplexer to enable the selection of four
characters that are displayed on a 7-segment display. Using the 7-segment decoder from Part IV this circuit can
display the characters d, E, 0, 1, 2, or ‘blank’ depending on your DE-series board. The character codes are set
according to Table 1 by using the switches SW7−0, and a specific character is selected for display by setting the
switches SW9−8.

An outline of the Verilog code that represents this circuit is provided in Figure 3. Note that we have used the
circuits from Parts III and IV as subcircuits in this code. You are to extend the code in Figure 3 so that it uses four 7-
segment displays rather than just one. You will need to use four instances of each of the subcircuits. The purpose
of your circuit is to display any word on the four 7-segment displays that is composed of the characters in Table 1,
and be able to rotate this word in a circular fashion across the displays when the switches SW9−8 are toggled. As
an example, if the displayed word is dE10, then your circuit should produce the output patterns illustrated in Table
2.

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 CODE: (for D10-SoC)

module lab2task2m (SW, LEDR, HEX0,HEX1,HEX2,HEX3);

input [9:0] SW; // slide switches
output [9:0] LEDR; // red lights
output [6:0] HEX0,HEX1,HEX2,HEX3; // 7-seg display
wire [1:0] M0;
wire [1:0] M1;
wire [1:0] M2;
wire [1:0] M3;
mux_2bit_4to1 U0 (SW[9:8], SW[7:6], SW[5:4], SW[3:2], SW[1:0], M0);
char_7seg H0 (M0, HEX0);
mux_2bit_4to1 U1 (SW[9:8], SW[5:4], SW[3:2], SW[1:0], SW[7:6], M1);
char_7seg H1 (M1, HEX1);
mux_2bit_4to1 U2 (SW[9:8], SW[3:2], SW[1:0], SW[7:6], SW[5:4], M2);
char_7seg H2 (M2, HEX2);
mux_2bit_4to1 U3 (SW[9:8], SW[1:0], SW[7:6], SW[5:4], SW[3:2], M3);
char_7seg H3 (M3, HEX3);

endmodule
// implements a 2-bit wide 4-to-1 multiplexer
module mux_2bit_4to1 (S, U, V, W, X, M);
input [1:0] S, U, V, W, X;
output reg [1:0] M;

always @(*)
begin
case(S)
2'b00 : M = U;
2'b01: M = V;
2'b10: M = W;
2'b11: M = X;

endcase
end

endmodule
// implements a 7-segment decoder for d, E, 1 and “blank” (D10-SoC)
module char_7seg (SW, HEX0);
input [0:1] SW; // input code
output [0:6] HEX0; // output 7-seg code
assign HEX0[0] = (~SW[1]&~SW[0] | SW[1]&~SW[0] | SW[1]&SW[0]);
assign HEX0[1] = (~SW[1]&SW[0] | SW[1]&SW[0]);
assign HEX0[2] = (~SW[1]&SW[0] | SW[1]&SW[0]);
assign HEX0[3] = (SW[1]&~SW[0] | SW[1]&SW[0]);
assign HEX0[4] = (SW[1]&~SW[0] | SW[1]&SW[0]);
assign HEX0[5] = (~SW[1]&~SW[0] | SW[1]&~SW[0] |
SW[1]&SW[0]);
assign HEX0[6] = (SW[1]&~SW[0] | SW[1]&SW[0]);
endmodule

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RTL view:

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 TESTBENCH:

module testbench_l2t2m();
reg [9:0] SW; // slide switches
wire [6:0] HEX0,HEX1,HEX2,HEX3;
lab2task2m ins0 (SW, LEDR, HEX0,HEX1,HEX2,HEX3);

initial
begin
SW = 10'b0000011011;
#10;
SW = 10'b0100011011;
#10;
SW = 10'b1000011011;
#10;
SW = 10'b1100011011;
#10;

end
endmodule

SIMULATION:

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Part III:
Extend your design from Part V so that is uses all 7-segment displays on your DE-series board. Your circuit needs
to display a three- or four-letter word, corresponding to Table 2, using ’blank’ characters for unused displays.
Implement rotation of this word from right-to-left as indicated in Table 3 and Table 4. To do this, you will need to
connect 6-to-1 multiplexers to each of six 7-segment display decoders for the DE10-Lite, DE0-CV and DE1-SoC.
Note that for the DE10-Lite you will need to use 3-bit codes for your characters, because five characters are needed
when including the ’blank’ character (your 7-segment decoder will have to use 3-bit codes, and you will need to use
3-bit wide 6-to-1 multiplexers). For the DE2-115, you will need to connect 8-to-1 multiplexers to each of the eight 7-
segment display decoders. You will need to use three select lines for each of the multiplexers: connect the select
lines to switches SW9−7. In your Verilog code connect constants to the 6-to-1 (or 8-to-1) multiplexers that select
each character, because there are not enough SW switches.

• Task 1: Rotating the word dE10 on six displays.

TABLE:

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CODE:

module lab2task3_1 (SW, HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7) ;

input [2:0] SW; // slide switches // red lights

output [6:0] HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7; // 7-seg display

wire [2:0] M0,M1,M2,M3,M4,M5,M6,M7;

mux_3bit_8to1 top (SW, M0,M1,M2,M3,M4,M5,M6,M7);

seg_7 first(M0,HEX0);

seg_7 second(M1,HEX1);

seg_7 third (M2,HEX2);

seg_7 fourth(M3,HEX3);

seg_7 fifth (M4,HEX4);

seg_7 sixth (M5,HEX5);

seg_7 seventh(M6,HEX6);

seg_7 eigth (M7,HEX7);

endmodule

// implements a 3-bit wide 8-to-1 multiplexer

module mux_3bit_8to1 (S, M0,M1,M2,M3,M4,M5,M6,M7);

input [2:0] S;

output reg [2:0] M0,M1,M2,M3,M4,M5,M6,M7;

always@(*)

begin

case(S)

3'b000 : begin
M0=3'b100;

M1=3'b100;
M2=3'b000;

M3=3'b001;
M4=3'b010;

M5=3'b011;

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 end

3'b001 : begin

M0=3'b100;

M1=3'b000;

M2=3'b001;
M3=3'b010;

M4=3'b011;
M5=3'b100;

end

3'b010 : begin

M0=3'b000;

M1=3'b001;

M2=3'b010;

M3=3'b011;
M4=3'b100;

M5=3'b100;

end

3'b011 : begin

M0=3'b001;
M1=3'b010;

M2=3'b011;
M3=3'b100;

M4=3'b100;
M5=3'b000;

end

3'b100 : begin

M0=3'b010;

M1=3'b011;
M2=3'b100;

M3=3'b100;
M4=3'b000;

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 M5=3'b001;

end

3'b101 :begin

M0=3'b011;

M1=3'b100;
M2=3'b100;

M3=3'b000;
M4=3'b001;

M5=3'b010;

end

3'b110 : begin

M0=3'b100;

M1=3'b100;

M2=3'b000;
M3=3'b001;

M4=3'b010;
M5=3'b011;

end

3'b111 : begin
M0=3'b100;

M1=3'b000;
M2=3'b001;

M3=3'b010;
M4=3'b011;

M5=3'b100;

end

endcase

end

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endmodule

// implements a 7-segment decoder for d, E, 1 and 0

module seg_7 (input [2:0] SW, output [6:0] HEX0);

assign HEX0[6] = ~SW[2]&~SW[1]&~SW[0] | ~SW[2]&SW[1]&~SW[0] |SW[2]&~SW[1]&~SW[0] ;

assign HEX0[5] = ~SW[2]&SW[1]&~SW[0] |SW[2]&~SW[1]&~SW[0] ;

assign HEX0[4] = ~SW[2]&~SW[1]&SW[0] |SW[2]&~SW[1]&~SW[0] ;

assign HEX0[3] = ~SW[2]&SW[1]&~SW[0] |SW[2]&~SW[1]&~SW[0] ;

assign HEX0[2] = ~SW[2]&SW[1]&~SW[0] |SW[2]&~SW[1]&~SW[0] ;

assign HEX0[1] = ~SW[2]&~SW[1]&~SW[0] | ~SW[2]&SW[1]&~SW[0] |SW[2]&~SW[1]&~SW[0] ;

assign HEX0[0] = ~SW[2]&SW[1]&~SW[0] | ~SW[2]&SW[1]&SW[0] |SW[2]&~SW[1]&~SW[0] ;

endmodule

RTL VIEW:

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TEST BENCH:
module testbench_l2t3_1 ();

reg [2:0]SW;
wire [6:0] HEX0,HEX1,HEX2,HEX3,HEX4,HEX5;

lab2task3_1 dut( SW, HEX0,HEX1,HEX2,HEX3,HEX4,HEX5);

initial
begin
SW=3'b000;
#10;
SW=3'b001;
#10;
SW=3'b010;
#10;
SW=3'b011;
#10;
SW=3'b100;
#10;
SW=3'b101;
#10;

end

endmodule

SIMULATION:

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 • Task 2: Rotating the word dE2 on eight displays.

CODE:

module lab2task3_2 (SW, HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7) ;

input [2:0] SW; // slide switches // red lights
output [6:0] HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7; // 7-seg display
wire [1:0] M0,M1,M2,M3,M4,M5,M6,M7;

mux_3bit_8to1 top (SW, M0,M1,M2,M3,M4,M5,M6,M7);

seg_7 first(M0,HEX0);
seg_7 second(M1,HEX1);
seg_7 third (M2,HEX2);
seg_7 fourth(M3,HEX3);
seg_7 fifth (M4,HEX4);
seg_7 sixth (M5,HEX5);
seg_7 seventh(M6,HEX6);
seg_7 eigth (M7,HEX7);

endmodule
// implements a 3-bit wide 8-to-1 multiplexer
module mux_3bit_8to1 (S, M0,M1,M2,M3,M4,M5,M6,M7);
input [2:0] S;
output reg [1:0] M0,M1,M2,M3,M4,M5,M6,M7;

always@(*)
begin
case(S)
3'b000 : begin
M0=2'b11;
M1=2'b11;
M2=2'b11;
M3=2'b11;
M4=2'b11;
M5=2'b00;
M6=2'b01;
M7=2'b10;

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 end
3'b001 : begin
M0=2'b11;
M1=2'b11;
M2=2'b11;
M3=2'b11;
M4=2'b00;
M5=2'b01;
M6=2'b10;
M7=2'b11;
end
3'b010 : begin
M0=2'b11;
M1=2'b11;
M2=2'b11;
M3=2'b00;
M4=2'b01;
M5=2'b10;
M6=2'b11;
M7=2'b11;
end
3'b011 : begin
M0=2'b11 ;
M1=2'b11 ;
M2=2'b00 ;
M3=2'b01 ;
M4=2'b10 ;
M5=2'b11 ;
M6=2'b11 ;
M7=2'b11 ;
end
3'b100 : begin
M0=2'b11 ;
M1=2'b00 ;
M2=2'b01 ;
M3=2'b10 ;
M4=2'b11 ;
M5=2'b11 ;
M6=2'b11 ;
M7=2'b11 ;
end
3'b101 :begin
M0=2'b00 ;
M1=2'b01 ;
M2=2'b10 ;
M3=2'b11 ;
M4=2'b11 ;
M5=2'b11 ;
M6=2'b11 ;
M7=2'b11 ;
end
3'b110 : begin
M0=2'b01 ;
M1=2'b10 ;
M2=2'b11 ;
M3=2'b11 ;
M4=2'b11 ;
M5=2'b11 ;
M6=2'b11 ;
M7=2'b00 ;
end

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3'b111 : begin
M0=2'b10 ;
M1=2'b11 ;
M2=2'b11 ;
M3=2'b11 ;
M4=2'b11 ;
M5=2'b11 ;
M6=2'b00 ;
M7=2'b01 ;
end

endcase

end

endmodule
// implements a 7-segment decoder for d, E, 2 and 0
module seg_7 (input [1:0] SW, output [6:0] HEX0);

assign HEX0[6] = ~SW[1]&~SW[0] | SW[1]&SW[0] ;

assign HEX0[5] = ~SW[1]&SW[0] | SW[1]&SW[0];
assign HEX0[4] = ~SW[1]&SW[0] | SW[1]&~SW[0]| SW[1]&SW[0];
assign HEX0[3] = SW[1]&SW[0];
assign HEX0[2] = SW[1]&SW[0];
assign HEX0[1] = ~SW[1]&~SW[0] | SW[1]&~SW[0]| SW[1]&SW[0] ;
assign HEX0[0] = SW[1]&SW[0];

endmodule

RTL VIEW:

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TEST BENCH:
module testbench_l2t3_2 ();

reg [2:0]SW;
wire [6:0] HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7;

lab2task3_2 dut( SW, HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7);

initial
begin
SW=3'b000;
#10;
SW=3'b001;
#10;
SW=3'b010;
#10;
SW=3'b011;
#10;
SW=3'b100;
#10;
SW=3'b101;
#10;
SW=3'b110;
#10;
SW=3'b111;
#10;

end

endmodule
SIMULATION:

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Conclusion:

In this lab we learnt how to connect simple input and output devices to an FPGA chip and
implement a circuit that uses these devices. We used the switches on the DE-series boards
as inputs to the circuit. We implemened various multiplexers ( 2 bit wide 4-1 , 3 bit wide 8
-1 ) to accomplish our tasks .We will used light emitting diodes (LEDs) and 7-segment
displays as output devices. Then we created a testbench of the tasks listed and simulated
our design and we observed that we got the results as expected.

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