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A High-Frequency CMOS Based Driver for High-Power MOSFET Applications

Conference Paper · January 2014

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 A High-Frequency CMOS Based Driver for High-Power MOSFET
Applications

A.J. Swart

Department of Electrical, Electronic and Computer Engineering, Central University of

Technology, Private Bag X20539, Bloemfontein, South Africa, 9300. Email:
drjamesswart@gmail.com

Abstract: Driving high-power MOSFETs at high frequencies requires a gate drive signal of more
than 10 Vp-p. Generating high frequencies is usually accomplished via a frequency generator, such as
a frequency synthesizer. However, the output signal voltage from these frequency synthesizers is
often lower than 10 Vp-p, being 5.5 Vp-p in the case of the 74HC 4046. This requires some or other
form of voltage amplification to successfully drive a high-power MOSFET. The purpose of this paper
is to present a CMOS based driver, using a HEF 40106 HEX inverter, which was successfully used to
raise a 6.78 MHz square wave signal from 5.5 Vp-p to above 10 Vp-p in order to drive a high-power
MOSFET. Results indicate that this CMOS based driver exhibits a wide bandwidth, being able to
amplify the 1st and 3rd harmonics of the square wave signal.

Keywords: CMOS driver, MOSFET, high-frequency, 4000 series, bandwidth

1. INTRODUCTION MOSFET. The reason for piloting this frequency within

The ability of high-power MOSFETs to act as a switch
makes it an ideal switching device [1]. The technique of
switching between maximum and zero voltage across a
high-power MOSFET has easily been achieved in the
past at frequencies below 1 MHz [2].
However, commercially available high-speed MOSFET
drivers now have the ability to produce switching
frequencies beyond 1 MHz, such as the TPS 2812,
which was used by Xiarong et al. [3] in a driving circuit
for ultrasonic transducers. It is only necessary to build a
high speed, low power driver for the MOSFET driver
when using the TPS 2812. However, a concern arises
with this MOSFET driver in that its input circuit has a
positive threshold of approximately 2/3 of VCC. The
minimum gate voltage required to successfully switch a
MOSFET is around 10 Vp-p [4]. This means that if
VCC is 10 V, then the minimum input threshold voltage
must be 6.67 Vp-p.
This 6.67 Vp-p becomes problematic when considering
the output voltage of certain frequency generation
devices, devices which are required to generate the
switching frequencies in high-power MOSFET
applications. For example, consider the 74HC 4046, a
phase-lock loop device capable of generating
frequencies up to 20 MHz (within the high-frequency
range), but at a constant output voltage of 5.5 Vp-p [2].
This means that it will not be able to be connected
straight into certain MOSFET drivers, such as the TPS
2812, without some or other form of voltage application
that will increase the 5.5 Vp-p signal to more than 6.67
Vp-p.
the high-frequency range is because ICASA does not
require a license for using this frequency [5]. This
CMOS based driver may further be applied as a pre-
amplifier to the TPS 2812 in order to raise any
frequency below 6.78 MHz with a 5.5 Vp-p amplitude
to above the 6.67 Vp-p threshold voltage required for
successful switching.
Theory regarding gate charge, energy and power
requirements for driving high-power MOSFETs is
firstly presented. Various voltage amplification circuits
are then presented, with focus being directed primarily
to HEF 40106 HEX inverter. The simulation circuit is
then introduced with its associated results.
2. GATE CHARGE, ENERGY AND POWER
MOSFET devices are not really inherently bound to
frequency limitations within the high-frequency range
due to the absence of minority carrier transport. Two
limits to high-frequency operation do though exist, and
include the transient time across the drift region and the
rate of charging of the input gate capacitance [6].
Speed limitations of MOSFET devices are therefore due
entirely to circuit capacitance and the inability of the
device to charge and discharge this capacitance [7].
Important parameters to therefore consider are the
parasitic capacitances of the MOSFET device [8].
Taylor [9] examined the gate control charge of a
MOSFET device in the on position and expressed it as:
Qgate Ciss. Vgs Coulomb (1)

The purpose of this paper is to present a CMOS based Where Ciss ≡ the input gate capacitance of the
driver, using the HEF 40106, which was successfully MOSFET in pF
used to raise a 6.78 MHz square wave signal from 5.5 Vgs ≡ the gate to source voltage V
Vp-p to above 10 Vp-p, in order to drive a high-power
Ciss is the sum of the real capacitance between the gate  A voltage source in series with a resistance;
and source (CGS) and the voltage dependant capacitance  Active pull down with passive pull up;
between the drain and the gate (CDG). The value of Vgs  A complimentary emitter follower; and
is a function of the device and the voltage required to  CMOS based IC’s such as the 4000 series;
achieve full enhancement. The energy required for this
gate charge can be expressed as [9]: A gate drive circuit may generally be represented by a
voltage source in series with a resistance. A resistance
2
Egate 0.5. Ciss. Vgs Joules (2) may be inserted intentionally between the gate of the
MOSFET and the voltage source so as to modify the
Subsequently, the power required for this gate charge switching speed or represent the impedance of the
can be expressed as [9]: voltage source [10]. Different turn-on and turn-off times
may be achieved by utilizing a diode in parallel with
2 this series resistance as shown in Figure 1.
Pgate 0.5. Ciss. Vgs . freq Watts (3)

Where f ≡ the input gate frequency in Hz

A portion of the gate drive power will further be

dissipated in the internal resistance of the gate. These
losses are negligible at frequencies around 100 kHz, but
become significant at higher frequencies, especially
when considering frequencies around 10 MHz.
Contrasting the IRF140 with the IRF610 yields the
results shown in Table 1 for a gate voltage of 12 Vp-p.

Table 1: Gate charge, energy and power required for

100 kHz and 6.78 MHz operation
Figure 1: Asymmetric gate drives featuring a fast turn-
100 kHz IRF140 IRF610
on technique
Ciss (F) 1660 pF 140 pF
Gate charge (C) 1.992 nC 1.68 nC However, asymmetry may be inherent in gate drive
Energy (J) 119.5 nJ 10.08 nJ circuits, where an active pull down action but a passive
Power (W) 12 mW 1 mW pull up action (or visa versa) exists. Figure 2 illustrates
gate drive circuits with inherent asymmetry.

6.78 MHz IRF140 IRF610 To achieve switching speeds of the order of 100 ns or
Ciss (F) 1660 pF 140 pF less requires a gate drive circuit with a low output
Gate charge (C) 1.992 nC 1.68 nC impedance and the ability to source and sink relatively
large currents [10]. A NPN and PNP transistor
Energy (J) 119.5 nJ 10.08 nJ connected in a totem-pole configuration, as shown in
Power (W) 810 mW 68 mW Figure 3, is capable of sourcing and sinking large
amounts of current, while providing a low output
Table 1 indicates that driving high-power MOSFETs at impedance [10].
low frequencies requires only a small amount of power
(1 mW versus 68 mW for the IRF610). This table
further highlights that larger input gate capacitances
requires higher input powers within the high-frequency
range (810 mW versus 68 mW). This has subsequently
resulted in the commercialisation of numerous
MOSFET IC drivers that need supply only a few mW in
the lower frequency ranges. However, higher frequency
ranges would require a higher gate drive power and
subsequently a slightly different MOSFET gate driver
being able to source and sink larger amounts of current,
while providing the correct gate voltage.

3. VOLTAGE AMPLIFICATION

Voltage amplification of square wave signals to drive

high-power MOSFETs may be achieved in a variety of Figure 2: Gate drive circuits with inherent asymmetry
ways, including the use of:
High-power MOSFETs may also be driven directly
from CMOS IC’s. The output characteristics of CMOS
are approximately the same whether sourcing or sinking
current. The main advantage is that the supply voltage
may be set to 15 V, an acceptable voltage to switch the
power MOSFET on and off. Lower output impedances
and higher currents can be achieved by connecting a
number of CMOS gates in parallel, as shown in Figure 4
[10].
Figure 3: Complementary emitter follower, low
impedance gate drive circuit
Figure 4: CMOS outputs paralleled to increase drive
capability
This last gate drive circuit, incorporating multiple
CMOS inverters in parallel was chosen for the voltage
amplification stage. Reasons include the provision of a
very low output impedance, the ability to source and
sink large amounts of current and its wide operating
bandwidth.
Voltage amplification of square wave signals requires
the designer to take into consideration the harmonic
content of the signal, and subsequently the bandwidth.
Consider a 6.78 MHz square wave signal that would
have harmonic content at 20.34 MHz (considering only
the 3rd harmonic). This harmonic frequency would also
have to be amplified, to ensure a more square wave
signal than a sine wave signal at the output (see figure
5). This then requires that the voltage amplification
stage possess a sufficient bandwidth to incorporate these
harmonics, or else severe degradation of the square
wave signal will exist. The following equation is used to
represent the 1st and 3rd harmonic waveform [11]:
4. 1.
f( t ) sin( . t ) sin( 3. . t ) (4)
 3
Figure 5: 1st harmonic only on the left, 1st and 3rd
harmonic on the right
A CMOS based IC that incorporates such a wide
bandwidth is the HEF 40106, a HEX inverting Schmitt
trigger containing 6 separate invertors. Although logic
ICs are not usually specified in terms of bandwidth (but
rather in terms of propagation delay), there have been
some researchers who have commented on their
bandwidth characteristics [12, 13]. The datasheet for the
HEF 40106 indicates that its transition time from low to
high is typically around 60 ns when fed from a 5 V
source. High to low transition time is typically also 60
ns. This means that 120 ns is required for a square wave
signal to switch between zero, maximum and zero
again. As the supply voltage increases, these transition
times decrease, thus increasing the maximum allowable
clock frequency.
A 5 V supply will cause the HEF 40106 to successfully
accommodate an input frequency of around 8 MHz (120
ns time period). The Schmitt trigger action is mainly
responsible for this transition time as well as for
relatively high input noise immunity. The datasheet
further indicates that the HEF 40106 requires a typical
positive-going input voltage of 5.8 V to successfully
switch the inverter, when run from a 10 V supply rail.
This is just higher than the typical output voltage of
certain frequency synthesizers which are often built
around phase-lock loop (PLL) IC’s. The 74HC 4046 is
such a PLL IC capable of producing frequencies
upwards of 20 MHz, but at an output voltage of 5.5 V.
The supply voltage to the first HEF 40106 must
therefore be made lower to accommodate the 5.5 V
from the frequency synthesizer. Using a voltage supply
of 7.5 V allows a positive-going input voltage of below
5.5 V, therefore allowing the inverter to switch
successfully and provide an output voltage of 7 V (0.5
V hysteresis voltage accounted for). This output voltage
must now be fed into a second HEF 40106 operating at
a supply voltage of 9.5 V to raise it to a higher voltage.
A third HEF 40106, operating at a supply voltage of
11.5 V, is finally used to raise the signal to 11 V,
providing the voltage required to drive the gate of the
high-power MOSFET operating in the high-frequency
range.
 The results of the experimental model were verified
However, using just one of the six inverters available on with a simulation model incorporated into the National
the HEF 40106 will not provide sufficient drive to the Instruments Multisim 11.0 simulation package. The
following inverters in the circuit. Paralleling 3 inverters results of the simulation model are shown in Figure 8.
on the chip will result in a lower output impedance, Again voltage amplification is visible as the 6.78 MHz
thereby providing sufficient drive for the next set of signal is raised from 5.5 V to 7 V, then to 9 V and then
inverters. This technique of paralleling inverters for a finally to 11 V. The simulation model does however
MOSFET driver was initially discussed by Grant and present a sharper square wave signal than does the
Gowar [10]. Figure 6 illustrates the circuit diagram experimental model.
comprising three individual HEX inverter Schmitt
triggers which serve as the voltage amplification section
to raise a voltage of 5.5 V to above 10 V. This same
circuit comprises the simulation model, which was
incorporated into National Instruments Multisim 11.0
simulation package.
XSC1

T
A B C D

R2
75Ω
Q1 Q7
VDD1 VDD2 VDD3 Point E
7.5V 9.5V 11.5V V2
15 V
BC639 TIP31C
U1A Point A U2A Point B U3A Point C Q3
L1 Point D IRF610 Figure 8: Outputs from the first three HEF 40106
1.5µH
U1B U2B U3B CMOS inverters taken from the simulation model
V1 Q2 Q6

6.78MHz U1C U2C U3C

5.5 V
R1
1kΩ
The 11 V ouput signal from the final CMOS inverters
BC640 TIP32C

VSS
were correlated to the mathematical equation (equation
0V 4) for the 1st and 3rd harmonics of a square wave signal.
This correlation is shown in Figure 9 which
substantiates the wide bandwidth of the HEF 40106 as
Figure 6: Simulation model being able to accommodate harmonics up to 21 MHz.

4. RESULTS

The voltage amplification section consists of 3 CMOS

HEX inverters, where 3 inverters on each IC are
paralled. The outputs of each of the CMOS HEF 40106
HEX inverters used in the experimental model, obtained
from test points A through C, are shown in Figure 7.
Point A represents a 7 V output signal, point B a 9 V
output signal and point C a 11 V output signal, all at a
high-frequency value of 6.78 MHz.

Figure 9: Correlation between the output waveform

from the third HEF 40106 CMOS HEX inverter and the
mathematical equation for the 1st and 3rd harmonics –
Point C

The final output waveform of the voltage amplification

stage was applied to a complementary emitter follower
connected to the input of a high-power MOSFET. The
input switching waveform of the MOSFET (IRF610) is
Figure 7: Outputs from the first three HEF 40106 shown in Figure 10, where successful switching was
CMOS inverters taken from the experimental model – accomplished as depicted in Figure 11 (output voltage
time per division is 20 ns where Points A, B and C are and current for the MOSFET device).
indicated

Experimental Model
Simulated Model
Figure 10: Final input switching waveforms from the
high-power MOSFET [14] – Point D
CH2
CH1
Figure 11: Output voltage (CH2) and current (CH1) for
the high-power MOSFET [15] – Point E
5. CONCLUSIONS
The application of three HEF 40106 HEX inverters,
each operating at a different supply voltage, has
provided sufficient voltage amplification of the 6.78
MHz signal derived from a PLL IC (74HC 4046).
Raising the 5.5 V signal to above 10 V has materialised
where the 1st and 3rd harmonic of the square wave signal
has been amplified. However, the final output signal
was not a perfect square wave, but did indeed provide
sufficient drive to turn the gate of the high power
MOSFET completely on and off.
6. REFERENCES
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[2] A. J. Swart and H. C. Pienaar, "A high frequency
Mosfet driver," in SAUPEC 2004, University of
Stellenbosch, Stellenbosch, 2004.
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