EECS 105 Spring 2004, Lecture 16

Lecture 16: MOS Transistor models:

Linear models, SPICE models

Prof. J. S. Smith

Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 16 Prof. J. S. Smith

Context
In the last lecture, we discussed the
MOS transistor, and
– added a correction due to the changing
depletion region, called the body effect
– Did a review of small signal models
– Started small signal models for the FET
z In this lecture, we will
– Continue to build the small signal
models for MOS FETs
– look at how MOS Transistors are
modeled in SPICE

Department of EECS University of California, Berkeley

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EECS 105 Spring 2004, Lecture 16 Prof. J. S. Smith

Reading
z We are next going to look at the analog
characteristics of simple digital devices, 5.2→5.4
z And following the midterm, we will cover PN
diodes again in forward bias, and develop small
signal models: Chapter 6
z we will then take a week on bipolar junction
transistor (BJT): Chapter 7
z Then go on to design of transistor amplifiers:
chapter 8

Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 16 Prof. J. S. Smith

Transistor equations:
Cutoff
VGS < VTN We discussed a physical model for these
⇒ ID = 0 parameters, but often they will be used to
VGS > VTP fit the observed curves for a given
manufacturing process
Linear
VGS ≥ VTN , VDS < VGS − VTN
VGS ≤ VTP , VDS > VGS − VTP
⇒ I D = µCox
W
L
[
(VGS − VT )VDS − 12 VDS2 ]
Saturation
VGS ≥ VTN , VDS ≥ VGS − VTN
⇒ I D = 12 µCox (VGS − VT ) (1 + λVDS )
W 2

VGS ≤ VTP , VDS ≤ VGS − VTP L

Note: if VSB ≠ 0, need to calculate VT

Department of EECS University of California, Berkeley

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EECS 105 Spring 2004, Lecture 16 Prof. J. S. Smith

Circuit models
z We are now going to produce circuit models, which
will translate the mathematics into drawings of
circuit elements so that we can design real circuits
using our developed intuition.

Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 16 Prof. J. S. Smith

Circuit models:
z In order to translate mathmatical expressions into
an equivalent circuit, we will use resistors,
capacitors, and variable current sources, hooking
them up with perfect wires. Perfect wires have no
parasitic capacitance or inductance, and convert
into equations by Kirchoff’s laws:
i (t ) → +
+
C R v1 i2 = gv1
v(t )
− −

Department of EECS University of California, Berkeley

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EECS 105 Spring 2004, Lecture 16 Prof. J. S. Smith

Large signal models:

z Large signal models try to recreate the behavior of
real devices over large voltage swings, may not be
linear, and may not be terribly accurate in the
details. For example, a PN junction might be
modeled as a perfect diode, which always blocks
current in the forward direction, and passes current
with no voltage drop in the reverse direction

Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 16 Prof. J. S. Smith

DC Large signal model for a FET

Sometimes a circuit model is very close to mathematics, for example
We can directly convert our mathematical model for the FET into:

+ +
VGS ID ↓ VSD
− −
+
Where:
VSB ⇐ VGT ≤ 0
⎧0
− ⎪
ID = ⎨ W ⎛ 2
⎞
⎟(1 + λVDS ) ⇐ VGT > 0
Vmin
k ′ ⎜ V V
⎪ L ⎜ GT min −
⎩ ⎝ 2 ⎟⎠
Vmin = min (VGT , VDS , Vsat )

VGT = VGS − VT and VT = VT 0 + γ ⎛⎜ − 2φ f + VSB − − 2φ f ⎞⎟

⎝ ⎠
Department of EECS University of California, Berkeley

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EECS 105 Spring 2004, Lecture 16 Prof. J. S. Smith

Typical parameters
z Here are some parameters for an actual 0.25 micron
process:
(Volts) (Root volts) (volts) (A/V2) (volts-1)

VT 0 γ VDSAT k′ λ
NMOS 0.43 0.4 0.63 115 ×10 −6 0.06
PMOS -0.4 -0.4 -1 − 30 × 10 −6 -0.1

Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 16 Prof. J. S. Smith

Limitations of large signal models

z Large signal models must often be greatly
simplified to handle intuitively
z Large signal models are often nonlinear, so it is
difficult to analyze circuits with more than a few
elements directly
z Elements such as variable stored charge are
difficult to model, often use a fixed capacitance
which has a compromise value

Department of EECS University of California, Berkeley

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EECS 105 Spring 2004, Lecture 16 Prof. J. S. Smith

Simplified large signal model

z To think about, and design circuits, we will often
use rough models which behave somewhat like the
physical device under a particular circumstance.
For example we might model a FET as a resistive
switch:
G D
+ +

VGS C Where C and R are chosen

VDS purely to give us an approximation
R to the observed value under the
− operating conditions
−

Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 16 Prof. J. S. Smith

Small signal models

z If we linearize the model as discussed in the last
lecture, by picking an operating point and allowing
only small signal variations around those operating
points (for both voltages and currents) we can
produce a small signal model, one which includes
only linear elements.
z This will let use linear circuit theory, which is a
way we can handle very large numbers of
interacting components.

Department of EECS University of California, Berkeley

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EECS 105 Spring 2004, Lecture 16 Prof. J. S. Smith

Small signal model for the MOS FET

The current from the drain of our FET can be modeled for small signals:
iDS (t ) = I DS + ids

For a given operating point voltage for Vgs and Vds, we get:
∂iDS ∂i
ids = vgs + DS vds
∂vgs ∂vds
Which we will then label:
1
ids = g m vgs + vds
ro

Transconductance
Conductance

Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 16 Prof. J. S. Smith

Substrate potential

Let’s look at the back gate effect in a small

signal model

Effect: changes threshold voltage, which

changes the drain current … substrate acts
like a “backgate”

∆iD ∂iD
g mb = =
∆vBS ℵ
∂vBS ℵ

ℵ⇒ (VGS, VDS, VBS) ← are all held constant

Department of EECS University of California, Berkeley

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EECS 105 Spring 2004, Lecture 16 Prof. J. S. Smith

Backgate Transconductance

VT = VT 0 + γ ( VSB − 2φ p − −2φ p )

∂iD ∂iD ∂VTn γ gm

Result: g mb = = =
∂vBS Q
∂VTn Q
∂vBS Q
2 −VBS − 2φ p
Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 16 Prof. J. S. Smith

Transconductance
z Notice that we have terms in our equations which
give the small signal current into one terminal in as
a constant times the small signal voltage into
another terminal. In order to translate that into a
linear equivalent circuit, we will use a variable
current source, but where the current is just
proportional to a voltage:
+
v1 i2 = gv1
−
Where g is called the transconductance
Department of EECS University of California, Berkeley

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EECS 105 Spring 2004, Lecture 16 Prof. J. S. Smith

Combining terms: Small-Signal Model

We now have three small signal contributions to the current into
the drain terminal for our FET, from changes in Vgs, Vbs, and Vds

1
ids = g m vgs + g mb vbs + vds
ro
Notice that the change in the small signal current into the drain from
A small signal change in Vds can be modeled as a resistor.
Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 16 Prof. J. S. Smith

Capacitances
z While adequate for some purposes, the model so far
implies that the current into the gate is zero. This is
a good approximation for low frequencies, for high
frequencies we need to account for the current
necessary to charge up the gate to supply the field
across the oxide. There are also stray capacitances
to the drain and source contacts.

Department of EECS University of California, Berkeley

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EECS 105 Spring 2004, Lecture 16 Prof. J. S. Smith

MOSFET Capacitances in Saturation

The gate-drain capacitance is only the fringe capacitance

when in saturation, because it is pinched off from the
charge in the channel.
Gate-source capacitance: There is fringing charge between
the edge of the gate and the source, but also to the channel

Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 16 Prof. J. S. Smith

Gate-Source Capacitance Cgs

Wedge-shaped charge in saturation Æ effective area is (2/3)WL

(see H&S 4.5.4 for details)

C gs = (2 / 3)WLCox + Cov
Overlap capacitance along source edge of gate Æ

Cov = LDWCox
(This is an underestimate, fringing fields will make
The overlap capacitance larger)

Department of EECS University of California, Berkeley

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EECS 105 Spring 2004, Lecture 16 Prof. J. S. Smith

Gate-Drain Capacitance Cgd

There is no contribution due to change in inversion charge

in channel, just overlap capacitance between drain and source

Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 16 Prof. J. S. Smith

Junction Capacitances

The source, gate, and drain will also have capacitances

between them and the well or substrate.
Capacitances to the drain and source will be junction
capacitances, and since VSB and VDB = VSB + VDS reverse
biases are different, the capacitances will be different

Department of EECS University of California, Berkeley

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EECS 105 Spring 2004, Lecture 16 Prof. J. S. Smith

Seeking perfection…
z Remember that all of the capacitances, resistances
and transimpedances will change as the operating
point changes
z There is no such thing as a perfect small signal
model, use the simplest one that is sufficient.
z Sometimes a small signal model is used well
outside of where it is accurate, because it is the
main way we can deal intuitively with these
devices!

Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 16 Prof. J. S. Smith

Junction Capacitances

Drain and source diffusions have (different) junction

capacitances since VSB and VDB = VSB + VDS aren’t
the same
“Complete” model

Department of EECS University of California, Berkeley

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EECS 105 Spring 2004, Lecture 16 Prof. J. S. Smith

P-Channel MOSFET

Measurement of –IDp versus VSD, with VSG as a parameter:

Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 16 Prof. J. S. Smith

Square-Law PMOS Characteristics

Department of EECS University of California, Berkeley

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EECS 105 Spring 2004, Lecture 16 Prof. J. S. Smith

Small-Signal PMOS Model

Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 16 Prof. J. S. Smith

Parameter variation
The work that we have done so far implies that
transistors will come out as we calculated, or at
least with reproducible characteristics, however:
z Transistors from different manufacturers can be

significantly different
z Transistor, resistance, and capacitor values will

vary from batch to batch ~20%

z Parameters will vary to a lessor extent from wafer

to wafer
z Transistors made close to each other on a wafer

will be pretty similar, if W is not too close to the

smallest available, and if they are close together.

Department of EECS University of California, Berkeley

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EECS 105 Spring 2004, Lecture 16 Prof. J. S. Smith

Must design with wide tolerances

z To accommodate these wide variations in
parameters, a VLSI designer must design circuits
which will work under a wide range of those
parameters.
z We will study methods such as feedback which will
tend to cause a design to operate as it should, even
though the process parameters vary.

Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 16 Prof. J. S. Smith

SPICE
z A spice model is generally a set of formulas such as
presented in this lecture, with the characteristics of the
specific process set by parameters to the model. Several
different models are available, indicated by the LEVEL:
z Level 1: The Shichman-Hodges model, which is based on
the long channel expressions given here.
z Level 2 model is a semiconductor physics model which
includes velocity saturation, drain induced barrier lowering,
etc.
z Level 3 is a semiemperical model which uses measured
device data, and works well down to 1 micron channel
lengths
z Many other models have been developed, mostly empirical

Department of EECS University of California, Berkeley

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EECS 105 Spring 2004, Lecture 16 Prof. J. S. Smith

MOSFET SPICE Model

… we will use the square-law

“Level 1” model
See H&S 4.6 + Spice refs. on reserve for details.

Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 16 Prof. J. S. Smith

SPICE level 1 parameters

z Even SPICE level 1 has many parameters, for
example:
– TOX oxide thickness
– VT0 threshold voltage
– LAMBDA channel length modulation parameter
– GAMMA bulk threshold parameter
– CGSD gate source overlap capacitance
– KP transconductance parameter
Etc. Most parameters have reasonble defaults if
values are not set explicitly

Department of EECS University of California, Berkeley

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