Universitat Politècnica de Catalunya

Departament d’Enginyeria Electrònica

Electronic Systems

Topic 5

SEQUENTIAL SYSTEMS

Lectures: 3 hours
Exercises: 2 hours
 SEQUENTIAL SYSTEMS

1. Introduction.
2. Bi-stables.
3. Registers.
4. Counters.
Contents

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 SEQUENTIAL SYSTEMS

1. Introduction.
I. Sequential systems.
II. Classification of sequential systems.
2. Bi-stables.
3. Registers.
Contents

4. Counters.

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 1.I. SEQUENTIAL SYSTEMS

• The current value of the outputs depends not only on the

current value of the inputs but also on the previous state
of the system (memory effect).

Sequential
Sistema Z(t) = f(X(t),X(t-1),X(t-2),…,X(t0))
X(t)
system
seqüencial

• Sequential systems have feedback.

S ste a seqüe c a

X(t) Sistema
Combinational Z(t)
system
combinacional

Q0
Q Q+
Q

∆t

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 1.I. SEQUENTIAL SYSTEMS

• The sequence of the input values determines the state variables Q.

• A sequential system is fully specified by:
• The inputs X.
• The outputs Z.
• The current state Q0.
1. Introduciton

• The output function Z=f(X, Q0)

• The transition function Q=g(X,Q0).
S ste a seqüe c a

X(t) Sistema
Combinational Z(t)
system
combinacional

Q0
Q Q+
Q

∆t

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 1.II. CLASSIFICATION OF SEQUENTIAL SYSTEMS

• Synchronous: State changes are synchronized by a clock

signal CLK (usually a square wave with 50% duty cycle).

CLK

• Asynchronous: State changes are

not synchronized by a clock signal and can theoretically
occur as fast as the propagation delays allow.
• Synchronous systems are slower, simpler and much
more common than asynchronous ones.

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 SEQUENTIAL SYSTEMS

1. Introduction.
2. Bi-stables.
I. Basic memory element
II. Edge-triggered bi-stables (flip-flops)
III. Flip-flop types
IV.Asynchronous control signals.
Índex

3. Registers.
4. Counters.

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 2.I. BASIC MEMORY ELEMENT

• Circuit without inputs and two outputs (Q and Q �)

made up of two NOT gates with the output of one
of them connected to the input of the other one.
2. Biestables

0 1
Q �
Q
Q’
1 0

• Two stable states (bi-stable).

• It can store one bit but not to change it. ???
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 2.II. EDGE-TRIGGERED BISTABLES

• Usually called flip-flops.

• State changes are synchronized by one of the edges of
the clock signal.
• Positive edge-triggered flip-flop: State changes are
synchronized by the rising clock edge.

CLK

T
• Negative edge-triggered flip-flop: State changes are
synchronized by the falling clock edge.

CLK

T
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 2.III. FLIP-FLOP TYPES

• J-K flip-flop: Two inputs called J, K allow to modify the

outputs Q and Q � as stated in the table below.
• Can be positive or negative edge-triggered. (The table
shown corresponds to the positive edge-triggered type.)
2. Biestables

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 2.III. FLIP-FLOP TYPES

• Example of time-diagram for a

positive edge-triggered J-K flip-flop.
2. Biestables

CLK

Q
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 2.III. FLIP-FLOP TYPES

• Example of time-diagram for

a negative edge-triggered J-K
flip-flop. (Observe the circle
next to the clock input “C”.)
2. Biestables

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 2.III. FLIP-FLOP TYPES

• D flip-flop: Input D (“data”) is used to determine the output

values, Q and Q � as stated in the table below.
• Can be derived from a J-K flip-flop by setting J = D,K = D �.
• Can be positive or negative edge-triggered. (The table shown
corresponds to the positive edge-triggered type.)
• Can be regarded as a one-bit memory cell.

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 2.III. FLIP-FLOP TYPES

• Example of time-diagram for a positive edge-

triggered D flip-flop
2. Biestables

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 2.III. FLIP-FLOP TYPES

• T flip-flop: An input called T (“toggle”) determines the operation

mode as stated in the table below.
• Can be derived from a J-K flip-flop by setting J = K = D.
• Can be positive or negative edge-triggered. (The table shown
corresponds to the positive edge-triggered type.)
2. Biestables

T
Q0 Q0 No change
Q0 Q0 Toggle
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 2.III. FLIP-FLOP TYPES

• Example of time-diagram for a negative edge-

triggered T flip-flop.

T
2. Biestables

CLK

T 0 1 0 0 1 1

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 2.IV. ASYNCHRONOUS CONTROL SIGNALS

• Often, flip-flops include additional asynchronous inputs to

modify the outputs regardless of the clock signal.
• Asynchronous signals can be high-level active or low-
level active.
2. Biestables

• Usual asynchronous signals include:

 Clear (CLR), also called “reset”: Q = 0.
 Preset (PRE), also called “set”: Q = 1.
• In the example shown, both “clear”
and “preset” are low-level active.

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 2.IV. ASYNCHRONOUS CONTROL SIGNALS

• Example of time-diagram for a

positive edge-triggered D flip-flop
with active-low asynchronous
control signals.
2. Biestables

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 SEQUENTIAL SYSTEMS

1. Introduction
2. Bi-stables
3. Registers
I. Introduction
II. Register types
III. Parallel-in parallel-out registers
Índex

IV.Shift registers
4. Counters.

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 3.I. INTRODUCTION

• Registers, memories, and counters are among

the simplest and more common electronic
sequential systems.
• Available in the form of MSI ICs.
3. Registres

• D flip-flops are the main building block.

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 3.I. INTRODUCTION

• A D flip-flop can store one bit.

3. Registres

• A register is a system made up of

• n D flip-flops
• with a common clock signal
• common asynchronous control signals
• The register can store n bits.

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 3.II. REGISTER TYPES

• Registers can be classified according to their

serial or parallel input and output format.
parallel-in parallel-out parallel-in serial-out
3. Registres

serial-in parallel-out serial-in serial-out

shift registers
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 3.III. PARALLEL-IN PARALLEL-OUT REGISTERS

• A single clock edge is used to simultaneously store the

input data (D0, …, Dn-1 ).
• Output data updated after the clock edge
• Used for data storage.
3. Registres

0 1 0 1

X0 X1 X0 X1

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 3.IV. SHIFT REGISTERS

• Data are transferred between D flip-flops.

 The data output of a D flip-flop is connected to the data
input of the next one.
 Combinational circuits can be added to enhance the
functionality of the system. (E. g., choosing between left-to-
3. Registres

right and right-to-left shifting, parallel loading, enabling...)

• Types
 Serial-in serial-out.
 Useful to generate delays between two (or more) signals.
 Parallel-in serial-out, serial-in parallel-out.
 Useful for data conversion.

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 3.IV. SHIFT REGISTERS

• Serial-in serial-out
(left-to-right): data
“advances” from left to
right, requiring n clock
3. Registres

edges to be stored
and n clock edges to
be retrieved.

• Negative-edge
triggered shift
registers are also
possible.

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 3.IV. SHIFT REGISTERS

• The flow of data within electronic digital systems tends to

take place in parallel (several bits at a time: bus).
• However, to save resources (wires), data transmission
between different systems is often performed in series
3. Registres

(one bit at a time).

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 3.IV. SHIFT REGISTERS

• The serial-to-parallel and parallel-to-serial data

conversion is carried out using shift registers.

parallel write-in parallel read-out

3. Registres

1011 1011
serial data
transmission
I(n–1..0) Q(n–1..0)
CLK SHIFT REGISTER CLK SHIFT REGISTER
SO = Q0 SI
1011 1 ????
?101 1 1???
??10 0 11??
???1 1 011?
???? ? 1011

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 SEQUENTIAL SYSTEMS

1. Introduction
2. Bi-stables
3. Registers
4. Counters
I. Introduction
II. Synchronous counters.
Índex

III. Counter module

IV.Digital clock

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 4.I. INTRODUCTION

• Counter: electronic sequential system that can be in N

different states (S0, S1, S2, …. SN-1) running sequentially
through them by means of a clock signal.

• The clock signal can be rising-edge active or falling-edge

4. Comptadors

active (not both).

• Usage: time measuring, event counting, frequency

dividers,...
000
001

110 010

101 011
100 29
 4.I. INTRODUCTION

• The number of states is referred to as the counter module.

Example: an increasing, 3-bit binary counter counts from 0 to 7
and, therefore, has 8 different states and its module is 8.
4. Comptadors

• The counter is made up of flip-flops.

• In a synchronous counter the changes in its flip-flops are

synchronized with the edges of the clock.

• The counter has a cyclical behaviour.

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 4.II. SYNCHRONOUS COUNTERS

• Synchronous
• 3-bit binary up counter
• Positive-edge triggered.
4. Comptadors

T flip-flop

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 4.II. SYNCHRONOUS COUNTERS

• Synchronous
• 3-bit binary up counter
• Positive-edge triggered.
4. Comptadors

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 4.IV. SYNCHRONOUS COUNTERS

• 4-bit binary up counter, negative-edged triggered.

4. Comptadors

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 4.III. THE MODULE OF A COUNTER

• Assume an ascending n-bit binary counter.

• “Natural” module is 𝑁𝑁 = 2𝑛𝑛 .
• In base-10, counting sequence is 0, …, 𝑁𝑁 − 1.
4. Comptadors

• But, what if we want the module to be 𝑁𝑁 ′ , with 𝑁𝑁 ′ < 𝑁𝑁

and 𝑁𝑁 ′ not a power of 2?
• Answer:
Use a counter equipped with an asynchronous “clear”
signal and, possibly, some additional gates.

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 4.III. THE MODULE OF A COUNTER

• Example: Counting from 0 up to 11.

• Desired module is 𝑁𝑁′ = 12.

• As 23 < 12 < 24 :
4. Comptadors

Use a 4-bit binary up counter provided with an

asynchronous “clear” signal. (Notice the “natural” module
is 𝑁𝑁 = 16.)

• Add a logic gate to…

• Detect the last desired state of the counter ( 𝑁𝑁′ =
1210 = 11002 ).
• Reset (clear) the counter and
• Make it start over again from the initial state (00002)
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 4.III. THE MODULE OF A COUNTER

• It suffices to detect the two ones in the binary encoding of

12 (1210 = 11002 ).
• In general, it suffices to detect the ones in the binary
encoding of the module.

CLK
t
Q 0 1 2 3 4 5 6 7 8 9 A B 0 1 2 3 4 5
Q3 Q2 Q1 Q0 C t
CLR Q3
4-BIT COUNTER
CLK t
CLR
t

glitch

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 4.IV. DIGITAL CLOCK

 Seven-segment displays.
 Input signal: AC mains (60 Hz).
4. Comptadors

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BIBLIOGRAPHY

 DIGITAL FUNDAMENTALS, 11TH edition, Thomas L. Floyd. Editorial Pearson.

Chapters 7, 8, and 9.
Fundamentos de sistemas digitales, 9ª edición, Thomas L. Floyd. Editorial
Pearson. Chapters 7, 8, and 9.

A digital copy of the book (in Spanish) is available through the

library website: link.

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