FPGA Implementation of Adaptive

Filtering Algorithms for Noise

Cancellation—A Technical Survey

Pankaj Goel and Mahesh Chandra

Abstract In an environment where noise is our constant companion, quality of

speech signal degrades considerably. Over a period of time, researchers have devel-
oped and implemented many algorithms to enhance the quality of speech signal.
In this article, an attempt is made to present the significant work of researchers in
the area of Field-Programmable Gate Arrays (FPGA) implementation of noise can-
cellation algorithms using adaptive filters. FPGA based hardware platforms have
been commonly used to implement prototypes for active noise canceller (ANC) sys-
tems. The commonly used software tools for FPGA based implementations include
MATLAB/Simulink, Modelsim, Xilinx System Generator, Xilinx ISE, Vivado design
suite, and Altera Quartux II development platform. The performance of the algo-
rithms achieved using FPGA based platforms give an insight of what may be achieved
from the final commercial implementation. In this study, it has been observed that
the performance of various adaptive filter structures varies considerably in terms of
rate of convergence, throughput rate, improvement in signal-to-noise ratio (SNR),
maximum clock speed, hardware complexity, power consumption and cost.

Keywords Active noise cancellation · Speech enhancement · Adaptive

algorithm · DSP · FPGA · Hardware implementation

1 Introduction

The unwanted signal present in the information bearing signal is referred to as noise
which degrades the signal strength in terms of quality and intelligibility. Noise can
be broadly classified into two main categories, namely White Noise or Non-White

P. Goel (B) · M. Chandra

Electronics and Communication Engineering, BIT Mesra, Mesra, Ranchi 835215,
Jharkhand, India
e-mail: pankajgoel80@gmail.com
M. Chandra
e-mail: shrotriya@bitmesra.ac.in

© Springer Nature Singapore Pte Ltd. 2019 517

V. Nath and J. K. Mandal (eds.), Proceedings of the Third International
Conference on Microelectronics, Computing and Communication Systems,
Lecture Notes in Electrical Engineering 556, https://doi.org/10.1007/978-981-13-7091-5_42
518 P. Goel and M. Chandra

Noise. White noise is spectrally flat but non-white is not. Furthermore, noise can
either be stationary like computer’s fan noise or non-stationary like Machine gun
noise.
Various commonly used adaptive filters used to diminish the noise are Least
Mean Square (LMS) algorithm, Normalized LMS algorithm (NLMS), Variable Step
Size LMS algorithm (VSSLMS), Filtered-X LMS algorithm (FxLMS), Hybrid LMS
algorithm and Recursive Least Square (RLS) algorithm.
The hardware implementation can be done using either Digital Signal Processors
(DSPs) or Field-Programmable Gate Arrays (FPGAs). DSPs have advantages such
as the use of C programming language and therefore more user-friendly, and rela-
tively simple design flow, whereas FPGAs offer advantages such as high degree of
parallelism and low power consumption.
In this article, the important work of researchers is presented in the field of FPGA-
based hardware implementations of noise cancellation algorithms using adaptive
filters. FPGA implementations of different algorithms are compared based on their
maximum clock speed, resources required, power consumption and cost, and in the
end, a conclusion is drawn.

2 Adaptive Filtering Algorithms

An adaptive filter is a filter capable of tracking the variations in the statistical charac-
teristics of input data and capable of self-adjusting its parameters. In non-stationary
environments where characteristics of the environment are unknown or changing
with time, a fixed filter doesn’t give good results. In such situations, an adaptive filter
gives efficient results as an adaptive filter can track the changes in the environment
and update the filter weight vector coefficients. Adaptive filters are usually more
complex and difficult to implement as compared to non-adaptive systems, but such
type of systems offers increased system performance whenever the input signal is
time varying or its characteristics are unknown [1].
An active noise cancellation (ANC) system is one which is used to suppress the
noise from the signal of interest. One of the popular algorithms used for ANC is
Least Mean Square (LMS) algorithm devised by Widrow and Hoff in 1959. It is a
widely used algorithm because of its simplicity. This algorithm belongs to the family
of stochastic gradient algorithms involving filtering and adaptive process.
The ANC system consists of two types of inputs, one is a primary input also called
as source signal s(n) and the other is reference input or noise signal x(n). The source
signal gets distorted by a noise signal x 1 (n) which is usually correlated with noise
signal x(n). The reference signal can vary in amplitude, phase or time with respect
to noise portion of the primary signal [2, 3].
The desired signal d(n) is the result of addition of primary signal s(n) to correlated
noise signal x 1 (n). The reference signal x(n) will be given to adaptive filter such that
its output y(n) can be subtracted from desired signal d(n) to yield error signal e(n).
FPGA Implementation of Adaptive Filtering … 519

Fig. 1 Active noise d ( n ) = s ( n ) + x1( n )

cancellation system using
LMS adaptive filter
algorithm x( n ) y(n) +

Adaptive - e( n )
filter ∑

The output of the summer block, e(n) = d(n) − y(n) is then fed back to adaptive
filter in order to update filter coefficients [4, 5] (Fig. 1).
One of the primary disadvantages of the LMS algorithm is slow convergence
rate due to the fixed step size for each tap weight in every iteration. To improve the
performance of active noise cancellation system, a variant of LMS algorithm known
as Variable Step Size Least Mean Square (VSSLMS) algorithm was developed in
which step size is usually expressed as a vector μ(n) for each iteration. Each element
of vector μ(n) can have different step size value corresponding to an element of
filter tap weight vector. During the adaptation process if w(n) is far from its optimum
value, the step-size parameter will be relatively high to achieve fast convergence and
whenever the filter coefficients w(n) approaches the steady-state solution, the step-
size parameter will decrease so as to reduce the excess Mean Square Error (MSE).
There are many other variants of LMS such as Normalized LMS (NLMS), Block
LMS (BLMS), Filtered-x LMS (FxLMS), Sign-error LMS algorithm that has been
developed by researchers to improve the performance.

3 FPGA Implementation of Adaptive Filter Algorithms

As the integrated circuit technology has made rapid progress in the past few decades,
multiple hardware platforms have come into existence for implementation of compu-
tationally intensive signal processing applications. Using these hardware platforms,
designers can implement the prototype hardware for an algorithm in a short period
of time. Therefore, hardware implementation of adaptive filtering algorithms has
become an interesting area of research lately. As adaptive filtering algorithms find
applications in diverse fields, choosing an appropriate hardware for an application is
a key for successful commercial implementation. A particular hardware should be
chosen keeping in mind the performance/area/cost tradeoff.
DSPs and FPGAs have emerged as predominant hardware platforms for adaptive
filtering algorithms implementation. In the past, the use of DSPs was ubiquitous, but
with the need of many applications outstripping the processing capabilities of DSPs,
the use of FPGAs is growing rapidly. Apart from higher processing capabilities
compared to DSPs, FPGAs offer many other advantages such as high degree of
parallelism, low power consumption and low cost.
520 P. Goel and M. Chandra

Adaptive filter architectures have been implemented on FPGA platform using

different approaches. One approach is to implement filter structures using hardware
description languages such as VHDL or Verilog and the second approach is to imple-
ment using MATLAB/Simulink and Xilinx System Generator development tools.
The concept of retiming has been used to implement highly pipelined adaptive filter
architectures and the maximum clock speed of retimed adaptive filter architectures
thus obtained is found to be superior to conventional architectures [6].
Three different architectures have been proposed for implementing a least mean
square (LMS) adaptive filtering algorithm to enhance signal-to-noise ratio (SNR)
of speech signal, and then the comparison is done based on the performance and
area for different filter lengths. To implement the architecture, Xilinx Multimedia
board is used. The audio is captured/playback using on-board AC97 audio codec
and the three architectures are implemented using Xilinx Virtex-II FPGA platform.
The three proposed architectures are pure software architecture, HW/SW Co-design
architecture and pure HW architecture [7].
Adaptive noise cancellation systems based on LMS and NLMS algorithms are
implemented to remove the 60 Hz interference from ECG signal. MicroBlaze soft
processor core is used to implement the two architectures. The first one uses 16 bit
fixed-point fractional format based on LMS algorithm whereas the second architec-
ture uses 16-bit fixed-point integer format based on NLMS algorithm [8].
An adaptive filter based on NLMS algorithm is implemented on FPGA platform. In
the proposed implementation, to reduce the computational complexity and improve
the speed of the architecture, bit-shift technique is used. The results obtained con-
firm that when the normalized frequency is set to 0.04375π offset from the centre
frequency, the attenuation value obtained is 99.21 dB [9].
Delayed LMS adaptive filter algorithm is implemented on FPGA platform using
VHDL hardware description language. Instead of a single large block, a number of
sub-blocks are used with efficient adder tree in the implemented structure which
results in less area and power consumption, and more efficient in terms of area-delay
product (ADP) and energy-delay product (EDP) [10].
A Sign-error LMS algorithm based pipelined adaptive filter architecture is imple-
mented with an aim to reduce the computational complexity. The proposed archi-
tecture has low latency, high throughput, a simple structure but at the same time,
its convergence rate is lesser compared to DLMS. The calculations required for
sign-error LMS algorithm implemented using 4:2 adder are less than half of the
conventional architectures. Also, this design provides faster convergence and higher
throughput than the delayed LMS (DLMS) algorithm [11].
High throughput fast block LMS (FBLMS) adaptive algorithm is implemented
on FPGA platform. Concept of distributed arithmetic is used to design the filter
structure. The advantage of Block LMS algorithm compared to LMS algorithm is
that the throughput rate is higher and area consumption is reduced. In Block LMS,
error calculations are not done for every sample but once per block of data. Similarly,
weights are not updated for every sample rather over a block of data. The resultant
FPGA Implementation of Adaptive Filtering … 521

structure is highly computation and area efficient. FPGA implementation of the

proposed structure confirms that it takes 45% less area than that of the existing
FBLMS algorithm based adaptive filter [12].
High speed highly pipelined adaptive filter structures based on Delayed LMS
algorithm has been implemented on Virtex-II Pro FPGA platform. To achieve fully
pipelined circuits, the delays in DLMS have been redistributed using the concept of
retiming. The delay reduction is 66.7% and convergence time is five times faster in
the resultant retimed delayed architectures. The throughput rate of 182 Msample/s is
achieved using retimed architectures implemented using virtex-II FPGA technology
[13].
High speed highly pipelined architectures for adaptive noise cancellation was
implemented on Virtex-II Pro XC2VP30 FPGA device. To achieve highly pipelined
parallel architectures for better performance, retiming technique was used resulting
in higher performance than conventional architectures. Retiming is a technique to
relocate delay elements in a circuit such that its input/output characteristics are not
affected. The retimed highly pipelined 64-tap direct form adaptive filter structure
has maximum operating frequency of 187.614 MHz compared to the conventional
structure which has maximum operating frequency of 10.576 MHz. It has also been
observed that the hardware resource consumption varies considerably for different
structures. For direct form retimed delayed LMS 64-tap structure (DF-RDLMS),
2464 delay elements are required whereas only 397 and 325 delay elements are
required for binary tree form retimed delayed LMS 64-tap structure (TDF-RDLMS)
and transpose form retimed delayed LMS 64-tap structure (TF-RDLMS), respec-
tively. Sequential architecture has the advantage that it require less hardware com-
pared to parallel architectures, and therefore suitable especially for large size filters.
Simulation results show an SNR improvement of approximately 8.8 dB on speech
signal taken from TIMIT database for input SNR of 6.57 dB and approximately
28 dB on ECG signals taken from MIT-BIH arrhythmia database for input SNR of
1.2436 dB [14–16].
Retimed adaptive filter structures based on delayed LMS algorithm have been
implemented for speech enhancement application and synthesis results obtained for
different FPGA platforms. It has been observed from the results that the implementa-
tion on different FPGA platforms leads to considerable variation in the performance
of various filter structures. For instance, the Maximum operating frequency and power
consumption of TF-RDLMS architecture for Virtex-4 series device are 90.901 MHz
and 448.16 mW respectively whereas for Spartan-6 series device is 96.899 MHz and
20.45 mW respectively. Therefore careful examination of the performance parame-
ters should be done while selecting an FPGA device for an application. Simulation
has been performed to check the improvement in SNR. For a Hindi speech signal
taken from Hindi speech database and white noise from Noisex 92 database, output
SNR of approximately 38.75 dB is achieved for input SNR of 20.41 dB [17, 18].
High-speed parallel structures are implemented using Delayed block FxLMS
(DBFxLMS) and delayed block FsLMS (DBFsLMS) algorithms. To design an active
noise cancellation system for linear noise processes, Filtered-X LMS-based algo-
rithms are suitable. The performance of the FxLMS algorithm diminishes if the
522 P. Goel and M. Chandra

noise source or medium introduces nonlinearity. The throughput rate for DBFxLMS
and DBFsLMS structures is higher (nearly L times) and hardware consumption is
less than the DFxLMS and DFsLMS structures. The DBFxLMS structure has more
than L times higher throughput rate, consumes L times more multipliers and adders,
and (3Q + 2)(3Q + 2) less registers (where Q is the secondary path filter length)
as compared to the existing FxLMS-based structure. The proposed DFxLMS and
DBFxLMS structures have 55 and 58% less ADP, 30 and 41% less EPS and signifi-
cantly higher throughput than those of the existing FxLMS-based structures [19].
Wavelet-based filters are very effective to remove noise from the information bear-
ing signals. To remove power line interference from ECG signal, a real-time denois-
ing technique using wavelet has been implemented on FPGA. In this work, Donoho
denoising algorithm based architecture and soft-thresholding technique is used. The
concept of this algorithm is based on the assumption that the wavelet coefficients
with smaller magnitudes are caused by noise and wavelet coefficients with larger
magnitudes are caused by information bearing signal. Using the soft-thresholding
technique, the smaller wavelet coefficients are replaced by zero and larger wavelet
coefficients are retained. Noise is estimated using the second level wavelet coeffi-
cients because power line interference is a narrow band signal [20].
Cutset retiming and clock period minimization techniques are used to obtain opti-
mized retimed filter structures. A lattice filter structure has been implemented using
Spartan3E series FPGA platform. The filter structure obtained after cutset retiming
technique consumes 190 slices whereas the filter structure obtained after clock period
minimization technique consumes 220 slices. To optimize the performance, various
optimization techniques such as supply voltage scaling, parallel prefix tree adders,
etc. is used at structural level [21].
An LMS adaptive filter using conventional multiplier adder has been implemented
for active noise control application. It has been observed that the LMS adaptive filter
is able to successfully track the unknown system with the convergence speed of
1.46 ms at 1/210 step size [22].
LMS adaptive filter based on the transposed direct form has been implemented on
Xilinx Spartan-3 FPGA platform. Different types of noises were considered such as
fan noise, car noise, and sinusoidal noise. ModelSim SE 6.2c simulator and Xilinx
ISE 9.li development environment was used for the simulation and synthesis of the
VHDL design, respectively. Noise reduction is achieved sufficiently for stationary
noise in a frequency range between 188 and 4000 Hz. The results obtained in the
work have proved that the FPGA platform is well suited for the complex real-time
audio processing tasks in augmented reality audio systems [23] (Table 1).
FPGA Implementation of Adaptive Filtering …
Table 1 Comparison of various adaptive noise cancellation algorithms implemented on FPGA
Platform
S. No. Algorithm
1 LMS adaptive filtering
implementation [7]
2 Adaptive noise cancellation
systems based on LMS and
NLMS algorithms [8]
3 Normalized LMS algorithm
implementation using
bit-shift technique [9]
4 DLMS filter structure
implementation using
optimized pipelining
technique [10]
5 Pipelined Sign-error LMS
adaptive filter architecture
[11]
6 Fast block adaptive filter
implementation using
distributed arithmetic [12]
7 High speed highly pipelined
Delayed LMS filter
structures FPGA
implementation [13]
8 LMS based Parallel and
Sequential architectures
implementation based on
Retiming concept [14]
Development Tool /Imple-
mentation Platform
Xilinx MicroBlaze
development tool and Virtex
II FPGA board
Xilinx MicroBlaze
development tool and Xilinx
FPGA implementation
FPGA platform
VHDL hardware description
language and FPGA
platform
MATLAB
FPGA platform
MATLAB/Simulink and
Xilinx System Generator
development tools and
Virtex-II Pro FPGA board
MATLAB/Simulink and
Xilinx System Generator
development tools and
Virtex-II Pro FPGA board
523
Significant Outcomes
System speed increases but
with an extra area and lower
flexibility
60 Hz interference
suppression from ECG
signal in real time is
achieved
Attenuation of 99.21 dB is
obtained with the proposed
design
Proposed design results in
better ADP & EDP, and less
area and power consumption
Faster convergence and
higher throughput compared
to conventional adaptive
filter structures
Proposed algorithm takes
45% less area than existing
Fast block LMS algorithm
RDLMS architectures are
superior to conventional
LMS architectures in terms
of maximum operating
frequency. The delay
reduction is 66.7%,
throughput rate is
182 Msample/s and
convergence time is five
times faster in the resultant
retimed delayed
architectures
Sequential architecture
requires less hardware
compared to parallel
architectures, and therefore
suitable especially for large
size filters. SNR
improvement of approx.
8.8 dB and 28 dB is
achieved for speech signal
and ECG signal with input
SNR of 6.57 dB and
1.2436 dB respectively
(continued)
524 P. Goel and M. Chandra

Table 1 (continued)
S. No. Algorithm
9 FPGA implementation of
High speed retimed delayed
LMS algorithm based
adaptive filter structures
[17]
10 Delayed block FxLMS
(DBFxLMS) and delayed
block FsLMS (DBFsLMS)
algorithms implementation
[19]
11 Donoho denoising
algorithm based wavelet
filter architecture [20]
12 Lattice filter implementation
based on cutset retiming and
clock period minimization
technique [21]
13 conventional multiplier
adder-based LMS adaptive
filter implementation [22]
14 Transposed direct form
LMS adaptive filter
implementation [23]
Development Tool /Imple-
mentation Platform
MATLAB/Simulink and
Xilinx System Generator
development tools and
Spartan 6 FPGA board
Hardware/ASIC
implementation
MATLAB/Simulink, Xilinx
system generator
development tool and Virtex
II FPGA board
VHDL hardware description
language and Xilinx FPGA
Sparten3E XC3S100E
device
Altera Quartux II
development platform and
Altera DE2 development
board
MATLAB/Simulink,
Modelsim SE6.2c, Xilinx
ISE 9.1i development
environment, Xilinx
Spartan-3 FPGA board
Significant Outcomes
Implementation on different
FPGA platforms leads to
considerable variation in the
performance of various filter
structures. Therefore careful
examination of the
performance parameters
should be done while
selecting an FPGA device
an application
The proposed DFxLMS and
DBFxLMS structures have
55 and 58% less ADP, 30
and 41% less EPS and
significantly higher
throughput than those of the
existing FxLMS-based
structures
Efficiently removes power
line interference from ECG
signal
Hardware consumption is
less than conventional filter
structures
LMS adaptive filter
successfully track the
unknown system with the
convergence speed of
1.46 ms at 1/210 step size
Noise reduction is achieved
sufficiently for stationary
noise in a frequency range
between 188 and 4000 Hz

4 Conclusion

Efficient noise cancellation techniques have a wide range of applications in wireless

and mobile communication systems. FPGA implementations of several adaptive
filter algorithms having different characteristics have been reviewed in this paper.
The parallel and sequential retimed adaptive filter structures have better maximum
operating frequency as compared to conventional adaptive filters but at the cost of
FPGA Implementation of Adaptive Filtering … 525

more hardware resources consumption. For instance, the retimed highly pipelined
64-tap direct form adaptive filter structure has maximum operating frequency of
187.614 MHz compared to the conventional structure which has maximum operat-
ing frequency of 10.576 MHz. The sign-error LMS algorithm and fast block LMS
(FBLMS) algorithms have relatively less computational complexity. For instance,
the proposed FBLMS algorithm implemented using distributed arithmetic takes 45%
less area than existing Fast block LMS algorithms. The DBFxLMS and DBFsLMS
algorithms have 55 and 58% less area-delay product (ADP), 20 and 30% less energy
per sample (EPS) than those of existing FxLMS-based algorithms. Hence this article
is an attempt to give an insight into the research work done in the field of FPGA
implementation of various adaptive filter algorithms for noise cancellation applica-
tions.

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