EE212L: Semiconductors Devices

Semester Project
Aimon Humayun 2019-EE-51
Sehar Khan 2019-EE-54

Problem Statement
Design and simulate a variable power supply which takes an AC input of 230V rms at 50 Hz and
gives a DC output that can vary in the range of 0-30V and maximum output load current should
be 1-1.5A.

Circuit Design
a) Block Diagram
Following figure shows the complete block diagram of the power supply.

b) Design Explanation
Step Down Transformer: A Step down Transformer is a type of transformer, which
converts a high voltage at the primary side to a low voltage at the secondary side.If we speak
in terms of the coil windings, the primary winding of a Step down Transformer has more
turns than the secondary winding.
Full Wave Rectifier: A full wave rectifier converts both halves of each cycle of an
alternating wave (AC signal) into pulsating DC signal

Smoothing Capacitors: The smoothing capacitor converts the full-wave rippled output of
the rectifier into a more smooth DC output voltage. We add capacitors in parallel before load
to get the following wave.

Regulator: A voltage regulator is a system designed to automatically maintain a

constant voltage. We use a regulator which is compatible with our requirements in this
project.
c) Design Calculation

Step Down Transformer

Full Wave Rectifier

We use two diodes to rectify the AC input. Diode D1 is ON during the positive half cycle
and Diode D2 is ON during the negative half cycle.

Smoothing Capcitors
Using the Formula

Load Resistance = 200 Ohm.

Frequency of rectified wave will be double the original frequency. So, f = 100 Hz. Vp
= 32.28 V

In order to get a small value of ripple voltage, we keep the value of VDC nearly equal to
Vp. Then we find the capacitance using the formula given above.
For VDC = 34.22V, C = 16000 uF.

In order to use standard values, we are using 3 capaciors.

C1 = 10,000 uF.
C2 = 4,700 uF.
C3 = 1,500 uF.
Hence, C = 16200 uF.

As a result, ripple voltage is 0.1 V.

 Regulator
In our project we use LT317A. The capacitors at the input and output of regulator are
used to avoid and unstability in the voltage.

In order to get a voltage of 30V at the output of lt317a the voltage drop between OUT and
ADJ should be 1.25V.
We achieve this by using voltage divider circuit.
 We adjust the values of resistance using this ratio.
If we take R1 = 220 Ω, the R2 = 5060 Ω. But to keep R2 standard we take R2 = 5.1kΩ.
Then Voltage at output is 30V. By using a load resistance of 24 Ohms, the output
current is 1.3A.

Circuit Simulation a. Circuit Diagram

b. Results
Load Voltages and Load Currents at different values of resisters R3 and R4.

Load Voltage and Load Current at 𝑅3 = 5.1𝑘Ω 𝑎𝑛𝑑 𝑅4 = 24Ω

Vout = 30 V and I out = 1.25A
Load Voltage and Load Current at 𝑅3 = 2.4𝑘Ω 𝑎𝑛𝑑 𝑅4 = 15Ω
Vout = 15 V and I out = 1 A

Load Voltage and Load Current at 𝑅3 = 3.3𝑘Ω 𝑎𝑛𝑑 𝑅4 = 20Ω

Vout = 20 V and I out = 1 A
 Load Voltage and Load Current at 𝑅3 = 4.7𝑘Ω 𝑎𝑛𝑑 𝑅4 = 20Ω Vout

= 28 V and I out = 1.4A

Load Current out of range 1-1.5A as Load Voltage → 0 at 𝑅3 = 200Ω 𝑎𝑛𝑑 𝑅4 = 12Ω

Vout = 2.4 V and I out = 0.2 A (See improvement section)

c. Input and Output Waveform

 AC input and DC output obtained at 𝑅3 = 5.1𝑘Ω 𝑎𝑛𝑑 𝑅4 = 24Ω

Output Ripple

3. Comments and Conclusion

Results
The designed power supply takes input of 230 Vrms at 50 Hz and gives variable DC output. We
use the voltage divider circuit to achieve variable DC at the output.
R3 (ohm) Load R (ohm) Output Voltage (V) Load Current
(A)
5.1k 24 30 1.25
2.4k 15 15 1
3.3k 20 20 1
4.7k 20 28 1.4

It shows that all the values are as desired.

Improvements
We observe that as the value of output voltage reaches 0V it is not possible to achieve current
range of 1-1.5A. The regulator IC doesn’t provide enough current. We can improve this by using
a Common Base Transistor in such a way the collector terminal is attached to the input of
regulator and base terminal is attached at the output terminal of the regulator and load resistance
is connected between emitter terminal and ground. In this way the requirement of current can be
achieved.

2019ee51/54