Class Test 2nd year 2nd Semester 2020-2021, Dept of ETCE, JU , Full Marks; 100 (5x20 =100)

Subject: Digital circuits and systems

Q1. (a). What are Multiplexers, active low & active high output type decoders, Full & half adder, Serial adder(4bits)&
parallel adder(4bits) and carry look ahead (CLA)adder ? Write their logical expressions and explain their functions with
necessary sketches etc if needed. Distinguish between (i) Full & half adder , (ii) Serial & parallel adder(4bits each) , (iii)
Full adder & CLA Adder , active low & active high output type decoders.
(b). Realize 8:1 MUX based Full adder and then make it by using 4:1 MUX based with proper explanation. Also realize
the Full adder (i) using active low output type decoder (ii) using active high output type decoder
Q2. (a) . Define a synchronous sequential circuit and give one example. What are Moore and Mealy
machines? How are they different from each other( give in tabular form)? Explain with example
conversion of Mealy machine into Moore machine. Why are they called Finite State Machines (FSM)?
Design a serial full adder. Why are synchronous sequential machines called deterministic machines?
(b) Discuss the steps involved in the design of an SSLC. Illustrate your explanation by using a suitable
example. Define a synchronous detector and give an example. Distinguish between forbidden and
don't care condition in digital circuit with suitable examples.
Q3. (a) What are cycles and races? Give the differences between them. Explain critical and non-critical races
with suitable examples
(b) What do you mean by ASLC? Give its classification and write the differences among them in
tabular form. Explain the following terms: (i) Input States, (ii) Internal States, (iii) Excitation
Variables and (iv) Stable State.
(b) Explain the following statements:
(i) " There is no specific advantage of using ASLCs over SSLCs "
(ii) " The reduction of the truth table of an incompletely specified machine is a trial-and-repeat
process ".
Q4. (a)Explain the difference between SSLC &ASLC(in tabular form). How design steps are different.

(b) What do you mean by the analysis of a SSL circuit? Analysis the circuit given below.

(c )An 8-bit microprocessor has a 16-bit address bus. The first 15 lines of the address are used to select a bank of
32K bytes of memory. The high-order bit of the address is used to select a register which receives the contents of
the data bus. Explain how this configuration can be used to extend the memory capacity of the system to 8 banks
of 32K bytes each, for a total of 256 K bytes of memory.

(d) What do you mean by hazards in digital circuits and explain the causes of hazards.

Q5. (a) What is the need of memory? Discuss volatile and non-volatile memories. Why RAM is known as random access
memory? Why in SRAM two CMOS inverters are cross-coupled? Why it is required to precharge the bit –lines after
every read and write operation? Discuss the read and write operation of SRAM cell.

(b)A 4-word Rom with 8:bit- lines has the following content: 0: 10001101, 1:11011010, 2:00 110110, and 3:01111100. Draw
the schematics of the ROM implemented using

(i) MOS NOR ROM, and

(ii) MOS NAND ROM.
(c)What are the differences among sequential access, direct access, and random access? What is the general relationship
among access time, memory cost and capacity?
(d )To reduce the delay an adder called a carry look ahead adder may be designed. It uses a complex combinatorial circuit to
generate the final carry simultaneously with the sum bits. For a n bit adder the total delay is 3tp and is independent of n.
However, the combinational circuit to generate the carry is very complex. Establish it.