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UC3844B, UC3845B, UC2844B, UC2845B High Performance Current Mode Controllers
UC3844B, UC3845B, UC2844B, UC2845B High Performance Current Mode Controllers
UC3844B, UC3845B, UC2844B, UC2845B High Performance Current Mode Controllers
UC2844B, UC2845B
High Performance
Current Mode Controllers
The UC3844B, UC3845B series are high performance fixed frequency
current mode controllers. They are specifically designed for Off−Line
and dc−dc converter applications offering the designer a cost−effective
solution with minimal external components. These integrated circuits http://onsemi.com
feature an oscillator, a temperature compensated reference, high gain
error amplifier, current sensing comparator, and a high current totem pole
output ideally suited for driving a power MOSFET. PDIP−8
Also included are protective features consisting of input and N SUFFIX
reference undervoltage lockouts each with hysteresis, cycle−by−cycle CASE 626
current limiting, a latch for single pulse metering, and a flip−flop 8
which blanks the output off every other oscillator cycle, allowing 1
output deadtimes to be programmed from 50% to 70%.
These devices are available in an 8−pin dual−in−line and surface SOIC−14
mount (SOIC−8) plastic package as well as the 14−pin plastic surface D SUFFIX
14
mount (SOIC−14). The SOIC−14 package has separate power and CASE 751A
ground pins for the totem pole output stage. 1
The UCX844B has UVLO thresholds of 16V (on) and 10V (off), ideally
suited for off−line converters. The UCX845B is tailored for lower voltage SOIC−8
applications having UVLO thresholds of 8.5V (on) and 7.6V (off). 8 D1 SUFFIX
Features CASE 751
1
• Trimmed Oscillator for Precise Frequency Control
• Oscillator Frequency Guaranteed at 250 kHz
• Current Mode Operation to 500 kHz Output Switching Frequency
PIN CONNECTIONS
• Output Deadtime Adjustable from 50% to 70%
• Automatic Feed Forward Compensation Compensation 1 8 Vref
• Latching PWM for Cycle−By−Cycle Current Limiting Voltage Feedback 2 7 VCC
• Internally Trimmed Reference with Undervoltage Lockout Current Sense 3 6 Output
• High Current Totem Pole Output RT/CT 4 5 GN
D
• Undervoltage Lockout with Hysteresis (Top View)
• Low Startup and Operating Current
Compensation Vref
•
1 14
These Devices are Pb−Free and are RoHS Compliant
NC 2 13 NC
• NCV Prefix for Automotive and Other Applications Requiring Voltage Feedback 3 12 VCC
Unique Site and Control Change Requirements; AEC−Q100 NC 4 11 VC
Qualified and PPAP Capable Current Sense 5 10 Output
VCC 7(12) NC 6 9 GND
RT/CT 7 8 Power Ground
Vref VCC
5.0V Undervoltage (Top View)
Reference Lockout
8(14) R
Vref
R Undervoltage
VC ORDERING INFORMATION
Lockout
7(11) See detailed ordering and shipping information in the package
dimensions section on page 15 of this data sheet.
RT/CT Output
Oscillator
6(10)
4(7) Latching
PWM Power DEVICE MARKING INFORMATION
Voltage Ground See general marking information in the device marking
Feedback
Input section on page 16 of this data sheet.
5(8)
2(3) Error Current
Output/ Amplifier Sense Input
Compensation
1(1) 3(5)
GND 5(9)
Pin numbers in parenthesis are for the D suffix SOIC-14 package.
Figure 1. Simplified Block Diagram
MAXIMUM RATINGS
Rating Symbol Value Unit
Bias and Driver Voltages (Zero Series Impedance, see also Total Device spec) (Note 1) VCC, VC 36 V
Total Power Supply and Zener Current (ICC + IZ) 30 mA
Output Current, Source or Sink (Note 2) IO 1.0 A
Output Energy (Capacitive Load per Cycle) W 5.0 mJ
Current Sense and Voltage Feedback Inputs Vin − 0.3 to + 5.5 V
Error Amp Output Sink Current IO 10 mA
Power Dissipation and Thermal Characteristics
D Suffix, Plastic Package, SOIC−14 Case 751A
Maximum Power Dissipation @ TA = 25°C PD 862 mW
Thermal Resistance, Junction−to−Air RqJA 145 °C/W
D1 Suffix, Plastic Package, SOIC−8 Case 751
Maximum Power Dissipation @ TA = 25°C PD 702 mW
Thermal Resistance, Junction−to−Air RqJA 178 °C/W
N Suffix, Plastic Package, Case 626
Maximum Power Dissipation @ TA = 25°C PD 1.25 W
Thermal Resistance, Junction−to−Air RqJA 100 °C/W
Operating Junction Temperature TJ +150 °C
Operating Ambient Temperature UC3844B, UC3845B TA 0 to +70 °C
UC2844B, UC2845B −25 to +85
UC3844BV, UC3845BV −40 to +105
Storage Temperature Range Tstg − 65 to +150 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The voltage is clamped by a zener diode (see page 9 Under Voltage Lockout section). Therefore this voltage may be exceeded as long as
the total power supply and zener current is not exceeded.
2. Maximum package power dissipation limits must be observed.
3. This device series contains ESD protection and exceeds the following tests: Human Body Model 4000 V per JEDEC Standard
JESD22-A114B, Machine Model Method 200 V per JEDEC Standard JESD22-A115-A
4. This device contains latch-up protection and exceeds 100 mA per JEDEC Standard JESD78
ELECTRICAL CHARACTERISTICS (VCC = 15 V [Note 5], RT = 10 k, CT = 3.3 nF. For typical values TA = 25°C, for min/max values
TA is the operating ambient temperature range that applies [Note 6], unless otherwise noted.)
UC284xB UC384xB, xBV, NCV384xBV
Characteristic Symbol Min Typ Max Min Typ Max Unit
REFERENCE SECTION
Reference Output Voltage (IO = 1.0 mA, TJ = 25°C) Vref 4.95 5.0 5.05 4.9 5.0 5.1 V
Line Regulation (VCC = 12 V to 25 V) Regline − 2.0 20 − 2.0 20 mV
Load Regulation (IO = 1.0 mA to 20 mA) Regload − 3.0 25 − 3.0 25 mV
Temperature Stability TS − 0.2 − − 0.2 − mV/°C
Total Output Variation over Line, Load, & Temperature Vref 4.9 − 5.1 4.82 − 5.18 V
Output Noise Voltage (f = 10 Hz to 10 kHz, TJ = 25°C) Vn − 50 − − 50 − mV
Long Term Stability (TA = 125°C for 1000 Hours) S − 5.0 − − 5.0 − mV
Output Short Circuit Current ISC − 30 − 85 −180 − 30 − 85 −180 mA
OSCILLATOR SECTION
Frequency TJ = 25°C fOSC 49 52 55 49 52 55 kHz
TA = Tlow to Thigh 48 − 56 48 − 56
TJ = 25°C (RT = 6.2 k, CT = 1.0 nF) 225 250 275 225 250 275
Frequency Change with Voltage (VCC = 12 V to 25 V) DfOSC/DV − 0.2 1.0 − 0.2 1.0 %
Frequency Change w/ Temperature (TA = Tlow to Thigh) DfOSC/DT − 1.0 − − 0.5 − %
Oscillator Voltage Swing (Peak−to−Peak) VOSC − 1.6 − − 1.6 − V
5. Adjust VCC above the Startup threshold before setting to 15 V.
6. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.
Tlow = 0°C for UC3844B, UC3845B Thigh = + 70°C for UC3844B, UC3845B
= − 25°C for UC2844B, UC2845B = + 85°C for UC2844B, UC2845B
= − 40°C for UC384xBV, NCV384xBV =+105°C for UC3844BV, UC3845BV
= +125°C for NCV384xBV
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UC3844B, UC3845B, UC2844B, UC2845B
ELECTRICAL CHARACTERISTICS (VCC = 15 V [Note 7], RT = 10 k, CT = 3.3 nF. For typical values TA = 25°C, for min/max values
TA is the operating ambient temperature range that applies [Note 8], unless otherwise noted.)
UC284xB UC384xB, xBV,
NCV384xBV
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UC3844B, UC3845B, UC2844B, UC2845B
ELECTRICAL CHARACTERISTICS (VCC = 15 V [Note 11], RT = 10 k, CT = 3.3 nF. For typical values TA = 25°C, for min/max
values TA is the operating ambient temperature range that applies [Note 12], unless otherwise noted.)
UC284xB UC384xB, xBV, NCV384xBV
Characteristic Symbol Min Typ Max Min Typ Max Unit
PWM SECTION
Duty Cycle %
Maximum (UC284XB, UC384XB) DC(max) 47 48 50 47 48 50
Maximum (UC384XBV) − − − 46 48 50
Minimum DC(min) − − 0 − − 0
TOTAL DEVICE
Power Supply Current ICC mA
Startup (VCC = 6.5 V for UCX845B, − 0.3 0.5 − 0.3 0.5
Startup (VCC = 14 V for UCX844B, BV)
Operating (Note 11) − 12 17 − 12 17
Power Supply Zener Voltage (ICC = 25 mA) VZ 30 36 − 30 36 − V
11. Adjust VCC above the Startup threshold before setting to 15 V.
12. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.
Tlow = 0°C for UC3844B, UC3845B Thigh = + 70°C for UC3844B, UC3845B
= − 25°C for UC2844B, UC2845B = + 85°C for UC2844B, UC2845B
= − 40°C for UC384xBV, NCV384xBV = +105°C for UC3844BV, UC3845BV
=+125°C for NCV384xBV
ÄÄÄÄÄ
ÄÄÄÄÄ
80 75
VCC = 15 V 1.CT = 10 nF 3
ÄÄÄÄÄ
% DT, PERCENT OUTPUT DEADTIME
50 TA = 25°C 2.CT = 5.0 nF
R T, TIMING RESISTOR (k Ω)
ÄÄÄÄÄ
70 3.CT = 2.0 nF
4.CT = 1.0 nF 2
20 4
ÄÄÄÄÄ
5.CT = 500 pF
65 6.CT = 200 pF 1
ÄÄÄÄÄ
7.CT = 100 pF
8.0
5.0 60
7
2.0 55 5
NOTE: Output switches at
1/2 the oscillator frequency 6
0.8 50
10 k 20 k 50 k 100 k 200 k 500 k 1.0 M 10 k 20 k 50 k 100 k 200 k 500 k 1.0 M
fOSC, OSCILLATOR FREQUENCY (kHz) fOSC, OSCILLATOR FREQUENCY (kHz)
For R T u 5 Kf X 1.72
R TC T
Figure 2. Timing Resistor Figure 3. Output Deadtime
versus Oscillator Frequency versus Oscillator Frequency
VCC = 15 V VCC = 15 V
2.55 V AV = -1.0 AV = -1.0
3.0 V
TA = 25°C TA = 25°C
20 mV/DIV
200 mV/DIV
2.5 V 2.5 V
2.45 V 2.0 V
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UC3844B, UC3845B, UC2844B, UC2845B
-20 180 0
10 100 1.0 k 10 k 100 k 1.0 M 10 M 0 2.0 4.0 6.0 8.0
f, FREQUENCY (Hz) VO, ERROR AMP OUTPUT VOLTAGE (VO)
Figure 6. Error Amp Open Loop Gain and Figure 7. Current Sense Input Threshold
Phase versus Frequency versus Error Amp Output Voltage
ÄÄÄÄ
ISC , REFERENCE SHORT CIRCUIT CURRENT (mA)
Δ Vref , REFERENCE VOLTAGE CHANGE (mV)
0 110
ÄÄÄÄ
VCC = 15 V
VCC = 15 V
RL ≤ 0.1 W
-4.0
-8.0 90
-12 TA = -55°C
TA = 125°C
-16 70
-20
TA = 25°C
-24 50
0 20 40 60 80 100 120 -55 -25 0 25 50 75 100 125
Iref, REFERENCE SOURCE CURRENT (mA) TA, AMBIENT TEMPERATURE (°C)
VCC = 15 V VCC = 12 V to 25 V
IO = 1.0 mA to 20 mA TA = 25°C
TA = 25°C
O
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UC3844B, UC3845B, UC2844B, UC2845B
ÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ
0
Vsat , OUTPUT SATURATION VOLTAGE (V) Source Saturation
ÄÄÄÄÄÄÄÄÄÄÄÄÄ
VCC VCC = 15 V
VCC = 15 V
-1.0 (Load to Ground) 80 ms Pulsed Load
TA = 25°C CL = 1.0 nF
ÄÄÄÄ
120 Hz Rate 90
TA = 25°C
-2.0 %
ÄÄÄÄ
TA = -55°C
ÄÄÄÄ
ÄÄÄÄ ÄÄÄÄ
3.0
TA = -55°C
ÄÄÄÄÄÄÄÄÄ
2.0
TA = 25°C
ÄÄÄÄÄÄÄÄ
10
1.0 Sink Saturation %
(Load to VCC) GND
0
0 200 400 600 800 50 ns/DIV
IO, OUTPUT LOAD CURRENT (mA)
25
VCC = 30 V
20 V/DIV
TA = 25°C 20
15
ÄÄÄÄ
ÄÄÄÄ
ICC, SUPPLY CURRENT
10
RT = 10 k
UCX845B
UCX844B
ÄÄÄÄ
CT = 3.3 nF
100 mA/DIV
5 VFB = 0 V
ÄÄÄÄ
ISense = 0 V
TA = 25°C
0
0 10 20 30 40
100 ns/DIV VCC, SUPPLY VOLTAGE (V)
Figure 14. Output Cross Conduction Figure 15. Supply Current versus Supply Voltage
3 5 Current Sense A voltage proportional to inductor current is connected to this input. The PWM uses this
information to terminate the output switch conduction.
4 7 RT/CT The Oscillator frequency and maximum Output duty cycle are programmed by connecting resistor
RT to Vref and capacitor CT to ground. Oscillator operation to 1.0 kHz is possible.
5 GND This pin is the combined control circuitry and power ground.
6 10 Output This output directly drives the gate of a power MOSFET. Peak currents up to 1.0 A are sourced
and sunk by this pin. The output switches at one−half the oscillator frequency.
7 12 VCC This pin is the positive supply of the control IC.
8 14 Vref This is the reference output. It provides charging current for capacitor CT through resistor RT.
8 Power This pin is a separate power ground return that is connected back to the power source. It is used
Ground to reduce the effects of switching transient noise on the control circuitry.
11 VC The Output high state (VOH) is set by the voltage applied to this pin. With a separate power source
connection, it can reduce the effects of switching transient noise on the control circuitry.
9 GND This pin is the control circuitry ground return and is connected back to the powersource ground.
2,4,6,13 NC No connection. These pins are not internally connected.
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UC3844B, UC3845B, UC2844B, UC2845B
OPERATING DESCRIPTION
The UC3844B, UC3845B series are high performance, Comparator. This guarantees that no drive pulses appear at
fixed frequency, current mode controllers. They are the Output (Pin 6) when Pin 1 is at its lowest state (VOL).
specifically designed for Off−Line and DC−DC converter This occurs when the power supply is operating and the load
applications offering the designer a cost−effective solution is removed, or at the beginning of a soft−start interval
with minimal external components. A representative block (Figures 21, 22). The Error Amp minimum feedback
diagram is shown in Figure 16. resistance is limited by the amplifier’s source current
(0.5 mA) and the required output voltage (VOH) to reach the
Oscillator comparator’s 1.0 V clamp level:
The oscillator frequency is programmed by the values
3.0 (1.0 V) + 1.4 V
selected for the timing components RT and CT. Capacitor CT Rf(min) ≈ = 8800 W
0.5 mA
is charged from the 5.0 V reference through resistor RT to
approximately 2.8 V and discharged to 1.2 V by an internal Current Sense Comparator and PWM Latch
current sink. During the discharge of CT, the oscillator The UC3844B, UC3845B operate as a current mode
generates an internal blanking pulse that holds the center controller, whereby output switch conduction is initiated by
input of the NOR gate high. This causes the Output to be in the oscillator and terminated when the peak inductor current
a low state, thus producing a controlled amount of output reaches the threshold level established by the Error
deadtime. An internal flip−flop has been incorporated in the Amplifier Output/Compensation (Pin 1). Thus the error
UCX844/5B which blanks the output off every other clock signal controls the peak inductor current on a
cycle by holding one of the inputs of the NOR gate high. This cycle−by−cycle basis. The Current Sense Comparator PWM
in combination with the CT discharge period yields output Latch configuration used ensures that only a single pulse
deadtimes programmable from 50% to 70%. Figure 2 shows appears at the Output during any given oscillator cycle. The
RT versus Oscillator Frequency and Figure 3, Output inductor current is converted to a voltage by inserting the
Deadtime versus Frequency, both for given values of CT. ground−referenced sense resistor RS in series with the
Note that many values of RT and CT will give the same source of output switch Q1. This voltage is monitored by the
oscillator frequency but only one combination will yield a Current Sense Input (Pin 3) and compared to a level derived
specific output deadtime at a given frequency. The oscillator from the Error Amp Output. The peak inductor current under
thresholds are temperature compensated to within ±6% normal operating conditions is controlled by the voltage at
at 50 kHz. Also, because of industry trends moving the Pin 1 where:
UC384X into higher and higher frequency applications, the
V(Pin 1) − 1.4 V
UC384XB is guaranteed to within ±10% at 250 kHz. Ipk =
In many noise−sensitive applications it may be desirable 3 RS
to frequency−lock the converter to an external system clock. Abnormal operating conditions occur when the power
This can be accomplished by applying a clock signal to the supply output is overloaded or if output voltage sensing is
circuit shown in Figure 18. For reliable locking, the lost. Under these conditions, the Current Sense Comparator
free−running oscillator frequency should be set about 10% threshold will be internally clamped to 1.0 V. Therefore the
less than the clock frequency. A method for multi−unit maximum peak switch current is:
synchronization is shown in Figure 19. By tailoring the 1.0 V
clock waveform, accurate Output duty cycle clamping can Ipk(max) =
RS
be achieved to realize output deadtimes of greater than 70%.
When designing a high power switching regulator it
Error Amplifier becomes desirable to reduce the internal clamp voltage in order
A fully compensated Error Amplifier with access to the to keep the power dissipation of RS to a reasonable level. A
inverting input and output is provided. It features a typical simple method to adjust this voltage is shown in Figure 20. The
dc voltage gain of 90 dB, and a unity gain bandwidth of two external diodes are used to compensate the internal diodes,
1.0 MHz with 57 degrees of phase margin (Figure 6). The yielding a constant clamp voltage over temperature. Erratic
non−inverting input is internally biased at 2.5 V and is not operation due to noise pickup can result if there is an excessive
pinned out. The converter output voltage is typically divided reduction of the Ipk(max) clamp voltage.
down and monitored by the inverting input. The maximum A narrow spike on the leading edge of the current
input bias current is −2.0 mA which can cause an output waveform can usually be observed and may cause the power
voltage error that is equal to the product of the input bias supply to exhibit an instability when the output is lightly
current and the equivalent input divider source resistance. loaded. This spike is due to the power transformer
The Error Amp Output (Pin 1) is provided for external interwinding capacitance and output rectifier recovery time.
loop compensation (Figure 29). The output voltage is offset The addition of an RC filter on the Current Sense Input with
by two diode drops (≈1.4 V) and divided by three before it a time constant that approximates the spike duration will
connects to the inverting input of the Current Sense usually eliminate the instability (refer to Figure 24).
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UC3844B, UC3845B, UC2844B, UC2845B
VCC Vin
VCC 7(12)
36V
Vref Reference
Regulator
8(14) VCC + (See
R Text) VC
Internal UVLO -
RT 2.5V Bias
R 7(11)
+
3.6V Vref
-
UVLO Output Q1
Oscillator
CT 4(7) T 6(10)
+ 1.0mA
S
Power Ground
Voltage 2R Q
Feedback R PWM
5(8)
Input 2(3) R Latch
Error 1.0V Current Sense Input
Amplifier
Output/
Compensation 1(1) Current Sense 3(5)
Comparator RS
GND 5(9)
Pin numbers adjacent to terminals are for the 8-pin dual-in-line package. = Sink Only Positive True Logic
Pin numbers in parenthesis are for the D suffix SOIC-14 package.
Capacitor CT
Latch “Set"
Input
Output/
Compensation
Current Sense
Input
Latch “Reset"
Input
Output
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UC3844B, UC3845B, UC2844B, UC2845B
Vref
8(14) R 8(14) R
Bias RA Bias
RT
R 8 4 R
RB
5.0k
6 3
Osc Osc
CT 4(7) R 4(7)
+ 5 +
5.0k Q
0.01 7
2R 2 S 2R
5(9) 5(9)
To Additional
UCX84XBs
The diode clamp is required if the Sync amplitude is large enough to cause 1.44 RA
the bottom side of CT to go more than 300 mV below ground. f + D(max) +
(RA ) 2RB)C RA ) 2RB
Figure 18. External Clock Synchronization Figure 19. External Duty Cycle Clamp and
Multi−Unit Synchronization
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UC3844B, UC3845B, UC2844B, UC2845B
VCC Vin
7(12)
5.0V Ref
8(14) R
5.0V Ref
8(14) Bias
R +
Bias - R
+
R 7(11) -
+
- Osc
Q1 4(7)
Osc + T
4(7) T 6(10) S
+ VClamp 1.0mA
R2 S 2(3) Q
1.0 mA R
Q 2R
EA R
2R R 5(8) 1.0M
2(3) EA R
Comp/Latch 1.0V
1.0V
1(1)
3(5) RS C
1(1)
R1 5(9)
5(9) tSoft-Start ≈ 3600C in mF
1.67 ǒR1R)1R2R2Ǔ Where: 0 ≤ VClamp ≤ 1.0 V
VClamp ≈
ǒRR21 ) 1Ǔ + 0.33x10
-3
V
Ipk(max) [ Clamp
RS
Figure 20. Adjustable Reduction of Clamp Level Figure 21. Soft−Start Circuit
Figure 22. Adjustable Buffered Reduction of Figure 23. Current Sensing Power MOSFET
Clamp Level with Soft−Start
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UC3844B, UC3845B, UC2844B, UC2845B
VCC Vin
7(12)
5.0V Ref
+
-
7(11)
+ The addition of the RC filter will eliminate
-
Q1
instability caused by the leading edge spike
on the current waveform.
T 6(10)
S
5(8)
Q
R
Comp/Latch 3(5) R
C RS
VCC Vin
IB
7(12) + Vin
0
Base Charge
5.0V Ref
- Removal
+
-
C1
+ 7(11)
-
Rg Q1 Q1
6(10)
T 6(10)
S
Q 5(8)
R 5(8)
Comp/Latch
3(5) RS
3(5) RS
Series gate resistor Rg will damp any high frequency The totem pole output can furnish negative base current
parasitic oscillations caused by the MOSFET input for enhanced transistor turn-off, with the addition of
capacitance and any series wiring inductance in the capacitor C1.
gate-source circuit.
Figure 25. MOSFET Parasitic Oscillations Figure 26. Bipolar Transistor Drive
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UC3844B, UC3845B, UC2844B, UC2845B
VCC Vin
7(12)
Isolation
Boundary
5.0V Ref
+
- VGS Waveforms
+ 7(11) + +
Q1
- 0
0
- -
T 6(10) 50% DC 25% DC
ǒNNSpǓ
5(8)
Q V(Pin1) - 1.4
R Ipk =
3(5) R
3 RS
Comp/Latch
C RS NS
NP
8(14) R
Bias
R
Osc
4(7)
+
1.0 mA
2R
2(3) R
EA
1(1)
MCR 2N
101 3905 5(9)
2N
3903
The MCR101 SCR must be selected for a holding of < 0.5 mA @ TA(min). The
simple two transistor circuit can be used in place of the SCR as shown. All
resistors are 10 k.
1(1) 1(1)
Rf ≥ 8.8k 5(9) 5(9)
Error Amp compensation circuit for stabilizing any current mode topology except Error Amp compensation circuit for stabilizing current mode boost
for boost and flyback converters operating with continuous inductor current. and flyback topologies operating with continuous inductor current.
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UC3844B, UC3845B, UC2844B, UC2845B
L1
MBR1635
4.7W + T1 5.0V/4.0A
MDA 250 4.7k 3300 + +
2200 1000
202 pF
56k
115 Vac 5.0V RTN
MUR110
1N4935 1N4935 12V/0.3A
+ L2 +
7(12) + 68 + 1000 10
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UC3844B, UC3845B, UC2844B, UC2845B
The capacitor's equivalent series resistance must limit the Drive Output current to 1.0 A. An additional series resistor
may be required when using tantalum or other low ESR capacitors. The converter's output can provide excellent line
and load regulation by connecting the R2/R1 resistor divider as shown.
The capacitor's equivalent series resistance must limit the Drive Output current to 1.0 A.
An additional series resistor may be required when using tantalum or other low ESR capacitors.
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UC3844B, UC3845B, UC2844B, UC2845B
ORDERING INFORMATION
Device Operating Temperature Range Package Shipping†
UC384xBDG SOIC−14 55 Units/Rail
(Pb−Free)
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UC3844B, UC3845B, UC2844B, UC2845B
MARKING DIAGRAMS
PDIP−8
N SUFFIX
CASE 626
8 8 8
1 1 1
SOIC−14
D SUFFIX
CASE 751A
14 14 14
UC384xBDG UC384xBVDG UC284xBDG
AWLYWW AWLYWW AWLYWW
1 1 1
SOIC−8
D1 SUFFIX
CASE 751
8 8 8
384xB 384xB 284xB
ALYW ALYWV ALYW
G G G
1 1 1
x = 4 or 5
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G = Pb−Free Package
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UC3844B, UC3845B, UC2844B, UC2845B
PACKAGE DIMENSIONS
PDIP−8
N SUFFIX
CASE 626−05
ISSUE N
NOTES:
D A 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
E 2. CONTROLLING DIMENSION: INCHES.
H 3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACK-
AGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3.
8 5
4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH
OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE
E1 NOT TO EXCEED 0.10 INCH.
5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM
PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR
1 4
TO DATUM C.
6. DIMENSION E3 IS MEASURED AT THE LEAD TIPS WITH THE
NOTE 8 LEADS UNCONSTRAINED.
c 7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE
b2 B END VIEW LEADS, WHERE THE LEADS EXIT THE BODY.
TOP VIEW WITH LEADS CONSTRAINED 8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE
CORNERS).
NOTE 5
INCHES MILLIMETERS
A2 DIM MIN MAX MIN MAX
e/2 A −−−− 0.210 −−− 5.33
A NOTE 3 A1 0.015 −−−− 0.38 −−−
A2 0.115 0.195 2.92 4.95
L b 0.014 0.022 0.35 0.56
b2 0.060 TYP 1.52 TYP
C 0.008 0.014 0.20 0.36
D 0.355 0.400 9.02 10.16
SEATING
PLANE D1 0.005 −−−− 0.13 −−−
A1 E 0.300 0.325 7.62 8.26
C M E1 0.240 0.280 6.10 7.11
D1 e 0.100 BSC 2.54 BSC
eB −−−− 0.430 −−− 10.92
e eB L 0.115 0.150 2.92 3.81
8X b END VIEW M −−−− 10 ° −−− 10 °
0.010 M C A M B M NOTE 6
SIDE VIEW
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17
UC3844B, UC3845B, UC2844B, UC2845B
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
NOTES:
1. DIMENSIONING AND TOLERANCING PER
−X− ANSI Y14.5M, 1982.
A 2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
8 5 PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
B S 0.25 (0.010) M Y M PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
1 IN EXCESS OF THE D DIMENSION AT
4 MAXIMUM MATERIAL CONDITION.
−Y− K 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
G MILLIMETERS INCHES
DIM MIN MAX MIN MAX
C N X 45 _ A 4.80 5.00 0.189 0.197
B 3.80 4.00 0.150 0.157
SEATING
PLANE C 1.35 1.75 0.053 0.069
−Z− D 0.33 0.51 0.013 0.020
G 1.27 BSC 0.050 BSC
0.10 (0.004) H 0.10 0.25 0.004 0.010
H M J J 0.19 0.25 0.007 0.010
D K 0.40 1.27 0.016 0.050
M 0_ 8_ 0 _ 8 _
N 0.25 0.50 0.010 0.020
0.25 (0.010) M Z Y S X S
S 5.80 6.20 0.228 0.244
SOLDERING FOOTPRINT*
1.52
0.060
7.0 4.0
0.275 0.155
0.6 1.270
0.024 0.050
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18
UC3844B, UC3845B, UC2844B, UC2845B
PACKAGE DIMENSIONS
SOIC−14
CASE 751A−03
ISSUE H
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
−A− 2. CONTROLLING DIMENSION: MILLIMETER.
14 8 3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
−B− 5. DIMENSION D DOES NOT INCLUDE
P 7 PL DAMBAR PROTRUSION. ALLOWABLE
0.25 (0.010) M B M DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
1 7 CONDITION.
G MILLIMETERS INCHES
R X 45 _ F DIM MIN MAX MIN MAX
C A 8.55 8.75 0.337 0.344
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
−T− F 0.40 1.25 0.016 0.049
K M J
SEATING D 14 PL G 1.27 BSC 0.050 BSC
PLANE J 0.19 0.25 0.008 0.009
0.25 (0.010) M T B S A S K 0.10 0.25 0.004 0.009
M 0_ 7_ 0_ 7_
P 5.80 6.20 0.228 0.244
R 0.25 0.50 0.010 0.019
SOLDERING FOOTPRINT
7X
7.04 14X
1.52
1
14X
0.58
1.27
PITCH
DIMENSIONS: MILLIMETERS
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