Secondary Side Synchronous Rectification Control

Implementation and SR Features for Flyback

Tomáš Tichý
What Is Synchronous Rectification For?

Synchronous Rectification
• Replaces diode rectifier by
transistor and emulates diode
operation
• Reduces voltage drop across
rectifier that reduce conduction loss
• Has higher effect for lower VOUT and
higher IOUT applications

2
Sensing Principle
VRDSON + VL_DRAIN + VL_SOURCE

VL_DRAIN VRDSON VL_SOURCE

ISD

• SR controller measures voltage across SR

MOSFET.
• Measured voltage consists of drop at RDSON and
drop at parasitic inductance of MOSFET
package
• Noise at current may shift voltage drop to
positive values and may cause incorrect turn-
off. MIN_TON feature should be used to blank
noisy time at the begin of conduction phase.

3
System with low and high parasitic inductance
Correct turn-off Premature turn-off
VDS VDS

DRV DRV

SR conducts ISECONDARY SR conducts Body diode conducts

ISECONDARY Body diode conducts

• System with low parasitic inductance turns-off properly (body diode conducts just short
time at the end of conduction phase, where current is low).
• System with high parasitic turns-off too early, rest of period is conducted via body diode
with higher power loss
4
Ringing after demagnetization phase

Voltage oscillations at SR
transistor appears after
demagnetization phase where
no current flows through
secondary side. Ringing can be
too deep that it triggers VCS_ON
threshold. It is wanted not to
turn SR on in valleys, because
there is just lack of energy.
Primary switch can be also
turned on anytime and cross
conduction is unwanted.
Minimum off time feature is
involved to avoid turn on.

5
 Minimum on-time

Methods how to avoid premature SR turn-off

6
Goals

• Avoid prematurely turn off during current oscillation phase

• Avoid reverse current condition
• Avoid cross-conduction condition

7
Too short minimum on-time

tMIN_TON is set to ~560 ns.

SR VDS
Driver is turned-off
incorrectly at high
negative dI/dt.

ISD
VOUT

SR DRV

8
Too long minimum on-time

tMIN_TON is set to ~2.4 µs.

Driver is still on even
when current goes
negative. This means that
current starts to flow from
output capacitor back to
SR VDS transformer. Spare energy
VOUT stored in transformer
causes deeper ringing
ISD
and power loss
SR DRV

9
 Fixed on-time interval

• Minimum on time interval is

VDS started at transistor turn-on event.
ISEC
• Time interval is fixed for all
conditions
VDS_OFF • SR transistor can‘t be turned off
VDS_ON
during minimum on time
• Minimum on time interval has to
DRV be set longer than ringing takes,
Turn-on delay Turn-off delay
but shorter than the shortest
conduction length

Min ON-time
tMIN_TON

10
 Fixed time interval – short conduction
VDS
ISD
Very short conduction interval
(shorter than minimum on-time)
VDS_OFF cause reverse current condition.
VDS_ON Minimum on-time doesn‘t allow to
Negative current flows from COUT to transformer
turn SR transistor off even when
DRV It causes deeper ringing and lower efficiency
current reaches zero. Energy starts
Turn-on delay to flow back from output capacitor
to transformer. When SR gets off,
tMIN_TON elapsed, driver may be turned-off there is lot of energy in transformer
Min ON-time
tMIN_TON that causes high amplitude ringing.
Ringing may trigger SR again and
OFF comparator OFF-cmp blanked for tMIN_TON secondary side energy oscillation
begins
tMIN_TON elapsed, CMP still high -> turn driver off

11
Fixed time interval – sudden primary turn on

VDS
ISD There is risk of deep cross-
conduction if primary side switch
VDS_OFF turns on during minimum on-time.
VDS_ON Cross-conduction condition lasts
until minimum on-time ends or
DRV
until primary side short circuit
Turn-on delay
detection is triggered.
Switches at both sides are
Min ON-time tMIN_TON elapsed, driver may be turned-off
tMIN_TON stressed with high currents and
high voltage overshoots.
OFF-cmp blanked for tMIN_TON Blanking ends, OFF-cmp is high -> turn driver off
OFF comparator

12
 Breakable minimum on time interval
VDS
ISD Off comparator is not fully
disabled during minimum on-time
VDS_OFF interval. Comparator is blanked by
VDS_ON short blanking interval during
DRV
minimum on-time that secures no
Turn-on delay Turn-off delay
reaction for current ringing, but
catches reverse or cross-
Min ON-time
conduction condition.
tMIN_TON

OFF-cmp blanked for limited time during t MIN_TON

OFF cmp
No blanking after tMIN_TON

Fixed blanking

13
Breakable time interval – short conduction

Short condition can be easily

detected and SR is properly
turned off sooner than current
crosses zero.

14
Breakable time interval – sudden primary turn on

Cross-conditions is detected very

soon and SR transistor is turned
off before cross-conduction
current gets too high.

15
 Prolong-able breakable minimum on time interval

VDS
ISD Minimum on-time interval could be
improved for prolong-able feature.
VDS_OFF Base minimum on-time is starter at
VDS_ON the begin of conduction phase. If
DRV
OFF comparator is triggered during
Turn-on delay Turn-off delay
base on-time, timer is reset to
extension minimum on-time and
tON_MIN
started immediately when OFF
Min ON-time tON_MIN_BASE

comparator goes back. This could

MIN_TON extension
tON_MIN_EXT added
1. 2. 3. 4. when OFF-cmp
goes low
OFF-cmp blanked for limited time (tOFF_BLK) during tON_MIN
help to set as short minimum on-
OFF cmp No blanking after tMIN_TON time as possible, but have it long
Initial blanking
tON_INIT_BLK enough in case of need.
t

16
Prolong-able breakable minimum on time interval

Transistor current
Computed drop at transistor
with 2nH + 5 mOhm
Minimum on-time
modulation in real
application. Modulation
helps with keeping
minimum on-time as
short as possible, but it
can be significantly
prolonged in case of
necessity

17
 Minimum off-time

Methods how to avoid premature SR turn-on

18
Goals

• Avoid prematurely turn on during voltage oscillations after demagnetization

phase
• Avoid reverse current condition
• Avoid cross-conduction condition
• Blank ringing valleys that can trigger on comparator

19
Fixed minimum off-time interval

Simple solution is to start fixed off

time interval with SR transistor
turn-off and lasts constant time.
Disadvantage of this simple
solution is that it is not good
enough. Off timer can be started
sooner that end of conduction
phase so off time is then not long
enough and SR transistor can be
turned on by ringing valley.

20
Fixed minimum off-time interval triggered by end of conduction phase

Logic improvement is to start

minimum off-time from end of
conduction phase not by SR
transistor turn-off.
This achieves proper usage of off-
time interval.
There is still disadvantage that
minimum off-time interval has to
be set to very long time to cover
the worst case scenario

21
Too short minimum off-time interval

tMIN_TOFF is set to ~1.2 µs.

Driver is incorrectly
activated during ringing
SR VDS phase that leads to moving
energy back and forth from
transformer to COUT.
ISD Decreases efficiency, may
VOUT lead to cross current
condition with primary side.
SR DRV
Situation is worst with
longer MIN_TON.

22
Too short minimum off-time interval

tMIN_TOFF is set to ~1.2 µs.

Driver is incorrectly activated
during ringing phase and is
SR VDS Shot through
kept on in time when primary
SR MOSFET is
turned-on
current starts to
flow
side turns-on. Cross current
condition occurs. Over current
ISD
protection at primary side
Primary side
MOSFET is turned turns primary driver off.
SR DRV off by over current
Primary side protection
MOSFET is getting on
Prim gate

23
Too long minimum off-time interval

tMIN_TOFF is set to ~6.7 µs.

SR VDS
Driver may be not activated for
ISD some or all pulses. Here is
shown border condition where
some pulses are missing.
Intervals of VDS above VDS_RESET
are 6.8 ms, 6.3 µs and 6.8 µs.
SR DRV

Primary gate

24
Resettable minimum off-time interval

Resettable minimum off-time interval

helps with timer setting. This allows to
set minimum off-time interval just
slightly longer than ringing period.
Minimum off-time can be reset each
time when SR transistor voltage drops
below VDS_RESET threshold. Off-timer can
start again when SR transistor voltage
gets above reset threshold. Next SR
controller operation is possible just if
minimum off-time timer elapsed
completely.
This significantly simplifies minimum off-
time setting and reduces risk of not
enough timer length.
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Minimum off-time issue with wide range applications

Wide range output voltage

applications (USBP-PD, QR3.0 …)
brings new challenge for minimum
off-time. Hard time comes when
SMPS operates with high input
voltage and low output voltage. This
causes long secondary side
demagnetization phase, short
ringing and short primary
conduction phase. Minimum off-
time interval is not able to elapse
before next conduction cycle that
doesn‘t allow SR transistor turn-on.

26
Minimum off-time shortening with wide range applications

Minimum off-time has to be

shortened in these cases. Drain to
source voltage has very high
negative dV/dt before begin of
secondary side conduction phase in
compare to dV/dt of voltage ringing.
High –dV/dt can be easily detected
and minimum off-time can be
shortened based on it. Elapsed
minimum off-time interval enables
SR transistor turn-on.

27
Operation without off-time shortening

SR VDS Problematic condition may occur

also during DCM. Here are some
MIN_TOFF SR DRV MIN_TOFF pulses skipped because
doesn’t elapses
before CS goes
low, NO DRV
doesn’t elapses
before CS goes MIN_TOFF doesn‘t elapse before
PULSE GOES
OUT
low, NO DRV
PULSE GOES conduction phase starts
OUT

ISD
VIN = 230V, VOUT = 5V, IOUT = 2.4A

tMIN_TOFF tMIN_TOFF tMIN_TOFF tMIN_TOFF tMIN_TOFF

MIN_TOFF reset because

VCS < VTH_CS_RESET

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Operation with off-time shortening

Each pulse Off-time shortening solves

SR VDS dV/dt is in
missing pulse issue
duty
SR DRV VIN = 230V, VOUT = 5V, IOUT = 2.4A

ISD

tMIN_TOFF tMIN_TOFF tMIN_TOFF tMIN_TOFF tMIN_TOFF tMIN_TOFF

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 Continuous conduction mode operation

SR operation during continuous conduction mode

30
Challenges

• SR controller has to detect end of conduction phase and turn SR transistor off
sooner than secondary side current reaches zero
• Smooth transition between DCM and CCM modes
• No external synchronization with primary side is usually acceptable

31
Implementation in CCM application

32
Sensing during CCM
Figures show timing of
ZOOM turn-off process during
CCM operation.
Voltage drop at
ISD
ISD parasitic inductance
(green) goes
significantly positive
during end of
VL_SOURCE + VL_DRAIN conduction phase and
VL_SOURCE + VL_DRAIN
VDS = VRDSON + VL_SOURCE + VL_DRAIN triggers turn-off
VRDSON
comparator shortly
VDS = VRDSON + VL_SOURCE + VL_DRAIN
VCS_OFF tCS_OFF_PD tF VCS_OFF after dI/dt changes so
VRDSON
DRV SR transistor is
SR controller has
DRV
turned off
enough time to turn off
MIN_TON
correctly

33
CCM operation waveforms - comparison
1 – SR VDS
2 – SR VGS
3 – Prim VGS
FDMS86181 4 – Isec
SR activated
Bodydiode (SR disabled)
Proof of correct operation is
waveforms comparison with
disabled SR (body diode
operation) and enabled SR. If
difference is very small or
negligible, it works well.
Picture is done by
interleaving previous pictures

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CCM operation waveforms
1 – SR VDS
2 – SR VGS
3 – Prim VGS
Computed (and interlaced) voltage
4 – Isec
VCS_OFF cross
drop at SR transistor with
RDSon=3.8mOhm and package C3 – Primary VDS
inductance 1nH
M4 – SR VDS computed based on
SR transistor is
current
turned-off
tCS_OFF_PD tf
SR DRV 4V/div

ISEC 4A/div This picture shows waveforms from

primary and secondary side. There
is also added computed waveform
Primary driver
Primary switch
turn-on process
Primary VGS 4V/div M4 that shows voltage across SR
turns-on
transistor in case it is turned on. It is
SR VDS 10V/div Primary VDS 50V/div
Primary switch
turn-on process is
computed from secondary side
almost done
current level and dI/dt with RDSon
(3.8mOhm) and transistor package
inductance (1nH)

35
 Thank you for your attention

More information at www.onsemi.com

36
 Backup

Supply, Schematics and Various Implementations, Layout, …

37
Controller Supply

Controller can be supplied from three different current source. User may decide
condition where each of these source will be used. This allows to optimize
efficiency and schematic according to specific needs.
Supply sources
- VCCL – main supply pin – internal blocks are supplied by VCCL voltage
- VCCH – second supply pin, provides supply for internal current source that
goes to VCCL pin if its voltage is low
- CS – third supply pin, provides supply for internal current source that goes to
VCCL pin if its voltage is low and current from VCCH doesn‘t flow (CS current
source has the lowest priority)

- VCCH and CS current sources are not activated until VCCL pin voltage drops
below VCCL_SB_A threshold

38
 Supply Priorities
VCCL_D
VCCL _ D Voltage in front of To ext. source
VCCL diode
ICCL
VCCL

To ext. source Supply DRV

Driver
VCCL VCCL_SB_D VCCH ICCH block
Supply
VCCL_SB_A control block

To SR tran. drain ICS

VCCH CS Self supply
ICCH block

Supply sources priorities:

CS 1. VCCL
ICS
2. VCCH (max 25mA)
3. CS (max 120mA)
Figure shows priority of each power source. The highest priority has VCCL pin, when there is high
enough voltage VCCL is only used. When voltage is not enough VCCH is checked and if it is able to
supply enough current it is used as power source to recharge VCCL voltage. The lowest priority has
CS pin that is used if both pins has low voltage. VCCL_SB_A level can be set to 4.7 V and 9 V.

39
CS Supply Current Source - Self Supply
VDS = VCS

VCCL_SB_D
VCCL
VCCL_SB_A
CS current is activated also at be gin of p rimary
on time even when there is enoug h voltage to
minimize voltage ove rshoo t

CS current is reduce d to avoid VCCL sh ort difficuilties

ICS

CS supply source (aka self-supply) operation is shown above. It shows situation

when there is no other power source just CS pin. CS current source has limited
current for low VCCL levels to avoid overpower issue in case of short at VCCL pin. CS
current flows to VCCL pin when CS has high enough voltage and VCCL drops below
VCCL_SB_A threshold. There is also short current peak from CS pin even when VCCL is
high enough each CS pin rising edge. This helps user to fight with SR transistor VDS
overshoot little bit

40
Flyback (DCM, CCM) schematics Full supply options
(VOUT, AUX, self supply)
VOUT and self supply

Full supply options II Just self-supply

(VOUT, AUX, self supply)

41
Flyback (DCM, CCM) high side schematics

AUX supply Full supply options

(AUX, AUX2, self supply)

Just self-supply

42
Layout

Proper layout is essential for correct operation

- GND and CS connections to SR transistor have to be done by
Kelvin connection to minimize parasitic in sensing loop
- Decoupling capacitor between VCCL and GND has to be connected
as close as possible with wide enough traces
- SR GND should be connected to system just through GND to SR
transistor source trace – no other connection to GND is allowed!
- DRV and GND connections to SR transistor should be wide
enough, short with narrow loop to allow flowing high driving
currents

43
Layout example NCP4307

GND is connected just

at one point via wide
and short Kelvin
connection as close as
possible to Source

Snubber
If VCCH is not needed,
connect it to VCCL pin (C2 is
not needed)

VCCL is divided from system

voltage by schottky diode to
allow charge VCCL (C1)
capacitor higher that system Decoupling
voltage is. Short and wide
capacitor as close
trace from DRV to Drain sense to the
as possible to IC quitest point
gate

44
 Active clamp flyback

Solution for proper operation with active clamp flyback

45
Schematic

ACF is basically standard

flyback that replaces
diode in clamp circuit
with switch.
If switch in clamp is used
(controlled) application
works in active clamp
mode, if it is kept off,
application works like
standard DCM/CCM
flyback.

46
Goals

• Critical operation point is transient between DCM and ACM mode

• Avoid cross conduction during transition between DCM and ACM
• Keep SR operating as much as possible

47
Transient from DCM to ACM
Clamp switch starts to
operate during transition
Prim low switch
between DCM and ACM.
Prim clamp switch
Clamp switch
ISEC
conduction time
increases gradually.
Clamp transistor on-time
SR VDS
causes secondary side
conduction.

48
Transient from DCM to ACM
Low side
tOFF_MIN has to be set Clamp transistor transistor is
to longer time than
length of ringing
period tOFF_MIN
is turned on turned on
Clamp switch starts to
VDS
ISD operate during transition
VDS_RESET
between DCM and ACM.
Clamp switch conduction
VDS_OFF
DS voltage drops below
VDS_ON VCS_ON but at time when

VDRV
tOFF_MIN doesn’t elapse and
just low -dV/dt is detected
so DRV is not activated Primary and
time increases gradually.
Turn-on delay Turn-off delay
secondary side
cross conduction
Turn-on delay Clamp transistor on-time
causes secondary side
Min ON-time
tMIN_ON
tMIN_ON
tOFF_BLK elapses
driver goes off
conduction.
tOFF_BLK

Min OFF-time
tOFF_MIN timer is
tOFF_MIN tOFF_MIN stopped here because
of VDS<VDS_RESET

Negative dV/dt tOFF_MIN timer doesn’t

detector at DS elapse but high -dV/dt
is detected so DRV
can be turend-on

t
49
Transient from DCM to ACM
Situation with standard
SR controller. There is
deep reverse current
Prim low switch
when primary clamp
VDS switch turns off even with
breakable minimum on-
time. Breakable minimum
on-time There would be
ISR not just reverse current
but also primary to
SR DRV secondary shoot through
Prim low switch without breakable
OFF cmp blank tMIN_ON_BASE
minimum on-time.

50
 Solution
High dV/dt
unblocks driver
Low dV/dt

VDS = VCS
Monitor voltage across SR
MOSFET. This voltage has very
VCS_RESET
high +dV/dt at begin of primary
VCS_OFF
low side switch conduction time.
VCS_ON
This could be monitored so SR
controller knows when it should
or should not activate driver.
+dV/dt before primary high side
VDRV
switch turn-on is low, driver is
unblocked
Driver

Driver blocked Driver unblocked

kept blocked until high +dV/dt is
detected.
Positive dV/dt
detector

51
Transient from DCM to ACM with tOFF_MIN has to be set
to longer time than
Clamp transistor
is turned on

+dV/dt and fully blocked driver VDS

length of ringing
period tOFF_MIN

ISD

SR driver is blocked until

VDS_RESET

VDS_OFF

+dV/dt at DS voltage is VDS_ON

DS voltage drops below
VDS_ON but at time when

detected. This eliminates driver

tOFF_MIN doesn’t elapse and
just low -dV/dt is detected
so DRV is not activated
VDRV

activation when primary clamp Turn-on delay Turn-off delay Turn-on delay

switch is turned on. No positive dV/dt was

detected after last driver
Min ON-time turn-off event -> driver tOFF_MIN timer is
tMIN_ON can’t be turned on stopped here because
of VDS<VDS_RESET

Min OFF-time
tOFF_MIN tOFF_MIN

Negative dV/dt tOFF_MIN timer doesn’t

detector at DS elapse but high -dV/dt
is detected so off
timer is done

Positive dV/dt
detector at DS Positive dV/dt detected,
tOFF_MIN done, driver
can be activated when
VDS goes below VDS_ON

t
52
+dV/dt detector schematic

+dV/dt is detected via

external RC network (R3,
R4, C6 and D5) that is
connected to TRIG/DIS
pin with modified
function. +dV/dt is
detected when TRIG/DIS
pin voltage exceeds ~2V.
External circuit allows
easy setup for given
application.

53
Transient from DCM to ACM with fully blocked driver

Practical result when

High dV/dt detected
NCP4307 is used in
DRV
ACF application
during transient from
DCM to ACF
TRIG/DIS operation
Driver blocked Driver blocked

ISR

CS = VDS

Primary high side on-time

54
Transient from DCM to ACM with tOFF_MIN has to be set
Clamp transistor
is turned on

+dV/dt and reduced min on-time

to longer time than
length of ringing
period tOFF_MIN
VDS
ISD

SR driver is not fully disabled VDS_RESET

VDS_OFF

when +dV/dt is not detected, but VDS_ON

DS voltage drops below
VDS_ON but at time when

SR switch is activated with VDRV

tOFF_MIN doesn’t elapse and
just low -dV/dt is detected
so DRV is not activated

significantly reduced minimum Turn-on delay Turn-off delay

Turn-on delay
Turn-off delay
Turn-on delay

on-time to be able turn-off as No positive dV/dt was

detected after last driver

soon as is needed. Minimum on- Min ON-time

tON_MIN_BASE
tON_INIT_BLK
turn-off event -> driver can
be turned on just with
tON_MIN_INIT minimum on tON_INIT_BLK

time is reduced to just initial

time interval

Min OFF-time
blanking time (mainly to blank tOFF_MIN tOFF_MIN

turn-on process). Negative dV/dt tOFF_MIN timer is tOFF_MIN timer doesn’t

detector at DS stopped here because elapse but high -dV/dt
of VDS<VDS_RESET is detected so off
timer is done

Positive dV/dt
detector at DS Positive dV/dt detected,
tOFF_MIN done, driver
can be activated when
VDS goes below VDS_ON

55
Operation with low +dV/dt in ACM
+dV/dt can be very small
at specific condition
during ACM operation.
Fully blocked driver will
SR DRV
cause difficulties here (no
SR operation), but
ISR operation is correct with
short minimum on-time.
+dV/dt
Longer minimum on-time
is not needed, because
SR VDS
there is no noise

56
Transient from DCM to ACM with +dV/dt and reduced min on-time

Reduced minimum on-

ISR Full tON_MIN Reduced tON_MIN time option allows to use
full minimum on-time
SR DRV when needed and
minimize it when soon
reverse condition may
+dV/dt happen. No reverse
current or shoot through
SR VDS current happen.

57
 Light load mode

Detect light load operation and decrease current consumption

58
Goals

• Detect primary side light load operation

• Decrease quiescent current as much as possible during light load
• Use SR transistor for as many pulses as possible

59
LLD based on time without conduction
VDS
VDS

VDS_LLD
VDS_LLD VDS_ON
tLLD_EXIT_BLK tLLD_EXIT_BLK
tLLD tLLD_EXIT_BLK tLLD DRV tLLD_EXIT_BLK
tLLD_EXIT_BLK tLLD_EXIT_BLK
DRV tLLD_EXIT_BLK
tLLD_REC
tLLD_EXIT_BLK
tLLD_REC ON cmp
ON cmp blanking

Light Load Light load ON cmp high after

blanking ->DRV activated

ICC ICCL_Q ICCL_LL ICC ON cmp goes low during

blanking -> no action

0 1 2 3 9 10 11 35 7 9
4 6 8

SR controller monitors SR transistor drain source voltage. Negative VDS voltage

means conduction cycle. When there is no conduction (positive voltage) for more
than set time it means light load condition and SR controller can enter disable mode.
SR controller transfers to normal mode immediately when VDS voltage
drops below zero.

60
LLD behavior in real application
1 – VDS
2 – DRV Light load mode is not activated
before 2nd pulse thats why
CS is below VCS_ON shorther
than tLLD_EXIT_BLK so driver is not
3 – VOUT driver is activated within
propagation delay when CS is
below VCS_ON
turned on
4 – ISD

1st pulse in skip

CS is below VCS_ON longer than
burst when light
tLLD_EXIT_BLK tLLD_EXIT_BLK tLLD_EXIT_BLK so driver is turned load was
on
activated before
30 ns
60 ns 200 ns

2nd pulse in skip

burst

Both figures show behavior of LLD function in real application. Left figure shows behavior at
first pulse of pulse burst when light load mode was activated before. It can be seen that driver
is activated in same pulse, just DS voltage has to stay below VDS_ON threshold for more than
tLLD_EXIT_BLK time. 2nd pulse operates normally, driver is activated within tDS_ON_PD.
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 Thank you for your attention

More information at www.onsemi.com

62