MIPS Processor R3000: Registers

MIPS Processor R3000
 RISC Type: Fixed Length: All MIPs instructions fit in a

single 32-bit word. Registers
 The MIPS architecture is modern and well-designed. MIPS
chips were designed from the ground up in 1985
R0 - R31
 Instruction Categories
 Load/Store
 Computational
 Jump and Branch
 Floating Point (coprocessor) PC
 Memory Management HI
 MIPS has 32 registers LO
 Zero Register $0
 Always has the value 0; cannot be changed!
 Cannot Change his value, H/W wont allow it!
 Has many uses.
 The size of a register in the MIPS architecture is 32 bits;

Computer Architecture 1 3/27/2016
MIPS Instruction Set
3
 Instructions execute simple functions.

 Maintain regularity of format – each instruction is one
word, contains opcode and arguments.
 Minimize memory accesses – whenever possible use
registers as arguments.
 Uses the three registers instruction formats among others.
 Example
Add $s1, $s2, $s3 # $s1= $s2 + $s3
 The above add instruction operates on three operands, two input
data operands $s2 and $s3 (registers), and the result is written into
an output operand $s1 (register).

MIPS Processor R3000
4
 RISC Type: Processor word is 32 bits long

 Fixed Length: All MIPs instructions fit in a Registers
single 32-bit word.
 The MIPS architecture is modern and well-
designed. R0 - R31
 Instruction Categories
 Load/Store
 Computational
 Jump and Branch PC
 Floating Point (coprocessor)
 Memory Management HI
 MIPS has 32 registers LO
 Zero Register $0
 Always has the value 0; cannot be changed!
 Cannot Change his value, H/W wont allow it!
 Has many uses.
 Each register contains 32 bits.
5
 Instructions execute simple functions.

 Maintain regularity of format – each instruction is one
word, contains opcode and arguments.
 Minimize memory accesses – whenever possible use
registers as arguments.
 Example:
 Three register instruction formats:
Add $s1, $s2, $s3 # $s1= $s2 + $s3

6
 Three types of instructions:

1. Register (R) - type – Only registers as arguments.
2. Immediate (I) - type – Arguments are registers and numbers
(constants or memory addresses).
3. Jump (J) - type – Argument is an address.
 Every instruction includes various ―fields‖ that encode
combinations of:
 A 6-bit operation or “OPCODE”,
 Specifying one of < 64 basic operations
 Escape codes to enable extended functions.
 Several 5-bit OPERAND fields, for specifying the sources and
destination of the operation, usually one of the 32 registers.
 Embedded constants (“immediate” values) of various sizes, 16-
bits, 5-bits, and 26-bits. Sometimes treated as signed values,
sometimes not.

7
 R-type: 3 register operands (2 sources, 1 destination).

 I-type: 2 register operands, 16-bit immediate constant
 J-type: no register operands, 26-bit immediate

MIPS Machine Execution
8
 Generally…
 Instructions execute after all previous instructions have
completed, therefore their results are available to the next
instruction.
 But, you may see exceptions to these rules.
 Example:
Instructions Variables
add $s0, $s1, $s1 $s0: 0, 12, 24, ?
add $s0, $s0, $s0 $s1: 6, ?
add $s0, $s0, $s0 $s2: 8
sub $s1, $s0, $s1 $s3: 10

MIPS Memory Organization
9
 Since 8-bit bytes are useful in many programs, virtually

all architectures today address individual bytes.
 "Byte Addressing" means that the index points to a byte
of memory.
o Since in MIPS the Word is 4 Bytes;
so the Byte Addressing of the
memory has a multiply by four.
o The address is the address of the
first byte of it.

MIPS Memory Organization
10
 Alignment Restriction: In MIPS Words must start at addresses that

are multiply of 4.
 Alignment Restriction: A requirement that data be aligned in memory on
natural boundaries.
 MIPS processors can operate with either big-endian or little-endian byte order.
 232 bytes with addresses from 0 to 232 – 1
 230 words with addresses 0, 4, 8, ... 232 – 4
Word Addresses
. 32 bits of data
12 32 bits of data
8 32 bits of data
4 32 bits of data
0 32 bits of data
MIPS Register Convention
11
Name Register number Usage

$zero 0 the constant value 0
$at 1 reserved for use by assembler
$v0-$v1 2-3 values for results and expression evaluation
$a0-$a3 4-7 arguments
$t0-$t7 8-15 temporaries
$s0-$s7 16-23 saved
$t8-$t9 24-25 more temporaries
$gp 28 global pointer
$sp 29 stack pointer
$fp 30 frame pointer
$ra 31 return address
Register 1 ($at) reserved for assembler, 26-27 (K0-K1) for operating system
MIPS Arithmetic Operations
12
 Instructions, like registers and words of data, are also 32

bits long:
 Example: add rd, rs, rt
 add $t1, $s1, $s2
 Registers have numbers, $t1=9, $s1=17, $s2=18
 R-Type: Register Instruction Format:
000000 10001 10010 01001 00000 100000
op rs rt rd shamt funct

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 op: Basic operation of the instruction, traditionally called

the opcode.
 rs: The first register source operand.
 rt: The second register source operand.
 rd: The register destination operand. It gets the result
of the operation.
 shamt: Shift amount. Used in shift instructions; it will
not be used until then, and hence the field contains zero
in this section.)
 funct: Function. This field, often called the function
code, selects the specific variant of the operation in the op
field.
14
 All instructions have 3 operands

 Operand order is fixed (destination first)
Example 1:
C code: a = b + c;
MIPS code: add a, b, c
Example 2:
C code: a = b + c + d;
MIPS code: add a, b, c
add a, a, d
Signed and Unsigned Numbers
15
 Number representations in binary

 (z31 x 231)+(z30 x 230)+(z29 x 229) … (z1 x 21) (z0 x 20)
 1011two = (1 x 23) + (0 x 22) + (1 x 21) + (1 x 20)ten
= (1 x 8) + (0 x 4) + (1 x 2) + (1 x 1)ten = 8 + 0 + 2 + 1ten = 11ten
 And the numbering of bits within a MIPS word and the placement of
the number 1011ten:
 Least Significant Bit (LSB): rightmost bit in a MIPS word.

 Most Significant Bit (MSB): left most bit in a MIPS word.

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 Positive & Negative Representation

 Sign and Magnitude Representation: is by adding
a separate sign, which conveniently can be represented in
a single bit.
+ 7ten = 0 111two
- 7ten = 1 111two
 Several shortcomings
 Where to put the sign bit?
 A separate sign bit means that sign and magnitude

has both a positive and a negative zero.
+ 0ten = 0 oootwo
- 0ten = 1 000two
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 One’s Complement: Represents the most negative value by 10 .

. . 000 and the most positive value by 01 . . . 11 , leaving an
two two
equal number of negatives and positives but ending up with

two zeros, one positive (00 . . . 00 ) and one negative (11 . . .
two
11 ).
two
+ 7ten = 0 111two
- 7ten = 1 000two
 Solution? Pick the representation that made the

hardware simple:
 leading 0s mean positive, and leading 1s mean
negative.
 It is called Two’s Complement Representation

Two’s Complement Representation
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 Has the advantage that all negative numbers have a 1

in the most significant bit.
 Hardware needs to test only this bit to see if a number is
positive or negative (with the number 0 considered
positive). This bit is often called the sign bit.
 By recognizing the role of the sign bit, we can represent
positive and negative 32-bit numbers
 (z31 x - 231)+(z30 x 230)+(z29 x 229) … (z1 x 21)+(z0 x 20)
 Example: converse to decimal:
 1111 1111 1111 1111 1111 1111 1111 1100two

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 Signed versus unsigned applies to loads as well as to arithmetic.

 The function of a signed load is to copy the sign repeatedly to fill the
rest of the register — called sign extension—but its purpose is to
place a correct representation of the number within that register.
 MIPS does offer two flavors of byte loads: load byte (lb) treats the
byte as a signed number and thus sign-extends to fill the 24 left-
most bits of the register, while load byte unsigned (lbu) works
with unsigned integers.
 Programs want to deal sometimes with numbers that can be only
positive. (e.g. memory addresses)
 Unsigned Numbers!
 Example in C language names of integers (declared as int in the program)
and the latter unsigned integers (unsigned int).
20
 Example: converse the 16 bits representation of 2

into 32 bits representation of -2.
 2 ten = 0000 0000 0000 0010two
 1111 1111 1111 1101two
 + 1two
 = 1111 1111 1111 1110 two
 Creating a 32-bit version of the negative number means
copying the sign bit 16 times and placing it on the left :
 1111 1111 1111 1111 1111 1111 1111 1110 two = –2
ten

MIPS Addition Operations
21
 ADD vs. ADDU

 The designers of MIPs wanted to insure that the results of
an instruction were always *correct* according to their
specification.
 The desire for correctness in conflicts constraints of a
finite representation, particularly in the case of some
arithmetic operations.
 For example, adding two 32-bit numbers might result in a 33-bit
result. Or even worse, when using a 2s-complement.
representation adding two positive numbers might result in a
negative result. These anomalies are called “OVERFLOWS”

MIPS Addition Operations
22
 Two ways to fix this:

 Perform an explicit test either before or after every
operation (expensive overhead)
 Generate an *Exception* in the case of an overflow
 ADD - generates exceptions on overflows
 ADDU - does not generate exceptions on overflows

MIPS Logical Operations - Shift
23
 Sample coded operation: Shift Logical Left – SLL
 Assembly: sll $2, $2, 4 # $2= $2 << 4 -> this is equivalent

to $2=$2 * 24
 sll rd, rt, shamt:

MIPS Shift Operations
24
 MIPS shift instructions:

1. sll (shift left logical): shifts left and fills emptied bits
with 0s
2. srl (shift right logical): shifts right and fills emptied
bits with 0s
3. sra (shift right arithmetic): shifts right and fills
emptied bits by sign extending
 Example: Shift by 8 arithmetic
1001 0010 0011 0100 0101 0110 0111 1000

Using Logical Operations
25
 Masking:
1011 0110 1010 0100 0011 1101 1001 1010
0000 0000 0000 0000 0000 1111 1111 1111
The result of anding these two is:
0000 0000 0000 0000 0000 1101 1001 1010
 Used for isolating bits and bytes in a word.
 Zeroing some bits in a word:
andi $t0,$t0,0x0FFF
 Setting some bits as ones in a word:
 Let $t0 =0x12345678
 Then after: ori $t0, $t0, 0xFFFF
 $t0= 0x1234FFFF
 high-order 16 bits are untouched, while the low-order 16 bits are
forced to 1s).
Multiplication
26
 In MIPS:
 32-bit value x 32-bit value = 64-bit value
 General Syntax:
mult register1, register2
 Store high 32 bits in Register HI
 Store low 32 bits in Register LO
 Example:
 in C: a = b * c;
 in MIPS:
let b be $s2; let c be $s3; and let a be $s0 and $s1 (since it may be up to
64 bits)
mult $s2,$s3 # b * c
mfhi $s0 # upper half of product into $s0
mflo $s1 # lower half of product into $s1

Division
27
 General syntax: div register1, register2

 Divides 32-bit values in register 1 by 32-bit value
in register 2:
 puts remainder of division in HI
 puts quotient of division in LO
 We could use this Instructions to program /, % in C
language.

MIPS Immediate ALU Operations
28
 Works like constants.

 Example: addi $9, $11, -3
 General: addi rt, rs, immediate

 How about Larger Constants? > 16 bits?

MIPS Immediate ALU Operations
29
Example: Translating MIPS ALU operation into Machine

Language
addi $21, $22, -50
opcode = 8 (look up in table)
rs = 22 (register containing operand)
rt = 21 (target register)
immediate = -50 (by default, this is decimal)
Decimal
8 22 21 -50 Representation of
Machine Code
001000 10110 10101 1111111111001110 Binary

Representation of
Machine Code
Large Constants
30
 In order to load a 32-bit constant into a register a

two instruction sequence is used,
 "load upper immediate―.
 lui $8, 1010101010101010
 Then must get the lower order bits right, i.e.,
 ori $8, $8, 1010101010101010

MIPS Load/Store Instructions
31
 General Syntax
 lw rt, immediate(rs) #Reg[rt] = Mem[Reg[rs]+sxt(imm)]
 ―Fetch into rt the contents of the memory location whose
address is const (immediate) plus the contents of rs‖
 Abbreviation: lw rt, imm for lw rt, imm($0)
 sw rt, immediate(rs) #Mem[Reg[rs]+sxt(imm)] = Reg[rt]
 ―Store the contents of rt into the memory location whose
address is const plus the contents of rs‖
 Abbreviation: sw rt, imm for sw rt, imm($0)

MIPS Load/Store Instructions
32
 MIPS is a LOAD/STORE Architecture.

 Means that “all” data memory accesses are limited to load and
store instructions, which transfer register contents to-and-from
memory. ALU operations work only on registers.
 Introduce a new type of instruction format
 I-type for data transfer instructions
 Example: lw $t0, 32($s2)
35 18 8 32
op rs rt 16 bit number
 This instruction will take the pointer in $s2 (Base reg.), add
32 bytes (offset) to it, and then load the value from the memory
pointed to by this calculated sum into register $t0
Translating MIPS Assembly Language into Machine
Language
33
 Example
 If $t1 has the base of the array A and $s2
corresponds to h, the assignment
statement A[300] = h + A[300]; is
compiled into:
 lw $t0, 1200($t1) #reg $t0 gets A[300]
 add $t0, $s2, $t0 # reg $t0 gets h +
A[300]
 Sw $t0, 1200($t1) #Stores h+A[300]
back into A[300]
 The constant in a data transfer
instruction (300) is called the offset, and
the register added to form the address
($t1) is called the base register.
Example
34
 Using the op given and the number of used registers the MIPS
machine language code for these instructions?
 $ t0 = 8, $t1 = 9, $ s1 = 18
 Binary Equivalent

MIPS Branch Instructions
35
 Provide a way of conditionally changing the PC to some

nearby location... -> (Decision making)
Immediate
 I-type: Branch Instructions
 opcode specifies Beq vs. Bne
 Rs and Rt specify registers to compare
 Function:
 if (Reg[rs] == Reg[rt]) =>PC ← (PC + 4 ) + 4*sxt(immediate)
 if (Reg[rs] != Reg[rt]) => PC ← (PC + 4) + 4*sxt(immediate)

Branch Relative Addressing
36
 Relative Addressing:
 The size of the constant field (Immediate) = (16-bits) limits the
range of branches.
 PC is 32-bit pointer to memory
 So immediate cannot specify entire address to branch to.
 Solution? PC- Relative Addressing

 16 bits means +/- 215 bytes from the PC,
 But instructions are words.
 So the number of bytes to add to the PC will always be a multiple of 4.
 So specify the immediate in words.
 Now, we can branch +/- 215 words from the PC (or +/- 217 bytes), so
we can handle loops 4 times as large.
MIPS Branch Instructions
37
 Final calculation:
 If we don’t take the branch: (condition is false)
PC = PC + 4.
 If we do take the branch: (condition is true)
PC = (PC + 4) + (immediate * 4).
 Example:
Assuming (i at $s0, j at $s1, h at $s3)
in C : if (i == j) h = i + j;
in assembly language
bne $s0, $s1, Label
add $s3, $s0, $s1
Label: ....
Control Flow
38
 We have: beq, bne, what about Branch-if-less-than?

 New instruction: slt $t0, $s1, $s2
―Set if Less Than‖ if $s1 < $s2
then $t0 = 1
else
$t0 = 0
 We Can use this instruction to build new “pseudo-
instruction”
blt $s1, $s2, Label
 Note that the assembler needs a register to do this,
 There are policy of use conventions for registers
slt $1, $s1, $s2
bne $1, $zero, Label
Singed vs. Unsigned Comparison
39
 Example
 Suppose register $s0 has the binary number
 1111 1111 1111 1111 1111 1111 1111 1111two
 and that register $s1 has the binary number
 0000 0000 0000 0000 0000 0000 0000 0001two
 What are the values of registers $t0 and $t1 after these
two instructions?
 slt $t0, $s0, $s1 # signed comparison
 sltu $t1, $s0, $s1 # unsigned comparison
 The value in register $s0 represents - 1ten if it is an integer and
4,294,967,295ten if it is an unsigned integer. The value in
register $s1 represents 1ten in either case. Then register $t0
has the value 1, since - 1ten < 1ten, and register $t1 has the value
0, since 4,294,967,295ten > 1ten.
Control Flow
40
 4 combinations of slt & (beq / bne) :

slt $t0,$s0,$s1 # $t0 = 1 if g<h
bne $t0,$0,Less # if (g<h) goto Less
slt $t0,$s1,$s0 # $t0 = 1 if g>h

bne $t0,$0,Grtr # if (g>h) goto Grtr
slt $t0,$s0,$s1 # $t0 = 1 if g<h

beq $t0,$0,Gteq # if (g>=h) goto Gteq
slt $t0,$s1,$s0 # $t0 = 1 if g>h

beq $t0,$0,Lteq # if (g<=h) goto Lteq
Pseudo Instructions
41
 Pseudo instructions: bgt, ble, bge, la, li, move

 Not implemented in hardware
 Assembler expands/translate pseudo instructions into
machine instructions
 Register 1, called $at, is reserved for converting pseudo
instructions into machine code.
 Example
 La $s1, x # load $s1 with 32bit address x
 li $s1, x # load $s1 with 32bit data x

 assembler translates them into
 lui $s1, upper(x)
 ori $s1, $s1, lower(x)

MIPS Jumps
42
 The range of MIPS branch instructions is limited to

approximately ± 32K instructions from the branch
instruction. Unconditional jump instruction is used
for farther branches
 Jump Instructions:
 j label
# jump to label (PC = PC[31-28] || CONST[25:0]*4)
 jal label # jump to label and store PC+4 in $31
 jr $t0 # jump to address specified by register’s contents
 jalr $t0, $ra # jump to address specified by register’s contents
Note: Not all Architectures provide them all

MIPS Jumps
43
226 = 64 MWords
j: PC ← (PC & 0xf0000000) | 4*(immediate)

jal: PC ← (PC & 0xf0000000) | 4*(immediate);
Reg[31] ← PC + 4
MIPS Jump Example
44
 MIPS unconditional branch instructions:

j label
 Example:
C Code MIPS Code
if (i!=j) beq $s4, $s5, Lab1
h = i+j; add $s3, $s4, $s5
else j Lab2
h = i-j; Lab1:sub $s3, $s4, $s5
Lab2:...

MIPS Jumps Example
45
 Loops MIPS Code:

Loop: beq $9, $0, End
add $8, $8, $10
addi $9,$9,-1
j Loop
End:
 What is the code of beq instructions?
 op of beq = 4 (look up in table)
rs = 9 (first operand)
rt = 0 (second operand)
immediate = ???
 In this case, immediate = 3

Summary of Addresses in Branches and Jumps
46
 Relative addressing
 With respect to PC (program counter)
 Most branches are local (principle of locality)
 Jump instruction just uses high order bits of PC

 Address boundaries of 256 MBytes (maximum jump 64
Mwords)
 Format:
– 215 to 215 – 1 ~ ±32 Kwords
op rs rt 16 bit address
op 26 bit address
226 = 64 Mwords

Example: Loop in C
47
 Three types of loops in C:

 While, Do-While, For
 Example
i = o
while ( save[i] == k )
i += 1;
 Given a value for k, set i to the index of element in
array save [ ] that does not equal k.

MIPS Code for While Loop
48
 Compiler assigns variables to registers:
$s3 ($ 19) ← i initially Zero (0).

$s5 ($ 21) ← k
$s6 ($ 22) ← memory address where save [ ] begins
 Then generates the following assembly code:
Loop: sll $t1, $s3, 2 # Temp reg $t1 = 4 * i

add $t1, $t1, $s6 # $t1 = address of save[i]
lw $t0, 0($t1) # Temp reg $t0 = save[i]
bne $t0, $s5, Exit # go to Exit if save[i] ≠ k
addi $s3, $s3, 1 #i=i+1
j Loop # go to Loop
Exit:
 Assuming text segment starts at 0x80000
Machine Code and Addresses
49
Memory Machine code

Byte addr. Bits 31-26 | 25-21 | 20-16 | 15-11 | 10 – 6 | 5–0 | instrc.
80000 0 0 19 9 2 0 sll
80004 0 9 22 9 0 32 add
80008 35 9 8 0 lw
80012 5 8 21 Exit = +2
+2 bne
80016 8 19 19 1 addi
80020 2 Loop = 20000 (memory word address) j
80024 .....
Note: $t0 ≡ Reg 8, $t1 ≡ Reg 9, $s3 ≡ Reg 19, $s5 ≡ Reg 21, $s6 ≡ Reg 22
temp temp i k save
Finding Branch Address Exit
50
 Exit = +2 is a 16 bit integer in bne instruction

000101 01000 10101 0000000000000010 = 2
 $PC = 80016 is the byte address of the next instruction
00000000000000010011100010010000 = 80016
 Multiply bne argument by 4 (convert to byte address)
0000000000001000 = 8
 $PC ← $PC + 8
00000000000000010011100010011000 = 80024
Thus, Exit is memory byte address 80024.

Finding Jump Address Loop
51
 J 20000
000010 00000000000100111000100000 = 20000
 $PC = 80024, when jump is being executed
00000000000000010011100010011000 = 80024
 Multiply J argument by 4 (convert to byte address)
0000000000010011100010000000 = 80000
 Insert four leading bits from $PC
00000000000000010011100010000000 = 80000
Thus, Loop is memory byte address 80000.

Switch Case Example
52
switch (k) {
case 0: f=i+j; break; /* k=0*/
case 1: f=g+h; break; /* k=1*/
case 2: f=g-h; break; /* k=2*/
case 3: f=i-j; break; /* k=3*/
}
 We could rewrite the code using if-else structure
If (k == 0) f = I + j;
else if (k == 1) f = g + h;
else if (k == 2) f = g - h;
else if(k == 3) f = - j;
 Using this mapping:
f: $s0, g: $s1, h: $s2, i: $s3, j: $s4, k: $s5

Switch Case Example
 Final compiled MIPS code:
bne $s5, $0, L1 # branch k != 0
add $s0, $s3, $s4 # k == 0 so f = i+j
j Exit # end of case so Exit
L1:
addi $t0, $s5, -1 # $t0 = k-1
bne $t0, $0, L2 # branch k != 1
add $s0, $s1, $s2 # k == 1 so f = g+h
L2:
addi $t0, $s5, -2 # $t0 = k-2
bne $t0, $0, L3 # branch k != 2
sub $s0, $s1, $s2 # k == 2 so f = g-h
L3:
addi $t0, $s5, -3 # $t0 = k-3
bne $t0, $0, Exit # branch k != 3
sub $s0, $s3, $s4 # k == 3 so f = i-j
Exit:
Computer Architecture 1 53 3/27/2016
Supporting Procedures in Computer Hardware
54
 A procedure or function is one tool programmers use

to structure programs, both to make them easier to
understand and to allow code to be reused.
 Parameters act as an interface between the procedure and
the rest of the program and data, since they can pass values
and return results
 Procedures are one way to implement abstraction in
software.

Execution of a Procedure
55
 In the execution of a procedure, the program must

follow these six steps:
1. Put parameters in a place where the procedure can access
them.
2. Transfer control to the procedure.
3. Acquire the storage resources needed for the procedure.
4. Perform the desired task.
5. Put the result value in a place where the calling program can
access it.
6. Return control to the point of origin, since a procedure can be
called from several points in a program.

MIPS Procedure Convention
56
 MIPS Convention in using registers in procedural call:

 $a0–$a3: four argument registers in which to pass
parameters
 $v0–$v1: two value registers in which to return values
 $ra: one return address register to return to the point of

origin
 MIPS assembly language includes an instruction just for the
procedures => (Transfer control to the procedure.)
 jump-and-link instruction (jal):
 Jal ProcedureAddress
 An instruction that jumps to an address and simultaneously saves the
address of the following instruction (Return Address) in a register
($ra in MIPS).
Procedures in MIPS
57
 jal instruction actually saves PC + 4 in register $ra to

link to the following instruction to set up the procedure
return.
 MIPS use jump register instruction (jr), to help with

Case Statements, meaning an unconditional jump to the
address specified in a register: jr $ra

Procedures Writing Steps
58
 Put parameter values in argument registers, $a0 - $a3

 Save necessary values onto stack.
 Stack—a Last-In-First-Out (LIFO) memory queue
 Stack Pointer (SP): a pointer to the most recently allocated address in
the stack to show where the next procedure should place the registers
 Basic instructions: push (Add element to stack) & pop (Remove
element from stack).
 The register $sp always points to the last used space in the stack.
 To use stack, we decrement this pointer by the amount of space we
need and then fill it with info.
 jal call
 Put return address (PC+4) in $ra
 Jump to ―calee’s address‖
 Restore values from stack.
 Find returned parameters in value registers, $v0 - $v1
59
 Example: if we have the following function in C:

int leaf_example (int g, int h, int i, int j)
{
int f;
f = (g + h) – (i + j);
return f;
}
 What is the compiled MIPS assembly code?

 The parameter variables g, h, i, and j correspond to the argument
registers $a0, $a1, $a2, and $a3, and f corresponds to $s0.

60
 In MIPS we could write the code as follow:

add $t0,$a0,$a1 # register $t0 contains g + h
add $t1,$a2,$a3 # register $t1 contains i + j
sub $s0,$t0,$t1 # f gets $t0 – $t1, which is (g + h)–(i + j)
 Step 1: The compiled program starts with the label of

the procedure:
 leaf_example:
 Step 2: save the registers used by the procedure

 we need to save three registers: $s0, $t0, & $t1. We
―push‖ the old values onto the stack by creating space for
three words (12 bytes) on the stack and then store them:
61
addi $sp, $sp, –12 # adjust stack to make room for 3 items
sw $t1, 8($sp) # save register $t1 for use afterwards
sw $t0, 4($sp) # save register $t0 for use afterwards
sw $s0, 0($sp) # save register $s0 for use afterwards
The values of the stack pointer and the stack (a) before, (b) during, and (c) after the procedure call.
The stack pointer always points to the “top” of the stack, or the last word in the stack in this drawing.
62
 Step 3: Body of the function

add $t0,$a0,$a1 # register $t0 contains g + h
add $t1,$a2,$a3 # register $t1 contains i + j
sub $s0,$t0,$t1 # f = $t0 – $t1, which is (g + h)–(i + j)
 Step 4:
 Save return address:
 To return the value of f, we copy it into a return value register:

add $v0, $s0, $zero # returns f ($v0 = $s0 + 0)
 Step 5:
 Restore the three old values of the registers we saved by
―popping‖ them from the stack:

63
lw $s0, 0($sp) # restore register $s0 for caller

lw $t0, 4($sp) # restore register $t0 for caller
lw $t1, 8($sp) # restore register $t1 for caller
addi $sp,$sp,12 # adjust stack to delete 3 items
 Step 6:
 The procedure ends with a jump register using the return address:
jr $ra # jump back to calling routine
 MIPS separates registers:
 $t0–$t9: temporary registers that are not preserved by the
callee (called procedure) on a procedure call
 $s0–$s7: saved registers that must be preserved on a
procedure call (if used, the callee saves and restores them)

Allocating Space for New Data on the Stack
64
 Stack is also used to store variables that are local to

the procedure but do not fit in registers, such as local
arrays or structures
 Procedure frame or activation record: The segment of
the stack containing a procedure’s saved registers and local
variables
 MIPS software uses a frame pointer ($fp) to point to
the first word of the frame of a procedure
 A frame pointer offers a stable base register within a procedure
for local memory-references; because a stack pointer might
change during the procedure .

Allocating Space for New Data on the Stack
65
Stack allocation (a) before, (b) during, and (c) after procedure call. The frame
pointer ($fp) points to the first word of the frame, often a saved argument register, and the
stack pointer ($sp) points to the top of the stack

Allocating Space for New Data on the Heap
66
 Programmers need space in memory for static

variables and for dynamic data structures.
HEAP
MIPS Convention for Allocation of Memory

Allocating Space for New Data on the Heap
67
 Text segment: The segment of a UNIX object file that

contains the machine language code for routines in the
source file.
 Static data segment: the place for constants and other
static variables.
 To simplify access to static data, MIPS software reserves another
register, called the global pointer, or $gp.
 Heap segment: Although arrays tend to be a fixed
length and thus are a good match to the static data
segment, data structures like linked lists tend to grow
and shrink during their lifetime.
 This allocation allows the stack and heap to grow toward each
other, thereby allowing the efficient use of memory

MIPS Addressing Modes
68

Converting Machine Language into Assembly
Language
69
 Here are six machine language instructions in hex:

00001025
0005402A
11000003
00441020
20A5FFFF
08100001
 Let the first instruction be at address (0x00400000).
 Next step: convert to binary

Example Cont.
70
 The six machine language instructions in binary:
00000000000000000001000000100101
00000000000001010100000000101010
00010001000000000000000000000011
00000000010001000001000000100000
00100000101001011111111111111111
00001000000100000000000000000001
 Next step: separation of fields
Example Cont.
71
 Fields separated based on opcode:
0 0 0 2 0 37
0 0 5 8 0 42
4 8 0 +3
0 2 4 2 0 32
8 5 5 -1
2 00000100000000000000000001
 Next step: translate to MIPS instructions

Example Cont.
72
 Assembly Language: Version 1
0x00400000 or $2,$0,$0
0x00400004 slt $8,$0,$5
0x00400008 beq $8,$0, 3
0x0040000c add $2,$2,$4
0x00400010 addi $5,$5, -1
0x00400014 j 0x100001
 Better solution: translate to more meaningful

instructions (fix the branch/jump and add labels).

Example Cont.
73
 Assembly Language: Version 2
or $v0,$0,$0
Loop: slt $t0, $0, $a1
beq $t0, $0, End_Loop
add $v0, $v0, $a0
addi $a1, $a1,-1
j Loop
End_Loop:
 Next step: translate to C code (be creative!)

Example Cont.
74
 C code:
Mapping: $v0: product
$a0: mcand
$a1: mplier
product = 0;
while ( mplier > 0) {
product += mcand;
mplier -= 1; }

75

76

Table
Page A-50
77
MIPS Instruction:
add $8,$9,$10
0 9 10 8 0 32

MIPS Processor R3000: Registers

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MIPS Processor R3000: Registers

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MIPS Processor R3000

 RISC Type: Fixed Length: All MIPs instructions fit in a

 The size of a register in the MIPS architecture is 32 bits;

 Instructions execute simple functions.

Computer Architecture 1 3/27/2016

 RISC Type: Processor word is 32 bits long

 Instructions execute simple functions.

Computer Architecture 1 3/27/2016

 Three types of instructions:

Computer Architecture 1 3/27/2016

 R-type: 3 register operands (2 sources, 1 destination).

Computer Architecture 1 3/27/2016

Computer Architecture 1 3/27/2016

 Since 8-bit bytes are useful in many programs, virtually

Computer Architecture 1 3/27/2016

 Alignment Restriction: In MIPS Words must start at addresses that

Name Register number Usage

 Instructions, like registers and words of data, are also 32

 R-Type: Register Instruction Format:

000000 10001 10010 01001 00000 100000

Computer Architecture 1 3/27/2016

 op: Basic operation of the instruction, traditionally called

 All instructions have 3 operands

 Number representations in binary

 Least Significant Bit (LSB): rightmost bit in a MIPS word.

Computer Architecture 1 3/27/2016

 Positive & Negative Representation

 A separate sign bit means that sign and magnitude

 One’s Complement: Represents the most negative value by 10 .

equal number of negatives and positives but ending up with

 Solution? Pick the representation that made the

Computer Architecture 1 3/27/2016

 Has the advantage that all negative numbers have a 1

Computer Architecture 1 3/27/2016

 Signed versus unsigned applies to loads as well as to arithmetic.

 Example: converse the 16 bits representation of 2

Computer Architecture 1 3/27/2016

 ADD vs. ADDU

Computer Architecture 1 3/27/2016

 Two ways to fix this:

 ADDU - does not generate exceptions on overflows

Computer Architecture 1 3/27/2016

 Sample coded operation: Shift Logical Left – SLL

 Assembly: sll $2, $2, 4 # $2= $2 << 4 -> this is equivalent

Computer Architecture 1 3/27/2016

 MIPS shift instructions:

Computer Architecture 1 3/27/2016

Computer Architecture 1 3/27/2016

 General syntax: div register1, register2

Computer Architecture 1 3/27/2016

 Works like constants.

 General: addi rt, rs, immediate

Computer Architecture 1 3/27/2016

Example: Translating MIPS ALU operation into Machine

001000 10110 10101 1111111111001110 Binary

 In order to load a 32-bit constant into a register a

Computer Architecture 1 3/27/2016

Computer Architecture 1 3/27/2016

 MIPS is a LOAD/STORE Architecture.

Computer Architecture 1 3/27/2016

 Provide a way of conditionally changing the PC to some

 Rs and Rt specify registers to compare