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A CMOS Low Power Digital Polar

Modulator System Integration for WCDMA
Transmitter
Dae Woon Kang , Member, IEEE, Yong-Bin Kim, Senior Member, IEEE, and James T. Doyle,
Senior Member, IEEE
Abstract— Digital polar modulator for WCDMA transmitters
is integrated in a 0.5µm CMOS technology. A
CORDIC(coordinate rotation digital computer) processor
which converts rectangular coordinate to polar coordinate is an
essential requirement for low-cost implementation of the polar
modulator since it reduces the circuit complexity by
performing a sequence of elementary rotations using shift and
add operations without multiplications. Hard wired-logic to
eliminate the shifter and pre-calculated arctan angle value are
used, and linear interpolators to extend the sampling rate for
WCDMA specification are implemented to decrease the
operating frequency. This approach reduces cost in both size
and power. The average power consumption is 76mW with
50MHz clock and 5V power supply.
Index Terms—WCDMA, CMOS CORDIC, Low Power.
decreased battery life. Furthermore, I/Q based transmitter
design can be problematic in multi-band operation since
baseband mixing produces unwanted spurious products.
Additional circuitry, such as SAW filters to reject these
adverse signals and minimize wideband noise, increases the
size, and power consumption of the transmitter.
Fortunately, a polar modulation offers an alternative for
multimode and multiband operations [3]. Fig. 1 depicts a
high level architecture abstraction of a polar transmitter for
WCDMA transmitters. The shaded block shows the proposed
polar modulator which consists of a CORDIC processor,
interpolators, a barrel-shifter, and a DAC-PWM generator.
The digitized amplitude envelope through an amplitude
modulation and the synchronized phase-modulated RF carrier
through a phase modulation are recombined at the power
amplifier to produce linear and efficient RF transmission.

I. INTRODUCTION

T he future of the computer and communications industries

is converging on mobile information appliances-
phones, PDAs, laptops and other devices. Improvements in
systems-on-chip technology allow placing of a complete
embedded system on a single chip with high performance,
low power, and low cost. The state-of-the-art of the deep
sub-micron silicon technology has permitted more than
billion gates on a chip. Integration of various functions on a
single chip increases bandwidth of the system and reduces Fig. 1. Polar transmitter architecture for WCDMA.
RC delays and power-consumption and thus increases overall
system performance. The advent of third generation In burst-mode communication systems, a rapid carrier is
standards (3G) has created new demands on multimode
crucial. Therefore, a fast rectangular-to-polar conversion of
systems that can support various modulation formats such as
CDMA, TDMA, EDGE, GSM, GPRS, and WCDMA [1]. To the CORDIC processor is desired. And the delays-matching
achieve multimode operation, transmitters must of amplitude and phase is crucial since the restoration of the
accommodate constant envelope signals as well as non- transmitted data at the PA (Power Amplifier) may be
constant envelope signals [2]. To avoid distortion of non-
imperfect if the delays are not matched.
constant envelopes, conventional transmitters must employ
linear (class-A) or use predistortion techniques to linearize
slightly saturated (class-AB) amplifiers. Both This paper presents a high power-efficiency WCDMA
implementations sacrifice power efficiencies and result in transmitter module system integration into a single chip in a
sub-micron technology (0.5um) that is used for designing

Manuscript received Febrary 3, 2005. power amplifiers. This allows the module and power
D. W. Kang is with National Semiconductor Corp., Longmont, CO 80501
USA (phone: 303-845-4069; fax: 303-845-4005; e-mail: cdwksc@ nsc.com). amplifiers to be integrated in the same die, and makes the
Y-. B. Kim was with University of Utah, Salt Lake City, UT 84112 USA.
He is now with the Department of Electrical and Computer Engineering, application chipper, lower power, and lower cost. This paper
Northeastern University, Boston, MA 02115 USA (phone:617-373-2919, demonstrates the efficiency of the system integration of
fax:617-373-8970; e-mail: ybk@ece.neu.edu).
J. T. Doyle is with National Semiconductor Corp., Longmont, CO 80501 polar modulation with low cost hardware available for a
USA, (e-mail: jimd@ia.nsc.com).
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TABLE I
broad market for consumer products. Section 2 contains a 10-BITS BINARY VALUES FOR ARCTAN (2- )
I

description of the mathematics behind the CORDIC Step arctan Angle (degree) 10-bits binary
algorithm, and the proposed polar modulation architecture is
1 arctan(2 ) 0
45.0000 7F = 00 0111
described in Section 3. The simulation and experimental 1111
2 arctan(2 ) -1
26.5651 4B = 00 0100
results of the polar modulator are presented in Section 4. 1011
3 arctan(2-2) 14.0362 27 = 00 0010
II.CORDIC ARCHITECTURE FOR POLAR MODULATION 0111
4 arctan(2-3) 7.1250 14 = 00 0001
There are two well-known implementations for a 0100
rectangular to polar coordinate conversion to obtain the 5 arctan(2 ) -4
3.5763 A = 00 0000 1010
6 arctan(2-5) 1.7899 5 = 00 0000 0101
magnitude and phase of a complex number. One method uses 7 arctan(2-6) 0.8952 2 = 00 0000 0010
a ROM lookup table with both real and imaginary  X n +1   1 − tan θ n   X n 
components as inputs. This is practical for lower accuracy  Y  = cos θ n tan θ 1   Yn 
requirements as the ROM size grows exponentially with  n +1   n
increasing number of input bits. The other approach is the (2)
CORDIC processor [5] which can realize low-cost systems
by reducing system complexity. The CORDIC arithmetic Implementation of (2) requires three multiplications. Two
technique makes it possible to perform two dimensions multipliers are eliminated by selecting the angle steps such
rotations using simple hardware components without that tangent of a step is a power of 2. Dividing by a power of
multipliers. 2 is implemented using a shift-right operation. The angle for
A distinct feature of the CORDIC algorithm is that it uses a each step is given by
sequence of elementary rotations to realize a variety of
complicated and non-linear elementary functions. Each
elementary rotation requires simple simultaneous shift and  1 
θ n = arctan n  (3)
add operations. By unfolding the iterations for elementary 2 
rotation, a pipelined CORDIC array processor can be realized
[6, 7], which achieves greater speeds of computation such All summed iteration-angles are equal to the rotation angle
that many partial results can be calculated simultaneously. θ.

A. CORDIC Vectoring Mode for Polar Modulation ∞ − 1 if Yn < 0

The CORDIC algorithm performs a planar rotation which ∑S θ n n = θ , Sn = 
means transforming a vector (Xi, Yi) into a new vector (Xj, n =0 + 1 if Yn ≥ 0
Yj) as shown in Fig. 2(a). (4)

Define a variable called Z which represents the part of the

angle θ as given in (5).

n
Z n +1 = θ − ∑θ i (5)
i =0
This results in

(a) (b)
tan θ n = S n 2 −n (6)

Fig.2. Vectoring mode for polar modulation. Combining (2) and (6) gives
Using a matrix form, a planar rotation for a vector of (Xi,
Yi) is defined as  X n +1   1 − Sn 2−n   X n 
 Y  = cosθ n  −n  
 n +1  Sn 2 1   Yn 
 X j  cos θ − sin θ   X i 
Y  =  (7)
cosθ   Yi 
(1)
 j   sin θ
The cosθn coefficient is eliminated by pre-computing the
The θ angle rotation is executed in several steps. Each step final result (assume that n = 8).
is defined as in Table 1, and modified by eliminating the
cosθn factor as ∞
  1 
K = ∏ cos arctan n   ≈ 0.607259
n=0   2 
(8)
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III. THE POLAR MODULATOR ARCHITECTURE FOR WCDMA

If the congregate constant K is ignored, the calculation
which the CORDIC performs is formulated as
X n +1 = X n − S n 2 −2 n Yn
Yn +1 = Yn + S n 2 −2 n X n
−n
Z n +1 = Z n − S n arctan( 2 )
There is a special case, referred to as the vectoring mode,
driving Y to zero. As shown in Fig. 2(b), the CORDIC core
computes
1
[X j ]
,Y j , Z j =  X i2 + Yi 2 , 0, arctan i
K
(10)
where the arctan is pre-calculated as shown in Table I.
B. Polar Pre-/Post-processing for WCDMA Transmitters
Since I/Q data-streams’ polarity is always positive due to
the DAC’s input, the origin is moved to the center of data’
range as shown in Fig. 3(a). Then, a quadrant move is
performed to the first quadrant from the other quadrants in
Fig. 3(b). In the post-processing, the CORDIC processor
recovers the original quadrant and scales the congregate
constant.
TRANSMITTERS
Fig. 1 depicts a high level architecture abstraction of a
polar transmitter for WCDMA transmitters. A signal can be
expressed in polar form as a magnitude and a phase. The
(9) shaded block shows the proposed polar modulator which
consists of a QPSK (Quadrature Phase Shift Keying)
modulator, a CORDIC processor, two interpolators, a barrel-
shifter, and a DAC-PWM generator. The QPSK modulator
provides I (sine) and Q (cosine) data streams from a low
frequency serial data. The CORDIC processor transforms the
Cartesian coordinates (sine and cosine) from the digital I/Q
(In-Phase Quadrature) modulator into polar coordinates
Y (amplitude
 and phase). The linear interpolator generates three
intermediate
 values for the amplitude and angle to meet the
 Xi sampling
 requirement of WCDMA. The barrel-shifter
produces a gain for the amplitude. And the DAC-PWM
generator outputs a serial data for the amplitude.
A. QPSK Modulator
In communication systems, information is often conveyed
by means of a bandpass signal, which results from
modulating a sinusoidal carrier. In continuous-time case, any
bandpass signal, s(t) with carrier frequency ωc=2πfc, can be
represented by the unique complex signal sc(t)
s (t ) = Re sc (t )e jωct
(11)

where sc(t) is called the complex envelope of the modulated

signal. Equation (11) can be rewritten as

s (t ) = sc (t ) cos( ωc t +θ(t )) = I (t ) cos ωc t −Q (t ) sin ωc t

(12)
where sc (t ) = I (t ) − jQ (t ) = sc (t ) e jθ ( t )
sc (t ) = I 2 (t ) +Q 2 (t )
(a) (b)
I (t )
Fig. 3. Pre-processing for a polar transmitter. θ(t ) = tan −1 ( )
Q (t )
where I(t) is the in-phase component and Q(t) is the
C. Trade-off between Cost and Accuracy quadrature-phase component.
There is a trade-off between implementation costs and The characterization of continuous-time signals given
numerical accuracy [4]. The accuracy of a CORDIC above can be carried over to discrete-time signals. Such
processor is dependent on the internal word length used for signals are obtained by sampling a continuous-time signal
the three input variables as well as the number of iterations. uniformly at a sufficiently high rate and expressed as
A reduction of the number elementary iterations for a
specific algorithm significantly reduces the latency as well as 2πFc
hardware cost. It is desirable to find the optimal number of j n 2πFc 2πF
s ( n) = Re sc (n)e Fs
= Re sc ( n)(cos n + j sin
iterations Fs Fs
The internal bus width limits the maximum number of
(13)
useful pipelines. Therefore, the peak accuracy is achieved
after “the internal bus width” iterations. To increase where sc (n) = I (n) − jQ ( n) = sc ( n) e jθ ( n )
accuracy, extension bits are added. However, there are still
truncation errors. On the other hand, the accuracy of the sc ( n) = I 2 ( n ) + Q 2 ( n)
rotation angle is determined by how closely the input rotation I ( n)
angle was pre-calculated. There is the angle approximation θ( n) = tan −1 ( )
Q ( n)
error due to the finite set of angles.
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The sampling rate Fs in Hz is high enough to satisfy Fs >
2Fc+Bc, and Fc and Bc are the intermediate carrier
frequency in Hz and the bandwidth of Sc in Hz, respectively.
The carrier becomes a phase reference and the signal is
interpreted in reference to the carrier in phase modulation
(PM) which changes only the phase of the signal. The phase
is referenced to the carrier n most communication systems.
QPSK among various possibilities for PM is the most
promising candidate due to its high bandwidth efficiency. In
QPSK modulation, pairs of bits are mapped in the signal
constellation π/2 degrees apart. QPSK modulators provide
constant amplitude, 90° vectors: 0°, 90°, 180°, and 270°.
When the carrier phase varies by 180 degrees, the phase
changes cause additional symbol errors due to carrier
amplitude variations. And power amplifiers for QPSK
modulation must be specified for linear operation, namely 1
dB compression and harmonic suppression.
. operation.
Fig. 4. QPSK modulation and waveforms.
The QPSK modulator consists of serial-to-parallel
converter, spreader, PSK modulator, and adder as shown in
Fig. 4. In the direct sequence spread spectrum technique, a
pseudo random number (PRN) is applied directly to the data
entering the carrier modulator. The modulator, therefore,
sees much higher bit rate corresponding to the chip rate of
the PRN sequence. The result of modulating RF carrier with
such code sequence is to produce a direct-sequence-
modulated spread spectrum with {(sin x)/x}2 frequency
spectrum, centered at the carrier frequency. The direct-digital
synthesizer (DDS) produces sinusoids at a given frequency
by look-up tables. Multipliers in QPSK modulator generate
quadrature modulation, and the outputs from the multipliers
are summed (tx_out) and fed to a DAC. The waveforms in
Fig. 4 show the output values at each stage. Fig. 5 shows the
block diagram of QPSK modulator for a polar modulator,
which needs separate I and Q streams.
4
Fig. 5. Block diagram of I/Q modulator.
B. Rectangular to Polar CORDIC Architecture
A CORDIC element (CE) architecture is shown in Fig. 6.
The datapath of the CE has 2-bits fixed point extension
which reduces truncation errors. Using cyclic convolution
provides the advantages of high computing parallelism and
low computation complexity. A parallel structure as shown in
Fig. 7 consists of an array of CEs, each of which performs a
computation in parallel and is separated by registers to form
a pipelined structure.
The CE is the kernel of the CORDIC processor and its
primary function is to perform (9). The rectangular to polar
CORDIC accepts three input variables Xi, Yi, and Zi and
generates the output Xj, Yj, and Zj. It is operated in the
vectoring mode where variable Yi is forced to zero. In other
words, the coordinate components after rotation are given
and the algorithm calculates the angle of rotation. From the
hardware implementation point of view, this operation is
carried out using only shift and add operations since
multiplication of any quantity by 2-i is a shift of the binary
representation of the quantity by i-bit to the right. As a result,
all the evaluation procedures in CORDIC are computed as a
rotation of a vector in three different coordinates systems
with an iterative unified formulation. For example, the
operation is to sum or subtract a shifted valued of Xi to Yi to
obtain Yi+1, a shifted valued of Yi to Xi to obtain Xi+1, and a
pre-calculated value ai to Zi. Actually the above procedure
identified a pseudo-rotation rather than a rotation because it
ignores the congregate constant K which needs scaling
Fig. 6. CORDIC element architecture abstraction.
The main components of each CE are three adders, shifter,
look-up table, and a register. Since the function of the shifter
in the pipeline is fixed, the shift operation can be
implemented by wiring. Moreover, the lookup table can be
replaced with hardwired logic because each stage has a
congregate constant instead of a lookup table. Therefore,
only three adders and a register are the main components for
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a CE. Adopting the wire-based implementation greatly
reduces the hardware cost.
Figure 7 depicts the entire design which consists of three
modules, the pre-processing, pseudo-rotation and the scaling
factor blocks are very fast parallel, pipeline structures. Since
the RF digital baseband output is unsigned binary and is the
input of the CORDIC processor, the unsigned values are
converted to signed binary by moving the origin. The pre-
processing module also performs a movement to quadrant
one from the other quadrants. The function of the post-
processing block is to scale the magnitude and to recover the
original quadrant. To do this, the post-processing stage
consists of adders and wired-shifters.
Fig. 7. CORDIC processor architecture abstraction
. SPICE netlist is exported. This SPICE netlist is simulated
C. Post-processing for WCDMA requirements
For larger word sizes, it is not economical to extend the
sampling rate from 8 to 32 for WCMA input data using the
direct ROM approach. Therefore, an unsigned linear
interpolation technique is used where the distance between
tabulated points is uniform. Figure. 6 shows the uniform
interpolator which generates three intermediate values
between two inputs. The counter selects one of the outputs.
The interpolation method can reduce the clock frequency for
CORDIC and the interpolators except for the counter, and in
turn decreases the power dissipation of those blocks by factor
of 4.
The output of the barrel-shifter block reflects a gain from
the external inputs. There is an overflow signal which
indicates the output of the DAC-PWM module is out-of-
range, and the output is fixed as the maximum value. To
match the delays of the amplitude and angle, registers are
used at the final stage. The angle ports have additional
MUXes for serial- and parallel-outputs. The delay difference
is less than 1ns.
5
Fig. 8. Unsigned-linear interpolator.
The DAC-PWM module in Fig. 1 converts parallel data to
serial data. This makes the switch mode regulator simpler at
the expense of data loss (32-sampling) and high power
consumption due to high clock frequency.
IV. SIMULATIONS AND EXPERIMENTAL RESULTS
To simulate and verify the modulator, the input data is
generated by digital I/Q modulator implemented using Altera
Flex10K FPGA. The 10-bit CORDIC processor and other
post-processing blocks are modeled in Verilog HDL and are
fully synthesized. The datapath of CORDIC core consists of
0-latency pre-processing, 8-latency pipeline, and 2-latency
post-processing. Cadence Verilog-XL is used for simulation
and functional verification of the CORDIC processor and
other post-processing blocks. . Synthesis is achieved with
Synopsys’ Design Compiler. Low power clock buffers are
synthesized for the clock signals of the individual stages. The
automatic P&R
(Place and Route) is generated using Apollo from Synopsys.
The design is mapped onto a 0.5µm four metal CMOS
technology. The layout used the standard cell based design
flow of Apollo with 80% core utilization (1.1x1.3mm 2,
10,000 gates). The nominal supply voltage for core cells is
5V. Post-layout parasitic parameters are extracted and the
using Nanosim from Synopsys with the same Verilog test
bench used for the behavioural model. The correct timing
behaviour of the processor is observed. The average power
consumption of the core is about 76mW with a 50MHz clock
frequency and 5V supply. Fig. 9 shows the die photo of the
digital polar modulator.
Table II lists the errors between the results and the
calculations caused by truncation and limited pipeline stage.
X, Y and X’, Y’ are the unsigned and the signed 10-bits
inputs, respectively (See Fig. 3(a)). R is the polar magnitude
from the origin (512, 512), and A is the polar phase angle
whose maximum value 1024(0 indicates 360°). The error
between the calculation and the results for the modulator
including a channel noise is tolerable during demodulating.
Fig. 10 shows an example of the phase distortion at the
receiver due to the accumulated error. The error from the
CORDIC can be reduced by increasing the fixed point
extension and the CORDIC pipeline stages. Figure. 11 shows
a demo-board for polar modulation.
V. CONCLUSION
Due to CORDIC’s regularity and simplicity, the proposed
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transmitter’s architecture is very suitable for VLSI TABLE II

POST-LAYOUT SIMULATION RESULTS AND CALCULATIONS
implementation. The CORDIC architecture proposed in this
Input Output Calculation
paper adopts a hard wired pipeline strategy to increase the
performance and reduce the size at the architectural level. X (X’) Y (Y’) R(o) A(o) R(c) A(c)
The separate distribution of angle constants to each adder 612 (100) 562 (50) 112 75 111.80 85.33
612 (100) 612 (100) 142 127 141.42 128.00
also permits a hardwire solution instead of using a lookup 612 (100) 712 (200) 224 181 223.61 170.67
table, and all the shifters are hard-wired. Moreover, the 512 (0) 712 (200) 200 255 200.00 256.00
interpolation method reduces the clock frequency of the 412 (-100) 712 (200) 224 331 223.61 341.33
412 (-100) 612 (100) 142 385 141.42 384.00
CORDIC and the interpolators except for the counter, and in 412 (-100) 562 (50) 112 437 111.80 426.67
turn decreases the power dissipation of those blocks by factor 412 (-100) 512 (0) 100 511 100.00 512.00
of 4. . And the delays-matching of amplitude and phase is 412 (-100) 462 (-50) 112 587 111.80 597.33
412 (-100) 412 (-100) 142 639 141.42 640.00
accomplished in 1ns. The proposed digital polar modulator is 412 (-100) 312 (-200) 224 693 223.61 682.67
designed, integrated, and fabricated using 0.5µm CMOS 512 (0) 312 (-200) 200 769 200.00 768.00
process, tested, and used successfully for CDMA 612 (100) 312 (-200) 224 843 223.61 853.33
612 (100) 412 (-100) 142 897 141.42 896.00
applications. The modulator will be a good reference for low 612 (100) 462 (-50) 112 949 111.80 938.67
power communication chip VLSI integration, especially SoC 612 (100) 512 (0) 100 1 100.00 0.00
(Systems-on-Chip).
QPSK
CORDIC
modulator

Fig. 9. The digital polar modulator die photo

Fig. 11. Demo-board of the polar modulator(before

integration).

REFERENCES
[1] E.W. McCune, “Multi-mode and Multi-band Polar Transmitter for GSM,
NADC, and EDGE”, WCNC 2003, 16-20, March 2003.
[2] D. Rudolph, “Out-of-Band Emissions of Digital Transmissions Using
Kahn EER Technique”, IEEE Trans. On Microwave Theory and
Techniques, vol. 50, no. 8, pp.1979-1983, August 2002.
[3] L.R. Kahn, “Single-Sideband Transmission by Envelope Elimination &
Restoration”, Proc. IRE, 803-806, July 1952.
[4] K. Kota, & J. Cavallaro, “Numerical Accuracy and Hardware Tradeoffs
Fig. 10. An example of a QPSK constellation. for CORDIC Arithmetic for Special-Purpose Processors”, IEEE Trans.
On Computers, vol. 42, no. 7, pp. 769-779, July 1993.
[5] A. Chen, & S. Yang, “Reduced complexity CORDIC demodulator
implementation for D-AMPS and digital IF-sampled receiver”, Proc.
Globecom ’98, pp. 1491-1496, Nov. 1998.
[6] Y. Hu, “CORDIC_Based VLSI Architecture for Digital Signal
Processing”, IEEE Signal Processing, vol. 19, no. 3, pp. 16-35, July
1992.
[7] E. Deprettere, P. Dewilde, & R. Udo, “Pipelined
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1200
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Dae Woon Kang (S’00-M’04) received the B.S.

and M.S. degrees in Electrical Engineering from
the Yonsei University in Seoul, South Korea in
1991, and 1993, respectively, and the Ph.D. degree
in Electrical and Computer Engineering from the
Northeastern University at Boston, MA in 2003,
with a Ph.D. dissertation entitled “Low Power
Digital Adaptive Voltage Controller Design Based
on Hybrid Control and Reverse Phase Mode.”
He is currently Senior Circuit Engineer at
National Semiconductor Corp., Longmont, CO.
His research interests include adaptive voltage
scalings, delay-locked-loops, and low-power digital circuits and
methodologies. He was a summer intern for National Semiconductor Corp in
2002 when he designed a fully digital AVS controller. He was a summer
intern for Compaq Corp. in 2001 when he was involved in developing the
latest version of Alpha processor. His role was Alpha’s clock-tree and DLL
analysis and migration to a 0.125µm SOI technology. He was Senior Logic
Engineer at Samsung Electronics from 1993 to 1998. He developed several
ASIC designs. He has authored several papers and patents pending.

Yong-Bin Kim was born in Seoul, South Korea

in 1960. He received the B.S. degree in Electrical
Engineering from Sogang University in Seoul,
South Korea in 1982, the M.S. degree and PH.D
both in Computer Engineering from New Jersey
Institute of Technology and Colorado State
University in 1989 and 1996, respectively. From
1982 to 1987, Dr. Kim was with Electronics and
Telecommunications Research Institute in South
Korea as a Member of technical Staff. From 1990
to 1993 he was with Intel Corp. as a Senior
Design Engineer, and involved in micro-
controller chip design and Intel P6 microprocessor chip design. From 1993 to
1996 he was with Hewlett Packard Co., Fort Collins, Colorado as a Member
of Technical Staff, and involved in HP PA-8000 RISC microprocessor chip
design. From 1996 to 1998 he was with Sun Microsystems, Palo Alto,
California as an individual contributor, and involved in 1.5GHz Ultra Sparc5
CPU chip design. From 1998 to 2000, he was an assistant professor in the
Dept. of Electrical Engineering of University of Utah.
He is currently Zraket Endowed Professor in the Department of Electrical
and Computer Engineering at Northeastern University. His research focuses
on low power analog circuit design, high speed low power VLSI circuit
design and methodology.

James T Doyle, P.E; Senior Member of the IEEE,

BSEE 1972. MBA 1992 Presently Senior
Member of the Technical Staff (SMTS) and Chief
Technologist of National’s Portable Power
Product Group (PPS). He is now responsible for
CMOS PA controller design at National
Semiconductor. Presently 2 National designs are
being used in TriQuint GSM,GPRS and EDGE PA
modules, the smallest in the industry. Formerly,
he was a Chief Technologist for CCG Division of
Intel Corporation in Chandler Arizona and chief
architect of the 3G Mitsubishi Analog Baseband
Chip done by Intel. He was the technical lead on
the Solano 815 chip set project while at Intel. He
is a contributing author to the ISO8803.3 Ethernet Standard. He spent 13
years in Motorolas Handheld products division in Ft Lauderdale and
contributed to the HT, MX Saber Radio Line.
He has about 50 patents to his credit and has publish approximately 10
technical articles plus designed or modified over 200 chips in his career.