CHAPTER 1

INTRODUCTION

Low noise amplifiers (LNAs) play a key role in radio receiver performance. The
success of a receiver’s design is measured in multiple dimensions: receiver sensitivity,
selectivity, and proclivity to reception errors. The RF design engineer works to
optimize
receiver front−end performance with a special focus on the first active device.

1.1 BACKGROUND

The first active amplification component of a receiver is a Low Noise Amplifier

(LNA) [1]. The main function of LNA is to amplify the signal to suppress the noise of
subsequent stages while adding as little noise as possible. The performance of RF
receiver is significantly influenced by the LNA. Operating frequency also depends on
the RF filter used in front of LNA.

Fig. 1.1 RF Receiver

.
In more recent years microwave frequencies have also come into widespread use in
communications systems, radar applications; since the propagations of microwave is
effectively along line-of-sight paths.

The growth of wireless service and other telecom application has pushed the
semiconductor industry towards complete system on chip solutions. Wireless system
comprises of a front-end and a back end section. The front end section process analog
signals in the high radio frequency range, while the back end section process analog

1
and digital signals in the baseband low frequency range.

Fig.1.2 Basic low noise amplifier

The radio frequency signal received at the antenna is weak. Therefore an amplifier
with high gain and good noise performance is needed to amplify this signal before it
can be fed to others part of the receiver. Such an amplifier referred to as a low noise
amplifier as shown in Figure 2.1. The first stage of the receiver is typically a low noise
amplifier, whose main function is to provide enough gain to overcome the noise of
subsequent stages (such as mixer). Aside from providing this gain while adding as
little noise as possible, an LNA should accommodate large signals without distortion,
and frequently must also present specific impedance. The general topology of low
noise amplifier can be broken down into the three stages: input matching, amplifier
and the output matching. Low noise amplifier used in various applications like ISM
radio, cellular/PCS handsets, GPS receiver, cordless phone, wireless LAN, wireless
data, satellite communication etc.

1.2 DESIGN FLOWCHART

In the designing of low noise amplifier, some basic aspect of low noise amplifier
should be kept in mind. Since in low noise amplifier there is trade-off between many
factors i.e. gain, noise figure, stability, power consumption, and nonlinearity etc. Flow

2
chart of LNA design is shown below that describes the design flow of low noise
amplifier.
The design starts from some basic specification means some standard output values
that is desired for any circuits design these specifications are scattering parameters,
Gain, Noise Figure, Stability, Power, linearity etc. and our aim, tends to achieve these
specified values. Second step in the design is choice of technology so here; CMOS
technology has chosen for this design. Third step is choice the topology, there are
different types of topologies and among them we can use topology depending on our
design. Fourth step is some basic calculation like device width and last if there is
some impedance mismatch so we have to do impedance matching by inserting a filter
network.

Specifications: S parameters, Gain, Noise Figure, Stability, Power

etc.

Choice of Technology: CMOS, BiCMOS, GaAs, HEMT etc.

Choice of Topology: Source degeneration, Common

gate,Cascode etc.

Size of Device: Width

,Length.

Biasing: Fixed bias, Voltage divider,Current mirror

etc.

Matching: Input matching and Output matching

Fig. 1.3 Flow chart of3designing process for LNA

1.3 LOW NOISE AMPLIFIER SPECIFICATIONS

LNA amplification is one the most critical stage which affects the entire device
performance. Due to which chief importance is given on its parameters.

1.3.1 SENSITIVITY

The sensitivity of an RF receiver is the minimum magnitude of input signal required

to get a specified output signal having a specified SNR. In the other term sensitivity
represents as responsivity. Receiver sensitivity indicates that how faint an input signal
can be to be successfully received by the receiver, so lower power level will be better.
Sensitivity of the receiver is mainly determined by the LNA noise figure and power
gain.

1.3.2 NOISE FIGURE

The Noise performance of an Low noise amplifier is represented by its noise figure.
The Noise figure is a measurement of the noise performance of a circuit[4][10]. It is
expressed in decibels.

NF = 10 log10 F
F= ( SNRin /SNRout )

S/N input NF S/N Output

Fig. 1.4 Noise Figure of a System

Where SNRin and SNRout are the SNRs at the input and output of the amplifier
respectively.

1.3.3 NOISE FIGURE OF CASCADED STAGES

For a cascade system of N stages, the overall noise factor can be obtained in terms of
the noise factor and gain in each stage [4].

4
 Fig. 1.5 NF of Cascaded System

Total noise factor for cascaded stages is given by Friis’s formula.

F = F1 + F2−1/G1 +F3−1/G1G2+.......+Fi-1/G1G2-Gi-1

(1)

Where Fi and Gi are the noise factor and available power gain, respectively, of the i-
th stage and n is the number of the stages.

1.3.4 S-PARAMETERS

There are many ways to represent the behavior of a two-port network. At low
frequency generally Z, Y, H and ABCD parameters are used. S-parameters play an
important role in RF systems. Z-parameter and h-parameter is difficult to use in the
RF-system. Short circuit and open circuit do not behave the same at radio frequencies
because of inductance and capacitance present in a transmission line. S-parameters
are the best way to measure incident and reflected wave power in a two-port network
for RF block.

5
 Fig. 1.6 Two-Port Network []

S11 = Input reflection coefficient with matched output port

S12 = Reverse transmission coefficient with matched input port

S21= Forward transmission coefficient with matched output port

S22 = Output reflection coefficient with matched input port.

For the LNA amplifier from design point of view, S11 and S22 denote the input and
output impedances matching. S21 measures the amplification gain of the amplifier
and S12 represents the isolation between input and output ports.

1.3.5 STABILITY

Stability is a major concern in RF amplifiers. It is obvious that an LNA may become

an oscillator if it is unstable in the circuit performance. After circuit designing its
stability should be examined by the designer. The parameter through which stability
of the LNA is measured is known as stability factor (K). It’s value should be greater

6
than 1. The stability of a circuit is characterized by the stern stability factor given in
equation (2).

(2)

Δ = S11S22-S21S12

1.3.7 1-dB COMPRESSION POINT

Gain reduction due to the nonlinearity of the transfer function of the amplifying
device is called gain compression. The 1-dB compression point is the one of the
technique to measure gain compression. It is defined as the input signal level for
which the gain of the amplifier drops by 1-dB. By the help of 1-dB compression point
we can calculate the maximum input range of our design.

Fig. 1.7 1-dB Compression Point [21]

1.3.8 THIRD ORDER INTERCEPT POINT

The Third order intercept point is the measure for nonlinear system. It indicates that
how well a receiver performs with the distortion.

7
 Fig. 1.8 Third Order Intercept Point [21]

It’s based on nonlinearity which derived from Taylor series expansion. It relates to
the third order nonlinear term generated to the linear amplified signal. The
intersection of the line of the fundamental first order output and 3rd order
intermodulation product is called the third intercept point.

1.4 TECHNOLOGY SELECTION

Now-a-days, power consumption and cost efficiency play a crucial role in the recent
market trends due to this CMOS technology is used to get low power consumption
along with high packing density [4]. CMOS Technology has several advantages such
as

 Low cost
 Low static power dissipation
 Low area
 Low noise
 High dynamic range.

If we goes to design any analog circuit it is mandatory to known the some design
specification and that specification are standard and our goal is to achieve the desirable
result. CMOS technologies are the best way to design LNA. They provide high speed

8
operation, simplicity in fabrication and also low power consumption [8]. Frequency of
operation depends on different parameters like size of the transistors, impedance
values connected to the transistors, etc. Operating frequency also depends on the filter
connected to the input of the LNA.

1.5 LNA TOPOLOGIES

Common−source, common−gate, and cascode are three prevailing LNA topologies.

These topologies are widely used in the LNA to achieve to the desired results [6]. The
most preferred configuration for high-frequency LNA is common source topology
and cascode structure [3][6]. Multistage cascode structure LNA has the main
advantage of high gain as compared to single-stage LNA [9][10]. Common- Gate
topology provides a highly linear circuit but noise performance of this topology is
relatively low [6]. The overall noise figure of the circuit deteriorates with the addition
of different stages in LNA and the first stage plays an important role for obtaining
minimum noise figure as it directly gets added in the system’s overall noise figure
which can be seen through Friis noise equation mentioned as (1). Therefore, common
source is used at first stage and Cascode structures are used in next stages. Cascode
structure is defined as combination of common source and common gate[1].

Table 1. Comparison of Three LNA Topologies

Characteristic Common−Source Common−Gate Cascode

Noise Figure Lowest Rises rapidly with Slightly higher

frequency than CS

Gain Moderate Lowest Highest

Linearity Moderate High Potentially

Highest

Bandwidth Narrow Fairly broad Broad

Stability Often requires Higher Higher

compensation

9
 Reverse Isolation Low High High

Sensitivity to Greater Lesser Lesser

Temperature and
Power Supply

1.5.1 COMMON SOURCE WITH RESISTIVE FEEDBACK

In LNA design, combined structure of common source and resistive feedback are used
to overcome the limitation of each topology [8][16].
Following are the main advantages of CS topology with resistive feedback
 Better input and output impedance matching
 Acceptable values of S parameters
 Minimum noise figure
 Maintaining unconditional stability in the desired frequency range.

1.6 BIASING

After the accumulation of the circuit components as desired, we need to provide

biasing to give the device a stable operating point. If the biasing provided to the
circuit is not able to provide a stable operating point, it will ruin the circuit
performance at the desired frequency, and the circuit will become prone to
oscillations and this may destroy the circuit completely [6]. Hence, stability analysis
is very crucial for a device’s proper operation. Many methods are used to provide
biasing to the circuit such as resistive divider biasing, current mirror, etc. Out of these
methods, we prefer current mirror biasing as MOSFET current mirror tends to reduce
the chip area of the circuit and also provides a good stable operating point to our
device. After the design process is complete, we need to convert our design into end-
product which can be achieved by fabrication of the circuit. Before fabrication
process start. we need to perform simulations and analyze the stability of the circuit in
real time.

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1.7 MATCHING NETWORK

Impedance matching is an important aspect in RF circuits designing. Performance of

RF circuits depends on the input and output matching. In order to maximize power
transfer from source to load, matching impedances is required [2]. If the load
impedance is ZL, then for maximum power transfer source impedance Z S is equal to a
conjugate of load impedance as shown in equation (3).

ZS= ZL* (3)

The reflection coefficient Ґ is a normalized measure of the relationship between

source impedance and load impedance. Input and output impedance matching is given
by the input and output return loss. Return loss (RL) is the relationship between the
reflected power wave at a port to incident power wave at the same port.

1.7.1 L-TYPE MATCHING NETWORK

The L-match impedance matching circuit is one of the circuits used to match the
impedance between two points, usually a source and a load [2]. The circuit got its
name because the inductor and the capacitor form an L-shape (see schematic below).
Note that the inductor and capacitor can be interchanged depending on the input. If
we need to block direct current, then the capacitor is placed near the source.
Otherwise, the inductor is placed near the source, as seen in the schematic below.

Fig. 1.9 L-Type Matching Network

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1.7.2 Π-TYPE MATCHING NETWORK

π network using LC components, i.e. inductors and capacitors or even resistors and
capacitors can be arranged in ether a π. As suggested by its name, the basic π network
element has one series capacitor, and either side of it there is an inductor connected to
ground. Further network elements can be cascaded if a faster roll off rate is required

Fig. 1.10 π -Type Matching Network

The output voltage across the π filter is quite high making it suitable for the most
power related application where high voltage DC filters are required.
In a controlled RF environment, where higher frequency transmission is required, for
example in the GHz band, High-Frequency π filters are easy and flexible to make in
the PCB using just PCB traces. High-frequency Pi filters also provide surge
immunities more than the silicon-based filters. For instance, a silicon chip has a limit
of voltage withstand capacity, whereas π filters made using the passive components
have much more immunity in terms of surges and harsh industrial environments.

1.7.2 T-TYPE MATCHING NETWORK

12
 CHAPTER 2
LITERATURE REVIEW

S.No. REFERENCES FINDINGS LIMITATIONS

1. Cao, Zhiyuan, et al. "A K- This paper gives This paper have high
Band High-Gain LNA in maximum gain by NF and Power
0.13-µm RF CMOS." using cascode consumption and it
2019 IEEE International topology with inter- can be further
Symposium on Radio- stage matching improved
Frequency Integration
Technology (RFIT). IEEE,
2019.
2. Wang, Keping, and Hao For low input and Voltage gain is low
Zhang. "A 22-to-47 GHz output return losses, and it can be
2-Stage LNA With 22.2 L-type matching furthure improved
dB Peak Gain by Using network as well as π- by using CMOS
Coupled L-Type Interstage type matching technology instead
Matching Inductors." networks are used of SiGe and
IEEE Transactions on BiCMOS.
Circuits and Systems I:
Regular Papers 67.12
(2020): 4607-4617.
3. Vimalan, Lekshmi, and S. Low noise figure is Voltage gain is low
Devi. "Performance achieved by using and can be improved
Analysis of Various common source with the help of
Topologies of Common topology with resistive cascode topology
Source Low Noise feedback.
Amplifier (CS-LNA) at
90nm Technology." 2018

[1] Presents a K-band low-noise amplifier (LNA) for automotive radar applications.
The LNA features high gain and low noise using a 3-stage cascode topology, which

13
has been designed in a 0.13-μm RF CMOS. According to the measurement results, the
maximum gain is achieved. This paper have high NF and Power consumption and it
can be further improved by using common source topology at first stage. The input
and output return losses S11 and S22 are below than -10 dB.

In [2] a wideband low-noise amplifier (LNA) with coupled L-type interstage

matching inductors. The coupled inductors extend the bandwidth of LNA by moving
zeros to lower frequencies to cancel the effect of poles. Meanwhile, asymmetric L-
type inductors with different inductances can be designed separately to achieve better
gain flatness. In addition, the quality factor of coupled inductors is also slightly
improved without significantly changing their inductance. The LNA is fabricated in a
0.13-μm SiGe, BiCMOS technology. Noise Figure and gain, which can be further
improved. The measured input 1-dB gain compression point is stable in the entire 3-
dB gain bandwidth. The chip consumes a high power.
From [3], one of the basic components in any radio frequency (RF)
communication systems is Low Noise Amplifier (LNA). This paper compares various
Common Source Low Noise Amplifier (CS-LNA) topologies based on their
performance analysis. The three main common source LNA topologies that has been
taken for the performance analyses are an inductively loaded Common Source LNA.
A CS-LNA with feedback resistor and a CS-LNA cascode stage with inductive source
degeneration. In this paper, all the three LNA’s are designed which is generally used
for Global Positioning System (GPS) applications. The performance of these LNA
topologies are analyzed by comparing various aspects such as gain, Noise Figure
(NF), S parameters, stability and linearity of each circuit. The simulations are done at
90nm CMOS technology by using Cadence Virtuoso Spectre RF. Out of the three
topologies analyzed in this paper, the cascode CS-LNA with inductive source
degeneration provides high gain and low noise figure.

4. Li , Dongze, et al. "A 4- Here, the 90 nm Gain is low and total

mW Temperature-Stable CMOS technology is power consumption
28 GHz LNA with used to get low power of LNA circuit is
Resistive Bias Circuit for consumption along high
5G Applications." with high packing

14
 Electronics 9.8 (2020): density
1225
5. Kong, Sunwoo, et al. "A This paper presents a Gain and power
28-GHz CMOS LNA with LNA using boosting consumption can be
Stability-Enhanced G m- technique and improve further improved.
Boosting Technique Using stability.
Transformers." 2019 IEEE
Radio Frequency
Integrated Circuits
Symposium (RFIC). IEEE,
2019
6. Bansal, Malti, and Diksha The matching network Gain is low and total
Singh. "Different Input plays an important power consumption
Impedance Matching role to restrict the of LNA circuit is
Circuits for Cascode unnecessary power high and needs a
Common Source LNA loss due to which modification.
with Inductive obtained a very low
Degeneration Topology in output return loss.
45nm CMOS
Technology." 2019
International Conference
on Communication and
Electronics Systems
(ICCES). IEEE, 2019

[4] Presents, a low power two-stage single-end (SE) low-noise amplifier

(LNA) in 90 nm silicon-on-insulator (SOI) CMOS technology for 5G applications. In
this design, the influence of bias circuit is discussed. The resistor which was adopted
in bias circuit can feed DC voltage as well as keep whole circuit unconditionally
stable. The gate bias points are set to make the circuit low-power and temperature-
stable. Measurement results illustrated that the LNA achieved a maximum small
signal gain and an average noise figure (NF) in operating frequency band. Measured

15
S11 was below −10 dB and reverse isolation S12 was below −25 dB throughout the
band. It consumed average power by proper selection of bias point. The fabricated
LNA has demonstrated a gain variation of 3 dB and a NF variation from −40 °C to
125 °C. It suggests that the proposed SOI CMOS LNA can be a promising candidate
for 5G applications.

In [5] a low noise amplifier (LNA) using a g m -boosting technique with

improved stability using transformers in the millimeter-wave (mm-Wave) band. The
transformer composed of three inductors improves not only stability, but also gain and
low-noise performance of the LNA. The conditions for stability shows that the
proposed structure can guarantee good stability over a high frequency range [6]. The
chip was fabricated using the TSMC 65-nm CMOS process and it has an active chip
area. The fabricated LNA has average gain and average noise figure (NF). The
stability factor μ values is high at the source and load sides of the LNA. The 3-dB
bandwidth of the LNA is good.

In [6] various input impedance matching networks that can be used for cascode
common source LNA with inductive degeneration topology in 45 nm
CMOS technology. The matching networks being used and analyze their performance
using simulations. Based on our simulation results, we further conclude that T-
Matching network is the best input impedance matching network for
cascode common source LNA with inductive degeneration topology in 45 nm CMOS
technology
7. Castagnola, Juan L., et al. The input and output S-parameters can be
"A Novel Design and return losses should be improved by using
Optimization Approach below -10 dB and the transistors size and
for Low Noise Amplifiers stability factor should maintained size of
(LNA) Based on MOST be greater than 1 in the chip by reducing
Scattering Parameters and entire range of inductor size.
the gm/ID Ratio." frequency to get
Electronics 9.5 (2020): optimum performance
785.
8. Singh, Vikram, Sandeep The first stage plays S-parameters can be
K. Arya, and Manoj an important role for further improved by
Kumar. "Effect of resistive obtaining minimum using cascode

16
 feedback on performance noise figure as it topology instead of
parameters of common directly gets added in common gate.
source LNA." 2017 the system’s overall
International Conference noise figure. In first
on Computing, stage a CS transistor
Communication and with resistive feedback
Automation (ICCCA). is used instead of
IEEE, 2017. cascode structure due
to which noise figure
degrades abruptly.
9. Liu, Baohong, Genhua Multistage cascode High Noise Figure
Chen, and Ying Chen. "A structure LNA has the and DC power
24-GHz single-to- main advantage of consumption and it
differential LNA for K- high gain as compared can be improved by
band receiver to single-stage LNA. using common
applications." 2016 IEEE source trasnsistors.
International Conference
on Microwave and
Millimeter Wave
Technology (ICMMT).
Vol. 1. IEEE, 2016.

[7] Presents a new design methodology for radio frequency (RF) integrated circuits
based on a unified analysis of the scattering parameters of the circuit and
the gm/ID ratio of the involved transistors. Since the scattering parameters of the
circuits are parameterized by means of the physical characteristics of transistors,
designers can optimize transistor size and biasing to comply with the circuit
specifications given in terms of S-parameters . A complete design of a cascode low
noise amplifier (LNA) in MOS 65 nm technology is taken as a case study in order to
validate the approach. In addition, this methodology permits the identification of the
best trade-off between the minimum noise figure and the maximum gain for the LNA
in a very simple way.

In [8] effect of resistive feedback on performance parameters of Common-

Source (CS) low noise amplifier (LNA) is studied in this paper. For this purpose, an

17
ultra low power, low noise figure (NF), high power gain (S 21) low noise amplifier
(LNA) for narrowband (NB) wireless applications is proposed in this paper. The LNA
is designed for 2.4 GHz narrowband (NB) using 90nm CMOS process. It consists of a
resistive feedback Common-Source (CS) inductive degeneration main stage followed
by Common-Gate (CG) cascoded stage [8]. A series inter-stage inductor between the
main stage and the cascoded stage is used to achieve the low NF with desired stability
and power gain. The input return loss (S 1I) is high and output return loss (S 22) is very
low. The proposed LNA circuit provides acceptable values of input 1-dB compression
(P 2 dB) and input third-order intercept point (IIP3) as -32.8 dBm and IIP3 -18.5 dBm
respectively. The LNA consumes low DC power supply [8].

From [9] a 24 GHz single-to-differential LNA for K-band receiver applications

is presented. The proposed 24 GHz single-to-differential LNA is composed of three
stages: two cascode stages and one active balun stage. To reduce the power
dissipation of the circuit, the first two-stage is utilized as single-end signal and the last
stage is composed of common-source combined with common-gate to transform the
single-end signal to differential signal. The proposed LNA is implemented through
TSMC 0.18-μm 1P6M CMOS process. Simulation results show that the proposed
LNA can get average voltage gain and Noise Figure. Comparison between this work
and those published has been given for its feasibility. It's shown that this proposed
LNA is very suitable for K-band receiver applications.

10. J. Xu, Y. Na, C. Qiang, J. To achieve high Increases the overall

Gao, and X. Zeng, "A voltage gain, two stage power consumption.
3.4dB NF k-band LNA in cascade topology is
65nm CMOS technology," used in the LNA.
in IEEE International
Symposium on Circuits &
Systems, 2013.

18
 11. Wang, C., Hao, Y., Impedance matching The cascode stage
Haiying, Z., Kang, K. and technique is adopted has higher noise
Tang, Z., 2011, May. A to reduce noise figure figure and reverse
60GHz LNA with 4.7 dB and improve gain. isolation compared
NF and 18dB gain using to CS topology.
interstage impedance
matching technique in
90nm CMOS. In 2011
IEEE International
Conference on Microwave
Technology &
Computational
Electromagnetics (pp.
270-273). IEEE.
12. Murthy, BT Venkatesh, et The input and output Noise figure (NF)
al. "Ultra Low Noise matching circuits at will play a vital role
Figure, Low Power input and output will in the design as the
Consumption Ku-Band play a vital role in performance of the
LNA with High Gain for transferring maximum entire receiver will
Space Application." 2020 power from input to depend on the noise
5th International network and network figure of LNA.
Conference on to output respectively.
Communication and
Electronics Systems
(ICCES). IEEE, 2020.
From [10] the low cost, high integration level characteristics of CMOS process make
it attractive for fabricating RF circuits. As the dimension decrease of CMOS
transistors, the performance of CMOS process becomes sufficient for design
voluminous RF. To achieve high voltage gain, two stage cascade topology is used in
the LNA.

In [11] to obtain high gain and low NF, the input impedance match is very
important. For each of the LNA stages, two main structures, common source (CS) and
cascode were considered. Under the same power consumption, the simulated

19
maximum stable power gain of cascode topology is higher than common source (CS)
topology. However, the cascode stage has higher noise figure and reverse isolation
compared to CS topology.

In [12] the broadband and cost-effective LNA with low power consumption,
high gain and low NF are the goals. The RF input is fed to the input matching circuit.
The input and output matching circuits at the input and output respectively are playing
a crucial role in achieving desired parameters. The input and output matching circuits
at input and output will play a vital role in transferring maximum power from input to
network and network to output respectively [12]. The DC supply is fed at the gate and
drain of the transistor to achieve biasing. Noise figure (NF) will play a vital role in the
design as the performance of the entire receiver will depend on the noise figure of
LNA. Once NF is less, it influences on the other blocks to perform well [12].

13. Cho, K. F., & Wang, S. (2016, Gate inductive Gain can be more
July). A 0.4–5.3 GHz wideband peaking, resistive and Noise figure
LNA using resistive feedback feedback, and can be low
topology. In 2016 IEEE MTT-S source
International Conference on degeneration
Numerical Electromagnetic and inductive
Multiphysics Modeling and topologies to
Optimization (NEMO) (pp. 1- achieve the
2). IEEE. wideband matching
networks.
14. Bansal, Malti. "High linearity Resistive feedback Reverse isolation
and low noise shunt resistive topology with pi- can be improved
feedback CMOSLNA in 2.4 matched input
GHz ISM band." 2017 Recent provides low noise
Developments in Control, figure, moderate
Automation & Power gain and high
Engineering (RDCAPE). IEEE, linearity.
2017.
15. Aditi, Malti Bansal. "A high Shunt resistive High Noise figure
linearity and low noise shunt feedback CMOS
resistive feedback UWB LNA." low noise amplifier

20
 In 2017 Conference on (LNA) using a pi-
Information and matching network
Communication Technology has been designed
(CICT), pp. 1-5. IEEE, 2017. in this paper using
0.13μm CMOS
technology for
applications in
ultra-wideband
(UWB) systems.

In [13] a compact resistive-feedback CMOS low-noise amplifiers (LNA) is presented

for wideband applications. The LNA is based on a common source (CS) amplifier
with gate inductive peaking, resistive feedback, and source degeneration inductive
topologies to achieve the wideband matching networks. The LNA is fabricated in a
standard 0.18-µm RF CMOS technology.

In [14] A shunt resistive feedback CMOS low noise amplifier (LNA) using a
pi-matching network has been designed in this paper using 0.13 m CMOS technology.
The low noise amplifier is optimized for working in the 2.4 GHz frequency band
range. The shunt resistive feedback topology with pi-matched input provides low
noise figure, moderate gain and high linearity. Advanced Design System (ADS)
software is used for simulation.

[15] Presents a shunt resistive feedback CMOS low noise amplifier (LNA)
using a pi-matching network has been designed in this paper using 0.13μm CMOS
technology for applications in ultra-wideband (UWB) systems. This LNA has a low
noise figure and the maximum linearity of 3 dBm with moderate gain is achieved
simultaneously, when operated at 1.2 V power supply, with a 3-dB bandwidth ranging
from 3.1 GHz to 10.6 GHz.

16. Singh, V., Arya, S. K., & It consists of a More stability can
Kumar, M. (2017, May). Effect resistive feedback be achieved.
of resistive feedback on Common-Source
performance parameters of (CS) inductive
common source LNA. In 2017 degeneration main
International Conference on stage followed by

21
 Computing, Communication Common Gate
and Automation (ICCCA) (pp. (CG) cascoded
298-303). IEEE. stage. A series
inter-stage
inductor between
the main stage and
the cascoded stage
is used to achieve
the low NF with
desired stability
and power gain.
17. Liao, Wei-Rern, and Jeng-Rern Common source More reverse
Yang. "A 0.5–3.5 GHz (CS) cascade isolation can be
wideband CMOS LNA for LTE amplifier with achieved.
application." In 2016 IEEE resistive feedback
International Meeting for that is used to do
Future of Electron Devices, input matching
Kansai (IMFEDK), pp. 1-2. and reduce the
IEEE, 2016. noise figure
18. Singh, Vikram, Sandeep K. Common gate Average noise
Arya, and Manoj Kumar. "A 0.7 cascade topology figure and
V, Ultra-Wideband Common for wideband input appreciable
Gate LNA with Feedback Body matching and body voltage gain.
Bias Topology for Wireless biasing for
Applications." Journal of Low reducing power.
Power Electronics and
Applications 8.4 (2018): 42.

In [16] effect of resistive feedback on performance parameters of Common-Source

(CS) low noise amplifier (LNA) is studied in this paper. For this purpose, an ultra low
power, low noise figure (NF), high power gain (S21) low noise amplifier (LNA) for
narrowband (NB) wireless applications is proposed in this paper. The LNA is
designed for narrowband (NB) using 90nm CMOS process. It has a 3-dB bandwidth
of 2.189 – 2.637 GHz. It consists of a resistive feedback Common-Source (CS)
inductive degeneration main stage followed by Common Gate (CG) cascoded stage. A

22
series inter-stage inductor between the main stage and the cascoded stage is used to
achieve the low NF with desired stability and power gain. The proposed LNA circuit
provides acceptable values of input 1-dB compression (P1dB) and input third-order
intercept point (IIP3).

[17] presents a wideband CMOS low noise amplifier (LNA) for LTE
application. The LNA design is based on a common source (CS) cascade amplifier
with resistive feedback that is used to do input matching and reduce the noise figure.
Source follower and LC series resonances are used to do output matching. The LNA
achieves the average gain and low noise figure (NF). The LNA is fabricated with
TSMC 0.18-µm CMOS process. The chip size is 0.6mm*0.8mm.

In [18] an ultra-wideband (UWB) low noise amplifier (LNA) for 3.3–13.0 GHz
wireless applications using 90 nm CMOS is proposed in this paper. The proposed
LNA uses an improved common-gate (CG) topology utilizing feedback body biasing
(FBB), which improves noise figure (NF) by a considerable amount. Parallel-series
tuned LC network was used between the common-gate first stage and the cascoded
common-source (CS) stage to achieve the maximum signal flow from CG to CS stage.
Improved CS topology with a series inductor at the drain terminal in the second stage
connected and cascoded CS third stage provides high power gain (S21) and bandwidth
enhancement throughout the complete UWB. A common-drain buffer stage at the
output provides high output reflection coefficient (S22). It achieves an average power
gain and low noise figure with a very high reversion isolation (S12).

19. Singh, V., & Rattan, M. (2016). Forward body bias Noise figure
Ultra wide band low noise is used for low increase and gain
amplifier with self-bias for power dissipation. decreases after
improved gain and reduced providing forward
power dissipation. 2016 body bias to
International Conference on circuit.
Computing, Communication and
Automation (ICCCA).
20. Suganthi, K., and S. Malarvizhi. Analysis of Noise Figure and
"Analysis and design of low‐ cascode Topology, gain can be

23
 power and high‐gain Degenerative improved by using
complementary metal oxide inductor provide common source
semi‐conductor low noise stability and multi-stage
amplifier operating at 28 GHz cascode.
frequency for millimeter wave
LEOS, local multiport
distribution system and radar
application." Transactions on
Emerging Telecommunications
Technologies: e3950

From [19] the ultra wide band low noise amplifier (LNA) with three stages based on
CMOS technology. In this LNA, first stage is designed on current reuse topology to
achieve higher gain, while second stage is complementary push pull configuration in
self biased state, which provides high gain and low noise contribution and the third
stage is common source stage. This paper proposes two different designs. These
designs are optimized for different set of parameters, which makes them suitable for
two different categories of applications. The first design with single power source, is
able to achieve average gain with low noise figure. While second design achieves
reduction in the power dissipation and enhances input output impedance matching.
Power dissipation of the second design is 4.1 mW only. Both Ultra Wide Band Low
Noise Amplifiers (UWBLNA) are designed and simulated using TMSC 130 nm
CMOS technology.

In [20], Low-noise amplifier supports broadband standards with the advantage

of low-power, high-gain, and low noise figure (NF). The low-frequency design of this
low-noise amplifier (LNA) is used for multistandard wireless applications and the
high-frequency design of this LNA can be used in millimeter wave radar applications.
This LNA is designed at the front-end for amplification in the receiver side, so that
signal to noise is adjusted on the multistandard receivers. LNA permits performance
of the design with various parameters like NF, power efficiency, gain of the LNA,
figure of merits, and linearity of the low-noise amplifier. In 28 GHz, millimeter wave
(mmW) circuits' design and analysis with high gain, low power, low NF, and wide
bandwidth are preferred for radio frequency front end. This paper discusses, the
24
 Cascode design of CMOS LNA circuit at 28 GHz, and the novelty of the design is
that it can operate at
two different set of frequency bands (21 and 28GHz) and it is multiband and
multitunable. This has a average gain and NF. The input and output reflection
coefficients are S11 ≤−10 dB and S22 ≤−10 dB. Electromagnetic simulation is
performed using advanced design system tool. Output power of the proposed design is
2 dBm, transition frequency (f T) is 64GHz. The observed results show that the
proposed CMOS LNA design finds its suitability in mmW cloud radar application
ofmono-pulse radar system and radar front-end receiver circuits [20].
.

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